JPS60210032A - Automatic equalizer - Google Patents

Automatic equalizer

Info

Publication number
JPS60210032A
JPS60210032A JP6723684A JP6723684A JPS60210032A JP S60210032 A JPS60210032 A JP S60210032A JP 6723684 A JP6723684 A JP 6723684A JP 6723684 A JP6723684 A JP 6723684A JP S60210032 A JPS60210032 A JP S60210032A
Authority
JP
Japan
Prior art keywords
output
automatic
equalizer
automatic equalizer
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6723684A
Other languages
Japanese (ja)
Inventor
Kenji Inoue
井上 憲治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6723684A priority Critical patent/JPS60210032A/en
Publication of JPS60210032A publication Critical patent/JPS60210032A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03012Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03114Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
    • H04L25/03133Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a non-recursive structure
    • H04L25/0314Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a non-recursive structure using fractionally spaced delay lines or combinations of fractionally integrally spaced taps

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To set the optimum tap weight by providing an automatic gain controller between the output of an automatic equalizer and a deciding device in order to correct the attenuation of the data output. CONSTITUTION:The input signal given from an input terminal 1 of an automatic equalizing device is supplied to an automatic equalizer 3. Then an equalized signal is supplied to a deciding circuit 4 from an output terminal 6 via an automatic gain control circuit 15. The circuit 4 decides the closest transmission data point and delivers it to a decision output terminal 2 and also to a terminal at one side of a subtractor 5. While the output of the equalizer 3 is supplied to the other terminal of the subtractor 5. Then an error signal given from the subtractor 5 is applied to a tap weight controller of the equalizer 3. The attenuation of the data output of the equalizer 3 is corrected by the circuit 15. Thus the characteristics of the automatic equalizing device are improved in the case of large circuit distortions.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、最小2乗誤差法によるデータ伝送用ベースバ
ンド自動等化装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a baseband automatic equalization device for data transmission using a least square error method.

〔従来技術の説明〕[Description of prior art]

従来の最小2乗誤差法によるデータ伝送用ベースバンド
自動等化方式について図を参照して説明する。第1図は
最小2乗誤差法によるベースバンド自動等化方式を示す
図であり、1は入力端子、2は判定出力端子、3は自動
等化器、4は判定回路、5は減算器である。回線によっ
て線形歪を受けたベースバンド信号は入力端子1より入
力され、自動等化器3によって等化される。その出力は
、判定回路4に送られ、そこでもっとも近い送信データ
点が見つけられ、判定出力端子2に出力される。一方、
自動等化器3の出力と、判定回路4の出力は減算器5に
よって差をとることにより、誤差信号が作られ、自動等
化器3に供給され、タップ重みの修正に使用される。
A conventional baseband automatic equalization method for data transmission using the least squares error method will be explained with reference to the drawings. Figure 1 is a diagram showing a baseband automatic equalization method using the least squares error method, where 1 is an input terminal, 2 is a judgment output terminal, 3 is an automatic equalizer, 4 is a judgment circuit, and 5 is a subtracter. be. A baseband signal that has been subjected to linear distortion due to the line is input from an input terminal 1 and is equalized by an automatic equalizer 3. Its output is sent to the decision circuit 4, where the nearest transmitted data point is found and output to the decision output terminal 2. on the other hand,
A subtracter 5 takes the difference between the output of the automatic equalizer 3 and the output of the determination circuit 4 to create an error signal, which is supplied to the automatic equalizer 3 and used to modify the tap weights.

第2図は自動等化器3の詳細図であり、1は入刃端子、
6は出力端子、7は誤差信号入力端子、8−1〜8−3
は遅延回路、9−1〜9−3は乗算器、10−1〜10
−3はタップ重み、11は係数器、12−1〜12−3
は乗算器、13−1〜13−3は減算器、14は加算器
である。入力端子1より入力された信号は遅延回路8−
1〜8−3に順次シフトされ入力される。各遅延回路8
−1〜8−3の出力は各タップ重み10−1〜10−3
と各々乗算され、その各々の出力は加算器14によって
加算され、出力端子6に出力される。一方、誤差信号入
力端子7より入力された誤差信号は、係数器11によっ
て定数倍される。その出力は、乗算器12−1〜12−
3によって、各遅延回路8−1〜8−3の出力と各々乗
算され、その出力値分だけ、減算器13−1〜13−3
ニよッテ各タップ重ミl0−1〜10−3は減算される
ことによって修正される。
FIG. 2 is a detailed diagram of the automatic equalizer 3, in which 1 is a blade terminal;
6 is an output terminal, 7 is an error signal input terminal, 8-1 to 8-3
is a delay circuit, 9-1 to 9-3 are multipliers, 10-1 to 10
-3 is tap weight, 11 is coefficient unit, 12-1 to 12-3
is a multiplier, 13-1 to 13-3 are subtracters, and 14 is an adder. The signal input from input terminal 1 is sent to delay circuit 8-
The signals are sequentially shifted from 1 to 8-3 and input. Each delay circuit 8
-1 to 8-3 outputs each tap weight 10-1 to 10-3
and their respective outputs are added by the adder 14 and output to the output terminal 6. On the other hand, the error signal input from the error signal input terminal 7 is multiplied by a constant by the coefficient multiplier 11. The outputs of multipliers 12-1 to 12-
3 is multiplied by the output of each delay circuit 8-1 to 8-3, and the subtracters 13-1 to 13-3 are multiplied by the output value.
The weights of each tap 10-1 to 10-3 are corrected by subtraction.

したがって、従来の最小2乗誤差法による自動等化方式
は、自動等化器出力において、残留符号間干渉分が若干
残り、本来のデータも減衰し、それだけ伝送信号の誤り
率が大きくなる欠点を有していた。
Therefore, the conventional automatic equalization method using the least squares error method has the disadvantage that some residual intersymbol interference remains at the output of the automatic equalizer, and the original data is also attenuated, increasing the error rate of the transmitted signal. had.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記欠点を解消し、最適なタップ重み
を設定する自動等化方式を提供することを目−的とする
SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic equalization method that eliminates the above drawbacks and sets optimal tap weights.

〔発明の特徴〕[Features of the invention]

本発明は、等化層出力と送信信号の2乗平均誤差を評価
関数とし、これを最小にするようにタップ係数を逐次修
正する。最小2乗誤差法による自動等化方式では、最適
タップ重みの場合の2乗平均誤差によって本来のデータ
の出力にも減衰がみられる。このレベル変動は回線の鳴
音発生の原因になるどともに、過負荷、雑音劣化の原因
となるので、本発明の自動利得調整器を自動等化器、の
出力に付加することによって、極力レベル変動を抑え、
上記の本来のデータ信号の減衰骨を補正することを特徴
とする。
In the present invention, the root mean square error between the equalization layer output and the transmission signal is used as an evaluation function, and the tap coefficients are successively modified so as to minimize this. In the automatic equalization method using the least squares error method, attenuation is also seen in the original data output due to the mean square error in the case of optimal tap weights. This level fluctuation causes line noise, overload, and noise deterioration, so by adding the automatic gain adjuster of the present invention to the output of the automatic equalizer, it is possible to reduce the level as much as possible. Reduce fluctuations,
The present invention is characterized by correcting the attenuation of the above-mentioned original data signal.

すなわち、自動等化器と、その出力を判定する判定回路
と、上記自動等化器の出力と上記判定回路の出力とから
誤差信号を作り出し、上記自動等化器の伝送特性の制御
を行う手段とを備え、上記自動等化器は最小2乗誤差法
による伝送特性の等化手段を含むデータ伝送用ベースバ
ンド自動等化装置において、上記自動等化器の出力と上
記判定器との間に自動利得調整器を備えたことを特徴と
する。
That is, an automatic equalizer, a determination circuit for determining its output, and means for generating an error signal from the output of the automatic equalizer and the output of the determination circuit to control the transmission characteristics of the automatic equalizer. In the baseband automatic equalization device for data transmission, the automatic equalizer includes means for equalizing transmission characteristics using the least squares error method, and the automatic equalizer has a transmission characteristic between the output of the automatic equalizer and the determiner. It is characterized by being equipped with an automatic gain adjuster.

〔実施例による説明〕[Explanation based on examples]

本発明の実施例を図面に基づいて説明する。第3図は実
施例方式が利用された装置のブロック構成図である。入
力端子1から入力した入力信号は自動等化器3に入力し
、さらにその出力端子から出力した信号は自動利得調整
器15をへて判定回路4に送られ、そして判定出力端子
2に出力される一方、自動等化器3の出力と判定回路4
の出力は共に減算器5に入力し、さらにその出力は自動
等化器3のタップ重みの制御装置に接続されている。
Embodiments of the present invention will be described based on the drawings. FIG. 3 is a block diagram of an apparatus in which the embodiment method is used. The input signal input from the input terminal 1 is input to the automatic equalizer 3, and the signal output from the output terminal is further sent to the judgment circuit 4 through the automatic gain adjuster 15, and then output to the judgment output terminal 2. On the other hand, the output of the automatic equalizer 3 and the judgment circuit 4
Both outputs are input to a subtracter 5, and the output thereof is further connected to a tap weight control device of the automatic equalizer 3.

一般に送信シンボルをa、1、伝送路のインパルス応答
をり6、自動等化器のタップ重みをCt、自動等化器の
出力をyll、誤差信号を07とすると、自動等化器の
入力信号x7は xll−Σakh n−k−−−−−−−−(1)とか
ける。また y7=Σct X□。
In general, if the transmission symbol is a, 1, the impulse response of the transmission path is 6, the tap weight of the automatic equalizer is Ct, the output of the automatic equalizer is yll, and the error signal is 07, then the input signal of the automatic equalizer is x7 is multiplied by xll-Σakh n-k---(1). Also, y7=Σct X□.

=Σakρn −k−−−−−−−(2)但しρアーΣ
c、h、。
=Σakρn −k−−−−−−−(2) However, ρaΣ
c,h,.

であり、また判定回路によって判定誤りがないとすれば 6 n =3’ n a n −−−−−−−−(3)
となる。最小2乗誤差法は誤差信号e7の2乗平均誤差
が最小になるようにするアルゴリズムであり、 E、(en”〕 −・・・・−−−−−(41 E (an ” ) なるεを最小にすることが目的である。ここでE()は
集合平均を意味する。
And if there is no judgment error by the judgment circuit, then 6 n = 3' n a n −−−−−−−−(3)
becomes. The least squares error method is an algorithm that minimizes the mean square error of the error signal e7. The objective is to minimize , where E() means the ensemble average.

一連の計算によって、最適タップ重みの場合の2乗平均
誤差ε。1は ε。□−1−ρ。 間−曲(5) と表わすことができる。
Through a series of calculations, the root mean square error ε for the optimal tap weights. 1 is ε. □−1−ρ. It can be expressed as: (5).

ここでρ7は、伝送路と自動等化器の総合インパルス応
答であり、ρ。はそのピーク値を示す。
Here, ρ7 is the total impulse response of the transmission line and automatic equalizer, and ρ. indicates its peak value.

したがって、その場合、(2)式より yrl=Σak ρn−k (5)式を代入して −−−−−・−(6) となる。Therefore, in that case, from equation (2), yrl=Σak ρn−k (5) Substituting Eq. --------・-(6) becomes.

(6)式の第1項が自動等化器出力においての本来のデ
ータであり、第、2項は残留符号間干渉分である。
The first term in equation (6) is the original data at the automatic equalizer output, and the second and second terms are the residual intersymbol interference.

本発明の特徴囚するところは第3図の一点鎖線に囲まれ
たところで、自動等化器3と判定回路4の間に自動利得
調整器15を挿入したことであり、上記(6)式によっ
て表わせるように本来のデータの出力における減衰骨(
1−ε。pt )分を補正し、レベル変動を極力抑える
ことによりて誤り率の増加を防ぐことにある。
The feature of the present invention is that an automatic gain adjuster 15 is inserted between the automatic equalizer 3 and the judgment circuit 4 in the area surrounded by the dashed line in FIG. Attenuated bones in the original data output (
1-ε. pt) and suppress level fluctuations as much as possible to prevent an increase in the error rate.

入力端子1に入力した入力信号は、自動等化器3によっ
て自動等化され、その出力は自動利得調整器15によっ
てデータ点の平均電力が一定となるように利得制限され
る。その出力は判定回路4に送られ、もっとも近い送信
データ点が見つけられ、その判定出力値が判定出力端子
2に出力される。
The input signal input to the input terminal 1 is automatically equalized by the automatic equalizer 3, and its output is gain limited by the automatic gain adjuster 15 so that the average power of the data points is constant. The output is sent to the decision circuit 4, the closest transmission data point is found, and its decision output value is output to the decision output terminal 2.

一方、自動等化器3の出力と判定回路4の出力は、減算
器5によって差をとり誤差信号となり、自動等化器3の
タップ重みの修正に利用される。
On the other hand, the output of the automatic equalizer 3 and the output of the determination circuit 4 are subtracted by a subtracter 5 to become an error signal, which is used to correct the tap weight of the automatic equalizer 3.

〔発明の効果〕〔Effect of the invention〕

本発明は、自動等化器の出力に自動利得調整器を備える
ことにより、本来のデータの出力における減衰骨を補正
し、回線歪の大きな場合の自動等化器の特性を改善する
ことができる。
By providing an automatic gain adjuster at the output of the automatic equalizer, the present invention can correct the attenuation in the original data output and improve the characteristics of the automatic equalizer when line distortion is large. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の自動等化方式を示すブロック構成図。 第2図は自動等化器の詳細を示すブロック構成図。 第3図は本発明の一実施例を示すブロック構成図。 1・・・入力端子、2・・・判定出力端子、3・・・自
動等化器、4・・・判定回路、5・・・減算器、6・・
・出力端子、7・・・誤差信号入力端子、8−1〜8−
3・・・遅延回路、9−1〜9−3・・・乗算器、10
−1〜10−3・・・タップ重み、11・・・係数器、
12−1〜12−3・・・乗算器、13−1〜13−3
・・・減算器、14・・・加算器、15・・・自動利得
調整器回路。 特許出願人日本電気株式会社 代理人 弁理士 井 出 直 孝 尼1(21 級 Q 闘
FIG. 1 is a block diagram showing a conventional automatic equalization method. FIG. 2 is a block diagram showing details of the automatic equalizer. FIG. 3 is a block diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Judgment output terminal, 3... Automatic equalizer, 4... Judgment circuit, 5... Subtractor, 6...
・Output terminal, 7...Error signal input terminal, 8-1 to 8-
3... Delay circuit, 9-1 to 9-3... Multiplier, 10
-1 to 10-3...Tap weight, 11...Coefficient unit,
12-1 to 12-3...multiplier, 13-1 to 13-3
...Subtractor, 14...Adder, 15...Automatic gain adjuster circuit. Patent applicant NEC Co., Ltd. Patent attorney Takashi Ide 1 (21st class Q)

Claims (1)

【特許請求の範囲】 11) 自動等化器と、 その出力を判定する判定回路と、 上記自動等化器の出力と上記判定回路の出力とから誤差
信号を作り出し、上記自動等化器の伝送特性の制御を行
う手段と を備え、 上記自動等化器は最小2乗誤差法による伝送特性の等化
手段を含む データ伝送用ベースバンド自動等化装置において、 上記自動等化器の出力と上記判定器との間に自動利得調
整器を備えた ことを特徴とする自動等化装置。
[Claims] 11) an automatic equalizer; a determination circuit for determining its output; and an error signal generated from the output of the automatic equalizer and the output of the determination circuit, and transmitted by the automatic equalizer. A baseband automatic equalizer for data transmission including means for equalizing transmission characteristics using a least squares error method, wherein the automatic equalizer has an output of the automatic equalizer and An automatic equalization device characterized by comprising an automatic gain adjuster between the determiner and the determiner.
JP6723684A 1984-04-03 1984-04-03 Automatic equalizer Pending JPS60210032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6723684A JPS60210032A (en) 1984-04-03 1984-04-03 Automatic equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6723684A JPS60210032A (en) 1984-04-03 1984-04-03 Automatic equalizer

Publications (1)

Publication Number Publication Date
JPS60210032A true JPS60210032A (en) 1985-10-22

Family

ID=13339076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6723684A Pending JPS60210032A (en) 1984-04-03 1984-04-03 Automatic equalizer

Country Status (1)

Country Link
JP (1) JPS60210032A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01218218A (en) * 1988-02-26 1989-08-31 Nec Corp Automatic equalizer
EP0554120A2 (en) * 1992-01-31 1993-08-04 Fujitsu Limited Adaptive transversal equalizer
US5291522A (en) * 1990-07-05 1994-03-01 Fujitsu Limited Device and method for estimating sampled value of impulse response and signal reproduction system using the device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01218218A (en) * 1988-02-26 1989-08-31 Nec Corp Automatic equalizer
US5291522A (en) * 1990-07-05 1994-03-01 Fujitsu Limited Device and method for estimating sampled value of impulse response and signal reproduction system using the device
EP0554120A2 (en) * 1992-01-31 1993-08-04 Fujitsu Limited Adaptive transversal equalizer
EP0554120A3 (en) * 1992-01-31 1994-01-19 Fujitsu Ltd
US5598433A (en) * 1992-01-31 1997-01-28 Fujitsu Limited Automatic equalizer and data mode convergence method

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