JPS60206221A - Programmable logic array - Google Patents

Abstract

PURPOSE:To obtain an optionally programmable circuit which is integrated in circuit to a high degree by allowing input to an input signal line in two directions, providing a switch means for cutting off an input signal among lattice points of the input signal line, and programming even disconnection points to realize convolution. CONSTITUTION:Disconnection selection lines 12 and 212 are held at ''H'' for a disconnection selecting circuit 1. When this selection line is held at ''L'', an input signal line 31 is disconnected at positions 1 in figures (b) and (d) by TRs 4 and 5 in a figure (a). This circuit is constituted as shown in the figure (d), and then when disconnection selection lines 12, 212, and 612 in the figure (d) are held at ''L'', the lines are disconnected at positions 1 and 3 in the figures (b) and (d); and an input signal is sent from the other input side of the disconnected input signal line 31 to realize convolution shown in the figure (b). Further, lines 13 and 313 are held at ''L'' and then when disconnections are made at positions 2 in the figure (b) and (d), an arithmetic speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to Which the Invention Pertains] The present invention relates to a programmable logic array in which it is possible to select whether or not to disconnect an input line by an external signal, thereby allowing programmable convolution.

[Prior art and its problems]

Traditionally, when creating a mask, the pattern of the array intersections is determined (in PLA, there are many unused grid points in the array (and the disadvantage is that they take up wasted space, so the pattern is cut in advance). The results are improved by performing convolution (folding).

Furthermore, a programmable PLA whose logic circuit can be programmed using external input signals has been proposed (
For example, JP-A-56-91534). However, with programmable PLA, if the input signal line is cut for convolution, the signal line must be used with it cut, so Serino's programmable PLA cannot be used effectively. occurs.

[Purpose of the invention]

The present invention first improves the above-mentioned drawbacks by making the cut points also programmable when performing convolution in a programmable PLA.

It is an object of the present invention to provide a circuit device with a high degree of integration and which can be arbitrarily programmed.

A second purpose is to disconnect unnecessary long circuits using external input signals to increase calculation speed.

[Summary of the invention]

The present invention is characterized in that the input signal line can be input from both directions, and that electrical switch means for switching off the input signal is provided between each grid point of the input signal line.

For example, an input signal line cutting circuit (hereinafter referred to as a cutting one-factor selection circuit) whose input information is a cutting selection line parallel to each product term line of PLA and a cutting selection line parallel to each input signal line/phase term line. call)
is placed between each grid point on the input signal line. The programmer can cut at the desired position by searching for a cutting selection line that emits a signal to be input to the cutting selection circuit between the lattice points to be cut, and inputting a predetermined signal there. The input signal line allows input from both directions, and convolution is achieved by inputting a human input signal that does not share the cut input signal on one side and the product term line from the other side.

Each cutting selection line has a latch and can be used as is until it is rewritten with the next cutting data.

Also, if there are multiple unprogrammed grid points at the end of the input signal line, use the method described above.

By cutting the input signal line, it is possible to increase the calculation speed by one page.

〔Effect of the invention〕

According to the present invention, in a programmable PLA, convolution can be performed using an external input signal, and the cut point can be arbitrarily changed by simply changing the input value of the signal. In addition, unused lines can be cut and shortened (by doing so, the wiring can be minimized and the calculation speed can be increased.

[Embodiments of the invention]

First, an outline of the first embodiment will be described. At the end of each cut selection line 111-114, 212, 313, 612, 614 in FIG. 4 is a latch A as shown in FIG. Human force line 30-33. Phase term line 34.35 and product term @21~
The intersection points of 25 are called lattice points, and the lattice points marked with black circles are:
Perform logical product or logical sum.

Each grid point can be repeatedly rewritten to connect or disconnect. For example, in Japanese Patent Application Laid-Open No. 56-91534-6, a flip-flop and a gate circuit are provided at each lattice point, and the vc of each lattice point is determined by the contents of the flip-flop.
Connection/disconnection is restricted. FIG. 8 is a detailed view of 40 in FIG. 9 is a detailed diagram of the lattice points in Japanese Patent Application Laid-Open No. 56-91534, and 10 is a flip-flop. There are cutting selection circuits 1 to 3 between the valley grid points. FIG. 1 is a detailed diagram of an embodiment of the disconnection selection circuit 1. In FIG. @ In Figure 4, for the disconnection selection circuit 1, the normal disconnection selection circuit 12 and 212
is at a high level. Cutting line selection line 12 and 21
When transistor 2 is set to low level, transistor 4 in FIG.
and 5 become non-conductive, and the human input signal line 31 is cut off at the position 1 in FIGS. 2 and 4. This kind of circuit can be used as the fourth
By configuring as shown in the figure, @4 cut selection line 1 in figure
If 2゜212.612 is set to low level Dalian, it will be cut at 1 blue at 1.3 in Figures 2 and 4, and the input signal will also be input from the other side of the cut human power signal line 31. By sending the signal, the convolution shown in Figure 2 is realized.

If the position 2 in FIGS. 2 and 4 is cut off by setting the signal 13, 313 to a low level, it is possible to speed up the calculation linkage.

FIG. 45 is a schematic diagram of a second embodiment of the invention.礪4
The same parts as in the figure are given the same symbols. Logical products or logical sums are performed at the grid points marked with black circles. In such a circuit, a cutting selection circuit is provided between each grid point. Each cut selection circuit 1-3 has one cut selection line. Figure 6 is a detailed diagram of the cut selection circuit. When the cut selection line 212, which is normally at a high level, changes to a low level, transistors 4 and 5 become non-conductive, and the input signal line is changed to a low level.
It is cut at position 1 in the figure. By configuring such a circuit as shown in FIG.
If 2 is set to low level, 1 in Figure g2 and Figure 5.
．． The convolution shown in FIG. 2 is realized by cutting at position 3 and sending the input signal from the other side of the input signal line 31 as well.

In addition, the calculation speed can be increased by setting the signal to 313 at a low level and cutting at the 2's digit.

Each disconnect select line has a latch that holds the signal.

FIG. 3 shows an example of the latch shown in the above embodiment. 6 is a cutting information control line. When a high level signal is input to the cutting information line 6, the clocked inverter 11 is guided to select cutting. The next signal input to the line is read and this PLA
is rewritten to a new logic circuit, and when a low level signal is input to the disconnection information tllJ control line 6, the clocked inverter 11 becomes conductive from non-conducting 10, and this logic circuit remains in its previous state.

The disconnection/large-scale circuit shown in FIG. J1 and the latch circuit shown in FIG. 3 are not limited to this method (other methods can also be used).

FIG. 7 shows another embodiment of the circuit shown in FIG. In FIG. 7, normally, a low level signal is input manually to the cutting selection line 12.2121, and when disconnecting, a high level signal 1g is input.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a selective disconnection circuit, FIG. 2 is a plan view explaining the invention in detail, FIG. 3 is a circuit diagram of a latch circuit, and FIG. 4 is a circuit diagram of a latch circuit.
The figure is a circuit diagram of the first embodiment of the present invention, FIG. 5 is a circuit diagram of the second embodiment, FIG. 6 is a circuit diagram of its selective disconnection circuit, and FIG. 7 is a circuit diagram of another embodiment. , FIG. 8 is a partially enlarged circuit diagram. In the figure, 21 to 25...product term lines, 30 to 33...signal input lines. 11-14, 111-614... cutting selection line, 4.
5...H channel transistor, 34.35...
Aangang spelling. 6...Disconnection information control line, 8...P channel I transistor. Representative Patent Attorney Nori Yu Chika (and 1 other person) Figure 1 Figure 2 Figure 5 zS ~ 23 22 21 Figure 6 Figure 7

Claims (1)

[Claims] In a programmable logic array in which connection/disconnection of grid points can be written using input signals from an external source, the input signal can be input from both directions, and human input can be applied between each grid point of the human input signal line. A programmable logic array characterized by being provided with an electrical switch means for cutting off a signal.