JPS6020574A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To accelerate the switching operation especially shortening the storage time by a method wherein the impurity concentration of an electrode fetching part such as a base electrode etc. is lowered. CONSTITUTION:Base regions are not formed in series so that the impurity concentration at the base regions 2a-2d to be junctioned with metallic electrodes 4a-4d as the fetching parts of base electrode may be lowered but provided with the parts to be formed corresponding to individual emitter regions 3a-3d or to be formed individually. When base electrode fetching parts are formed through these procedures, the impurity in the region 2A (parasitic diode region) excluding the part 2B immediately below the emitter region required for transistor operation being very little, in case the transistor is saturated, the minor carriers injected from the region 2A to collector region 1 may be reduced to shorten the storage time especially out of the switching characteristics.

Description

[Detailed description of the invention] The present invention relates to improving the performance of semiconductor devices.

Among conventional semiconductor devices, the structure of a bipolar (NPN) transistor in particular is shown in FIG. This transistor 1 includes a collector region 1 consisting of an N+ type semiconductor layer and an N type semiconductor layer, a base region 2, and emitter regions 3a, 3b, and 3c.
...and the metal electrode 4a.

4b, 4c, 4d-, 5a, 5b, 5c, 5d-, 6゜7 Generally, the emitters 3a to 3c have a comb-like or lattice-like shape, and the emitter-base junction part (hereinafter referred to as peripheral length) is made as long as possible to obtain high output characteristics. Note that 8 is a field silicon oxide film. In the above conventional example, the base region 2't%%t% is formed by planar diffusion, so the closer it is to the surface, the higher the concentration is. The higher the concentration, the more this part operates as a parasitic diode, impeding high speed performance.

This will be explained in detail using FIGS. 2 and 3.

FIG. 2 is an equivalent circuit diagram of the transistor in consideration of a diode D parasitic to the transistor.

That is, the transistor Q in FIG. 1 is represented by a circuit in which a diode D is inserted between its base B and collector C. In this transistor, when it is in the on state, that is, in the saturated state, the potential of the base B is higher than the potential of the collector C, and the parasitic diode D is biased in the forward direction.
Minority carriers are injected into the collector region 1 through
Accumulation time t8 when turning off the transistor (9 when collector current 1° is turned on after base current ■8 is reversed)
The time it takes for the voltage to drop to 0% is long, reducing the switching speed.

It is already known that one way to reduce the amount of minority carriers injected from the parasitic diode is to lower the impurity concentration in the entire base region. However, when forming by planar diffusion, it is unavoidable that the concentration is highest near the surface.

The present invention has been made in view of the above points, and it is possible to reduce the concentration of the base region formed other than directly under the emitter M conductor layer by directional diffusion toward b' of the base region formed by planar diffusion. Therefore, the injection of minority carriers from the base region to the collector region is reduced,
It is an object of the present invention to provide a semiconductor device that can shorten switching time, especially storage time t8, by minimizing carrier storage, and a method for manufacturing the same.

The semiconductor device of the present invention has a second semiconductor layer of a conductivity type opposite to that of the semiconductor layer in a first semiconductor layer of a -conductivity type, and a region in the second semiconductor layer at a depth halfway from the surface of the second semiconductor layer. a third semiconductor layer having the same conductivity type as the first semiconductor layer; the second semiconductor layer has a concentration gradient portion such that the impurity concentration decreases as the distance from the third semiconductor layer increases, and the impurity concentration is low; The feature is that an electrode is provided on the surface including the part.

However, in the method of the present invention for manufacturing this semiconductor device, impurities are added from an opening in an insulating film formed on the surface of the first semiconductor layer to the area where the impurity concentration has decreased, and the impurity is added to the area around the opening in the first semiconductor layer. It is characterized by being formed by diffusion directly under the insulating film.

An embodiment of the present invention will be explained below with reference to FIGS. 4 and 5. In FIG. 4, the same sign as in FIG. 1 indicates the same component. That is, 1 is a collector region consisting of an N1-type semiconductor layer and an N-type semiconductor layer, 2x, 2a, 2b, 2
cm. is a single region made of a P-type semiconductor layer formed in the collector region, and 3a, 3b, and 3cm are base regions 2a, 2b.

2'c... An emitter region made of an N+ type semiconductor layer formed over a midway depth from each surface, 4a,
Reference numerals 4b and 4c are metal electrodes from which the base electrode 6 is taken out, and 5a, 5b, 5c, . . . are metal electrodes from which the emitter electrode 7 is taken out.

The collector electrode is formed above and below π11 in the drawing of the collector region 1, but is not shown. In the present invention, the base regions are formed in series so that the impurity concentration in the portions of the base regions 2a to 2d that are joined to the metal electrodes 48 to 4d, which are the lead-out portions of the base electrodes, is low. Rather, they are formed corresponding to the individual emitter regions 3a to 3d, but have portions that are formed individually. That is, the impurity concentration distribution in the portion where the metal electrodes 4a to 4d are joined is represented by the lateral distribution (concentration distribution between points a and b) as shown in FIG. 5(A) for the metal electrode 4b. The concentration distribution in the depth direction (concentration distribution between points d and e) is as shown in FIG. 5(B). Note that the base region 2X at the end is provided to make the impurity concentration of the metal electrode 4a at the end the same as the impurity concentration in other regions. Since the impurity 6 in the region 2A (parasitic diode region) other than the part 2B directly under the emitter region necessary for operation is small, a small number of impurities are injected from here into the collector region 1 when the transistor becomes saturated. The carriers are reduced, and among the switching characteristics, it is possible to reduce the storage time t8 shown in FIG. 3 in particular.

As a means for reducing the impurity concentration in the portion where the metal electrodes 4a to 4d are provided, as described above, it is possible to form a low impurity concentration portion directly under the metal electrodes 4a to 4d, separately from the formation of the base region. However, in the present invention,
As shown in FIG. 6, openings 12g, 12b, and 12 cm are formed in the insulating film 9a on the first semiconductor layer 1, which becomes the collector region.
, 9b, 9C. Impurities for forming the second semiconductor layer are added through the openings 12a, 12b, 12c by diffusion, ion implantation, vapor growth, etc. A second semiconductor layer is formed under the portions 12a, 12b, 12c by downward impurity diffusion as shown by the arrow 10, and the insulating films 9a, 9b are formed around the openings 12a, 12b, 12cm.

Directly below 9c, a portion where the impurity concentration of the second semiconductor layer is reduced by lateral impurity diffusion as shown by arrow 11 is formed to be continuous with the second semiconductor layer in the opening 1 portion. As a result, the insulating films 9 a and 9 b
A region where the concentration of impurities is reduced is formed directly below +9c-. Note that when forming a low concentration region of impurities by lateral diffusion as shown by the arrow 10, the diffusion may be performed in a state where the insulating films 9a, 9b, and 9c are not present. After forming the area of reduced concentration,
The third half of the second semiconductor layer 2a, 2'b, 2c, . η body layers 3a, 3b,
3c layers, and the third semiconductor layers 3a, 3b, 3c...
Metal electrodes 5a, 5a and 5b are respectively formed on the surface of the pot and the lower impurity concentration portions of the second semiconductor layers 2a, 2b, 2c.
5b, 5c· and 4a, 4b, 4c· are formed.

By making this transistor in this way,
There is no need to provide a special process for forming a portion of the second semiconductor layer with a reduced impurity concentration. Incidentally, in order to provide a metal electrode on the surface of a semiconductor layer as in the above embodiment, a metal electrode material such as polysilicon may be used.

Although the above explanation has been made regarding bipolar transistors, the present invention can also be applied to other semiconductor devices that are affected by parasitic diodes.

As described above, since the semiconductor device of the present invention reduces the impurity concentration at the electrode extraction portion such as the base electrode, it is possible to particularly shorten the storage time and speed up the switching operation. .

In the present invention, the low impurity concentration portion serving as the electrode extraction portion can be formed at the boundary portion when dividing the region, and is therefore suitable for a miniaturized structure for high-speed switching. In addition, conventional techniques for increasing withstand voltage such as FL, R (field limiting ring) and protruding electrodes (field blades, etc.) can be introduced to -1, making it suitable for increasing withstand voltage. In addition, the third aspect of the manufacturing method of the present invention is that the low impurity concentration portion, which is the part where the number of electrodes is exposed, is
By utilizing lateral diffusion when forming the region, no special process is required and it can be easily produced.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view showing an example of a conventional run ring, Figure 2 is its equivalent circuit diagram, Figure 3 is a current waveform diagram explaining its switching characteristics, and Figure 4 is an example of a transistor according to the present invention. 5(A) and 5(B) are impurity concentration distribution diagrams in the lateral and depth directions under the base electrode, respectively, and FIG. FIG. 3 is a partially enlarged sectional view showing the state. 1... Collector area, 2a to 2X... Base area, 3a
~3d-emitter region, 4a-4d, 5a-5d,
6.7...Metal electrode, 8,9...Insulating film, 9 Patent applicant Devergay Co., Ltd. Representative Patent attorney Waka 1) Win - Figure 1 Procedural amendment (voluntary) 1 Indication of case 111 (Japanese Patent Application No. 128284 2 Name of the invention ``IL conductor device and its manufacturing method 3 Supplement IF person = J<Relationship with the matter Patent applicant Address 13-1 Nihonbashi-chome, Chuo-ku, Tokyo Title name
(3013) TDC Co., Ltd. Representative Hiroshi Otoshi 4 Agent 〒272 Detailed explanation column, drawings (Figure 1) Contents of 7 amendments As shown in the attached sheet [1] The following amendments will be made to the description. (1) Amend the claims as shown in the attached sheet. (2) In page 3, line 6, add ``particularly the 2-A section'' between ``at the same time'' and ``parasitic diode.'' (3) Correct "entire base area" from line 5 on page 4 to line 6 on page 4 to "part 2-A." (4) In page 5, line 4, ``has,'' and ``on the surface'' is added between J and ``the second semiconductor layer.'' [2] Correct Figure 1 as shown in the attached sheet. Claim 1: - A second semiconductor layer of a conductivity type opposite to that of the first semiconductor layer is provided in the first semiconductor layer, and a second semiconductor layer is provided within the second semiconductor layer at a depth halfway from the surface of the second semiconductor layer. The second semiconductor layer has a third semiconductor layer having the same conductivity type as the first semiconductor layer over a region, and the second semiconductor layer has a concentration gradient portion such that the impurity concentration decreases as the distance from the third semiconductor layer increases. A semiconductor device characterized in that an electrode is provided on a surface including a low concentration portion. 2. The first semiconductor layer is the collector, the second semiconductor layer is the base,
The semiconductor device according to claim 1, which is a bipolar transistor having the third semiconductor layer as an emitter. 3.-first conductivity type: an impurity forming an insulating film on the conductor layer, opening the insulating film, and forming a second semiconductor layer having a conductivity type opposite to the first semiconductor layer from the opening; is added to form a second semiconductor layer in the opening, and a portion where the impurity concentration of the second semiconductor layer is reduced due to the diffusion of impurities is written as nfI in a portion directly under the insulating film around the control 1-'' portion. A third semiconductor layer is formed in succession to the second semiconductor layer in the opening, and a third semiconductor layer having the same conductivity type as the ilJl memorization semiconductor layer is formed in the second semiconductor layer, and the impurity concentration of the second semiconductor layer is reduced. A method for manufacturing a semiconductor device, comprising forming an electrode on a surface including a portion.

Claims (1)

[Scope of Claims] 1- A second semiconductor layer of a conductivity type opposite to that of the first semiconductor layer is provided in a first semiconductor layer of a conductivity type, and a region of a depth halfway from the surface of the second semiconductor layer is provided. a third semiconductor layer having the same conductivity type as the first semiconductor layer; the second semiconductor layer has a concentration gradient portion where the impurity concentration decreases as the distance from the third semiconductor layer increases; the portion where the impurity concentration is low; A semiconductor device characterized in that an electrode is provided on a surface including. 2. The semiconductor device according to claim 1B, which is a bipolar transistor having the first semiconductor layer as a collector, the second semiconductor layer as a base, and the third semiconductor layer as an emitter. 3- Forming an insulating film on a first semiconductor layer of a conductivity type, opening the insulating film, and adding an impurity through the opening to form a second semiconductor layer of a conductivity type opposite to that of the first semiconductor layer. A second semiconductor layer is formed in the opening, and the impurity concentration of the second semiconductor layer is made to be of the same conductivity type as the low-level body layer by diffusion of impurities directly under the insulating film around the opening. A method for manufacturing a semiconductor device, comprising forming a third semiconductor layer and forming an electrode on a surface including a portion of the second semiconductor layer where the impurity concentration is reduced.