JPH11204536A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the characteristics, such as high withstand pressure and high-speed switching, low saturation voltage and the like by setting the impurity concentration in a base region as a double-layered structure, and forming the heavily doped layer in the vicinity of the surface of a substrate at the depth including the layer in the vicinity of the surface of the substrate in an emitter region. SOLUTION: On a semiconductor substrate, having the N<+> /N<-> structure wherein a lightly doped N<-> -layer 2 is formed on a heavily doped N<+> -layer 1, a P<-> -layer 3 having am impurity concentration of NsP<-> =1×10<17> -5×10<17> cm<-3> and the depth from the substrate surface of XiP<-> =55-60 μm, is formed. Furthermore, a P<+> -layer 4 having an impurity concentration of NsP<+> =1×10<19> -5×10<19> cm<-3> and the depth from the substrate surface of XjP<+> =20-25 μm is formed on the P<-> layer 3. In the emitter region in the P<+> -layer 4, an N<+> -layer 5 is formed with an impurity concentration corresponding to a current amplitude β and the depth from the substrate surface of XjN<-> =13-18 μm is formed. Furthermore, the mesa groove formed at the outside of base region is filled with a passivation material 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a high breakdown voltage and high-speed switching.
The present invention relates to a bipolar transistor having a characteristic of low saturation voltage and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 6 is a cross-sectional structural view of a conventional bipolar transistor. Here, the structure of a mesa transistor is shown.

The bipolar transistor shown in FIG. 6 has the following structure. That is, N having a high impurity concentration
N ⁺ layer in which N ⁻ layer 2 having a low impurity concentration is formed on ⁺ layer 1
The impurity concentration NsP ⁻ = 1 on the semiconductor substrate having the / N ⁻ structure.
× 10 ¹⁷ -5 × 10 ¹⁷ cm ^-3 , depth Xj from substrate surface
A P ⁻ layer 10 with P ⁻ = 55 to 60 μm is formed.
Also, P ^- the emitter region on the layer 10, the current amplification factor β
The impurity concentration in accordance with, the depth XjN from the substrate surface ^- =
An N ⁺ layer 5 of 13 to 18 μm is formed, and an impurity concentration NsP ⁺ = 1 × 10 ^{19 to} 5 × 10 ¹⁹ cm is formed in the base region.
^-3 , P ⁺ at a depth XjP ⁺ = 8 to 10 μm from the substrate surface
A layer 11 is formed. Further, a mesa groove formed outside the base region is filled with a passivation material 6. The oxide insulating film 7 is formed at a predetermined portion on the surface of the semiconductor substrate as described above.
A base electrode 8 and an emitter electrode 9 are formed in an opening formed in the emitter region, and a collector is provided on the lower surface side of the N ⁺ layer 1 to constitute a bipolar transistor.

In the conventional bipolar transistor, a P ⁺ layer 11 shallower than the N ⁺ layer 5 in the emitter region is formed in the base region in order to increase the impurity concentration near the surface of the base region. This structure is employed for the purpose of reducing the contact resistance with the surface electrode and preventing the surface from being inverted.

[0005]

However, in the above-mentioned conventional bipolar transistor, a high impurity concentration layer is formed near the surface of the base region.
There is a problem that it is difficult to increase the switching speed. In the case of a bipolar transistor, the switching speed usually depends on how quickly the minority carriers in the base region flow out.Therefore, the high impurity concentration layer is formed near the base region surface, so that the switching speed is high. It becomes difficult to increase the speed.

On the other hand, when the impurity concentration in the base region is reduced, the junction resistance between the base and the emitter and between the collector and the base is increased, and the saturation voltage between the collector and the emitter is increased.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having characteristics of high withstand voltage, high speed switching, and low saturation voltage, and a method of manufacturing the same.

[0008]

According to the semiconductor device of the present invention, a first layer of the first conductivity type and a second layer of the first conductivity type formed on the first layer are provided. A third layer of a second conductivity type formed on the second layer and containing an impurity of the first impurity concentration; and a second layer formed on the third layer and having a higher impurity concentration than the first impurity concentration. A fourth layer of a second conductivity type containing an impurity having an impurity concentration of, and a first conductive layer formed near the substrate surface in the fourth layer, the depth from the substrate surface being smaller than the fourth layer. An opening is formed in the fifth layer of the mold, in a region where the fourth layer is formed near the substrate surface, and in a region where the fifth layer is formed near the substrate surface, and formed on the substrate surface. Insulating film, and an electrode formed in the opening of the insulating film on the substrate surface,
With this configuration, the emitter
At the base-to-base junction (junction), the fourth layer having a high impurity concentration reduces the junction resistance and suppresses the injection of carriers from the emitter region into the base region. Since the voltage can be reduced, the withstand voltage can be increased, and the movement of minority carriers in the base region can be suppressed by the third layer having a lower impurity concentration in a portion deeper than the fourth layer. High-speed characteristics can be achieved.

According to the method of manufacturing a semiconductor device according to the present invention, the second layer of the first conductivity type is formed on the first layer of the first conductivity type.
A second step of forming a third layer of a second conductivity type containing an impurity having a first impurity concentration on the second layer, and a third layer A third step of forming a fourth layer of the second conductivity type containing an impurity having a second impurity concentration higher than the first impurity concentration, and a third step of forming an insulating film on the fourth layer. Step 4 and opening an opening in a part of the insulating layer, and injecting and diffusing impurities, so that the depth from the substrate surface is higher than the fourth layer near the substrate surface in the fourth layer. A fifth step of forming a shallow first conductivity type fifth layer, a sixth step of forming an opening in the insulating film in a region where the fourth layer is formed near the substrate surface, and a substrate surface 4th nearby
And a seventh step of forming an electrode in the opening of the region where the fifth layer is formed and the region where the fifth layer is formed in the vicinity of the surface of the substrate. In the semiconductor device, at the emitter-base junction (junction), the fourth layer having a high impurity concentration reduces the junction resistance and suppresses the injection of carriers from the emitter region into the base region.
While the saturation voltage between the collector and the emitter is reduced, the breakdown voltage can be increased, and the movement of minority carriers in the base region can be prevented by the third layer having a lower impurity concentration in a portion deeper than the fourth layer. Since the switching is suppressed, the switching characteristics can be speeded up.

[0010]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of a semiconductor device according to the present invention, and more specifically, a cross-sectional view of a bipolar transistor according to the present invention. I have.

The bipolar transistor according to the present invention has the following structure. That is, a low impurity concentration on the high N ⁺ layer 1 impurity concentration N ^- layer 2 is formed N ⁺ / N ^- on a semiconductor substrate of a structure, the impurity concentration Ns
A P ⁻ layer 3 having a P ⁻ = 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ and a depth XjP ⁻ from the substrate surface of 55 to 60 μm is formed. On the P ⁻ layer 3, the impurity concentration NsP ⁺ = 1 ×
10 ¹⁹ -5 × 10 ¹⁹ cm ^-3 , depth XjP from substrate surface
⁺ = 20 to 25 m is a P ⁺ layer 4 is formed, P ⁺ to the emitter region of the layer 4, an impurity concentration corresponding to the current amplification factor beta, depth XjN from the substrate surface ^- = ^13~18μm of N
⁺ Layer 5 is formed. Further, a mesa groove formed outside the base region is filled with a passivation material 6. The oxide insulating film 7 is formed at a predetermined portion on the surface of the semiconductor substrate as described above.
A base electrode 8 and an emitter electrode 9 are formed in an opening formed in the emitter region, and a collector is provided on the lower surface side of the N ⁺ layer 1 to constitute a bipolar transistor.

FIG. 2 is a sectional structural view in each step of the method for manufacturing a semiconductor device according to the present invention. The semiconductor device according to the present invention is manufactured as follows by the method for manufacturing a semiconductor device according to the present invention.

A semiconductor substrate having an N ⁺ / N ⁻ structure in which an N ⁻ layer 2 having a low impurity concentration is formed on an N ⁺ layer 1 having a high impurity concentration as shown in FIG. As shown in (b), ion implantation and diffusion into the N ⁻ layer 2 are performed to obtain an impurity concentration NsP ⁻ = 1 × 10 ^{17 to} 5 × 10 ^17.
A P ⁻ layer 3 having a size of cm ⁻³ and a depth XjP ⁻ = 45 μm from the substrate surface is formed.

[0015] Next, as shown in FIG. 2 (c), P ^-
The layer 3 is ion-implanted, and the impurity concentration NsP ⁺ = 1 × 1
A P ⁺ layer 4 of 0 ^{19 to} 5 × 10 ¹⁹ cm ⁻³ is formed.
As shown in FIG. 2D, on the substrate surface, that is, P ⁺
An oxide insulating film 7 is formed on the layer 4. At this time, the depth XjP ⁺ of the P ⁺ layer 4 from the substrate surface is 20 to 25 μm,
^- from the substrate surface of the layer 3 deep XjP ^- = 55~60μm
Thus, the base region is formed.

After forming the oxide insulating film 7, a resist is formed,
Exposure and development of a predetermined pattern are performed, and as shown in FIG. 2E, a portion of the oxide insulating film 7 serving as an emitter region is removed by etching, and ion implantation is performed.
An N ⁺ layer 5 having a depth XjN ⁻ = 13 to 18 μm from the substrate surface is formed. That, P ⁺ layer 4 of the base region is N ⁺ layer 5
Than about 5 to 10 μm. Also,
The impurity concentration of N ⁺ layer 5 is appropriately adjusted so that current amplification factor β has a required value. The unnecessary resist is removed.

Finally, as shown in FIG. 2F, a mesa groove is formed outside the base region, and the mesa groove is filled with a passivation material 6. Also, formation of resist,
After exposing and developing a predetermined pattern and removing a predetermined portion of the oxide insulating film 7 by etching, a base electrode 8 and an emitter electrode 9 are formed. Thus, the semiconductor device according to the present invention shown in FIG. 1 is completed.

As described above, the impurity concentration of the base region of the semiconductor device according to the present invention has a two-layer structure, and the P ⁺ layer 4 having a high impurity concentration near the substrate surface.
Is characterized in that it is formed about 5 to 10 μm deeper than the N ⁺ layer 5 in the emitter region. By employing such a structure, in the emitter-base junction (junction), the junction resistance is reduced by the P ⁺ layer 4 having a high impurity concentration, and carriers are injected from the emitter region into the base region. Is suppressed. Accordingly, while the saturation voltage between the collector and the emitter is reduced, the withstand voltage can be increased. In addition, since the movement of minority carriers in the base region is suppressed by the P ⁻ layer 3 having a lower impurity concentration in the portion deeper than the P ⁺ layer 4, the switching characteristics can be speeded up.

FIG. 3 is a first graph showing switching characteristics of the semiconductor device according to the present invention and the conventional semiconductor device. Specifically, it is a graph showing the relationship between the fall time tf, which is the disappearance time of the collector current at the time of switching off, and the rate of change dIB / dt of the base current.
The cycle frequency fH of turning on and off the base current is 6
4 MHz.

If the range of the fall time tf that can be used in a certain standard is, for example, 0.3 μsec or less, the fall time tf of the semiconductor device according to the present invention is 0.3 μse
c The following range is expanded as compared with the conventional semiconductor device, and it can be seen that the switching speed is increased.

FIG. 4 is a second graph showing switching characteristics of the semiconductor device according to the present invention and the conventional semiconductor device. Specifically, it is a graph showing the relationship between the storage time tstg, which is the time from when the base current is turned off to when the collector current starts to disappear, and the rate of change dIB / dt of the base current. The ON / OFF cycle frequency fH of the base current is set to 64 MHz.

The storage time tst of the semiconductor device according to the present invention over the entire range shown in the graph of FIG.
g is 1 to 2 μs shorter than that of the conventional semiconductor device, and it can be seen that the switching speed is increased.

FIG. 5 shows the collector-emitter saturation voltage VCE (sa) of the semiconductor device according to the present invention and the conventional semiconductor device.
5 is a graph showing the relationship between t) and the collector current IC.
The current amplification factor β of the transistor is set to a constant value 5.

A comparison of the VCE (sat) -IC characteristics between the semiconductor device according to the present invention and the conventional semiconductor device shows that the collector-emitter saturation voltage VCE (sat) is 5 to 1 over the entire range.
It can be seen that it has been reduced by 0%.

It should be noted that the semiconductor device and the method of manufacturing the same according to the present invention can be carried out with the conductivity types of the respective parts in the above-described embodiment being opposite to each other.

[0026]

According to the semiconductor device and the method of manufacturing the same according to the present invention, the impurity concentration of the base region has a two-layer structure, and the layer having a high impurity concentration near the substrate surface is:
Since the emitter region is formed at a depth including the layer near the substrate surface, the junction resistance between the emitter and the base is reduced by the layer having a high impurity concentration at the junction between the emitter and the base. By suppressing the injection of carriers from the region to the base region, the saturation voltage between the collector and the emitter can be reduced, the breakdown voltage can be increased, and the impurity in a portion deeper than a layer having a higher impurity concentration can be obtained. Since the movement of minority carriers in the base region is suppressed by the low-concentration layer, the switching characteristics can be speeded up.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a semiconductor device according to the present invention.

FIG. 2 is a sectional structural view in each step of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a first graph showing switching characteristics of a semiconductor device according to the present invention and a conventional semiconductor device.

FIG. 4 is a second graph showing switching characteristics of the semiconductor device according to the present invention and a conventional semiconductor device.

FIG. 5 is a graph showing the relationship between the collector-emitter saturation voltage VCE (sat) and the collector current IC of the semiconductor device according to the present invention and the conventional semiconductor device.

FIG. 6 is a sectional structural view of a conventional bipolar transistor.

[Explanation of symbols]

1 N ⁺ layer 2 N ^- layer 3 P ^- layer 4 P ⁺ layer 5 N ⁺ layer 6 passivation material 7 oxide insulating film 8 base electrode 9 emitter electrode 10 P ^- layer 11 P ⁺ layer

Claims (2)

[Claims] A first layer of a first conductivity type; a second layer of the first conductivity type formed on the first layer; and a second layer of the first conductivity type; A third layer of a second conductivity type including an impurity having a first impurity concentration; and a third layer formed on the third layer and including an impurity having a second impurity concentration higher than the first impurity concentration. A fourth layer of a second conductivity type, wherein a depth from a substrate surface is smaller than the fourth layer;
A fifth layer of the first conductivity type formed in the vicinity of the substrate surface in a layer of the first type, a region in which the fourth layer is formed in the vicinity of the substrate surface, and the fifth layer in the vicinity of the substrate surface. An opening is opened in a region where the layer of No. 5 is formed, and an insulating film formed on the substrate surface, and an electrode formed in the opening of the insulating film on the substrate surface are provided. A semiconductor device characterized by the above-mentioned. 2. A first step of forming a second layer of the first conductivity type on a first layer of a first conductivity type; and a first impurity on the second layer. A second step of forming a third layer of a second conductivity type containing an impurity of a concentration, and forming a second layer having a higher impurity concentration than the first impurity on the third layer.
A third step of forming a fourth layer of the second conductivity type containing an impurity having an impurity concentration of, a fourth step of forming an insulating film on the fourth layer, An opening is formed in the portion, and an impurity is implanted and diffused, so that the first conductive layer, which is shallower than the fourth layer, is formed near the substrate surface in the fourth layer. A fifth step of forming a fifth layer of a mold, a sixth step of opening an opening in the insulating film in a region where the fourth layer is formed near the substrate surface, and a vicinity of the substrate surface A step of forming an electrode in the opening in the region where the fourth layer is formed and the region where the fifth layer is formed near the surface of the substrate. Semiconductor device manufacturing method.