JPS6020560A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to enhance the speed and to enhance the withstand voltage of a drain earthed laterally structural insulated gate field effect transistor by a method wherein a high concentration impurity buried layer is provided in the neighborhood directly under the source thereof as not to reduce the withstand voltage between the source and the drain. CONSTITUTION:An N type buried layer 2A is formed in a high resistivity P type substrate 1A, and after N type epitaxial layers 3A-3C are formed, P type diffusion layers 4A, 4B to be used for element isolation and as the drain of a laterally structural MOSFET are formed. After then, formation of a gate oxide film 101, formation of a poly-Si gate 7A, ion implantation for formation of a P type impurity diffusion layer 5A to enhance the withstand voltage, formation of a P type diffusion layer 8A, formation of an N type diffusion layer 9A to short-circuit between the epitaxial layer and the source, formation of contacts, and formation of Al wirings are performed according to the manufacturing method of the usual high withstand voltage laterally structural MOSFET. Accordingly, because the high concentration impurity buried layer 2A is existing in the neighborhood directly under the source diffusion layer 8A, a punch through is hard to be generated between the source and the drain (the substrate), and the effect of a vertically parasitic PNP transistor can be reduced, too.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an integrated circuit including an insulated gate field effect transistor, and particularly to a lateral structure insulated gate field effect transistor with a grounded drain structure that requires high speed and high breakdown voltage.

[Background of invention]

Figure 1 shows the cross-sectional structure of a single lateral structure insulated gate field effect transistor. The source and gate have terminals from the front surface, but the drain has terminals from the back surface, so IA had a Hatake impurity concentration to reduce the resistance of the drain. Therefore, the depletion layer formed between IA and 3B extends well toward the low impurity concentration 3B side, and there is a drawback that punch-through between the source and drain tends to occur.

[Purpose of the invention]

An object of the present invention is to provide a high-concentration impurity buried layer directly below the source in order to prevent a decrease in source-drain breakdown voltage in a lateral structure insulated gate field effect transistor with a common drain. The object of the present invention is to propose a semiconductor device with improved drain breakdown voltage.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. The manufacturing method is to form a high resistivity p-type substrate IAKn-type buried layer 2A, and then form an n-type epitaxial layer 3A.

After forming layers 3B and 3C, p-swelled diffusion layers 4A and 4B are formed to be used for element isolation and as a drain of a lateral structure insulated gate field effect transistor. Thereafter, a gate oxide film 1o1 is formed and a polySj gate (7
A) Formation, ion implantation for p-type impurity diffusion layer 5A with a dose of about I x 1012 cm-'' for high breakdown voltage, formation of p-type source diffusion layer 8A, and ion implantation for short-circuiting between the evitigmental layer and the source. It can be manufactured by forming the n-swelled diffusion layer 9A, contact formation, A/wire formation, etc. In the structure shown in FIG. 2, since the drain terminal is taken from the surface, the substrate IA can have a low impurity concentration. Therefore, the depletion layer between IA and 3B is wide on the IA side.In particular, since there is a high concentration impurity buried layer 2A directly under the source 8A, punch-through occurs between the source and drain (substrate).
<, the effect of parasitic vertical PNP can also be reduced. In addition, since the substrate IA has a low concentration, even if the high concentration buried layer 2A is present, there is little reduction in breakdown voltage due to avalanche. Also, the substrate I
Since the highly concentrated drain portions (4A and 4B) of A are formed so as not to be in direct contact with the highly doped buried layer 2A, a drop in breakdown voltage due to avalanche near 4A and 4B can be prevented. Further, since the drain is at the same potential as the substrate, there are restrictions on use, but it has the advantage that the device area is smaller than a structure in which the drain is separated.

FIG. 3 shows an embodiment in which the structure of the gate 7 is different from the embodiment shown in FIG.

FIG. 4 shows a case where a source diffusion layer 4B and a drain diffusion layer 4C are formed at the same time.
C reaches the substrate IA, but the source diffusion layer 4B is prevented from punching through the substrate IA by the buried layer 2A.

Figure 5 shows the P for high voltage resistance used in Figure 4.
A structure with a diffusion layer 5A is shown.

FIG. 6 shows a structure in which two gates (7C, 7D) are used to allow current to flow left and right. In addition, in this embodiment, the field blue (7A, 7B, 7) of the separator separation section is
E as the gate (7C97])) and the same film (e.g., po
lysi) was used, conductive wiring other than the gate (
For example, At) only needs one layer (IOA, 10B).

FIG. 7 shows a vertical insulated gate field effect transistor (n channel) which can be formed in the same process as the lateral insulated gate field effect transistor (p channel) of the present invention. By using these two types of transistors, the circuit shown in FIG. 8 can be constructed. This circuit can be used, for example, in a power MO8FET amplifier output stage.

FIG. 9 shows a known technique for improving the withstand voltage of a low-channel transistor (for example, published patent publication No. 55-30).
844) was shown.

FIG. 10 shows an example showing that the drain (8c) formed inside the element isolation diffusion layers (4A, 4B) does not have to reach the substrate IA. In this case, the lateral diffusion of 8c is 4 A.

Since it is smaller than 4B, the element area can be saved.

〔Effect of the invention〕

According to the present invention, it is possible to realize an insulated gate field effect transistor with a lateral structure of a common drain structure and a high withstand voltage, with less reduction in breakdown voltage due to punch-through between the source and drain and less deterioration of suppression due to avalanche. Furthermore, since the device has a drain/ground structure, the area of the element isolation region is small.

In addition, the push-pull circuit of the source follower connected to the insulated gate field effect transistor with complementary characteristics formed on the same chip as the horizontal insulated gate field effect transistor with the common drain structure has high frequency and high breakdown voltage performance. This can be achieved with a small element area.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a common drain lateral structure insulated gate field effect transistor, FIGS. 2 to 6 and 10 are cross sectional views of a common drain lateral structure insulated gate field effect transistor of the present invention, and FIG. 7 is the same. A cross-sectional view of a vertical structure insulated gate field effect transistor Q2 formed on a chip, FIG. 8 is a vertical structure insulated gate field effect transistor Q
FIG. 9 is a cross-sectional view when 2 is formed of a thick epitaxial layer region, and is a diagram showing a complementary circuit that can be constructed by the elements shown in FIGS. 7 and 8. IA/I) type substrate, 2A, 2B/-n+ buried layer, 3
8-3F...n-type epitaxial layer, 4A, 4B. 4C...p swelling diffusion layer (element isolation and drain of lateral structure insulated gate field effect transistor), 5A to 5D...
p-diffusion layer, 6A~6■...Insulating film (Example 5i02゜P
SG), 78~7E...Gate and shield plate (
Example, poly3i), s A to s E-,) swelling diffusion layer,
9A, 9B, 9C/n swelling diffusion layer, -10~10H...
・Wiring (e.g., At), IIA to 11E... Insulating film (e.g., 8jO2, PSG, PIQ), 12A, 12B, 12
C... Wiring (e.g., At), 13A, 13 B-n type diffusion Figure 1 χ 4 Figure 5 Figure 6 (2)

Claims (1)

[Claims] 1. A first semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type is separated by a second semiconductor layer of a first conductivity type, and a semiconductor layer of a first conductivity type is formed inside the second semiconductor layer of a first conductivity type. A third semiconductor layer is formed, each serving as a source and a drain of a lateral structure insulated gate field effect transistor, and the second semiconductor layer is highly doped at the interface between the first conductivity type semiconductor substrate and the second semiconductor layer immediately below the source. A semiconductor device characterized in that a fifth semiconductor layer of a second conductivity type is provided so as not to be in direct contact with a high concentration portion of the second semiconductor layer or the fourth semiconductor layer. 2. The semiconductor device according to claim 1, wherein the third semiconductor layer and the fourth semiconductor layer are formed at the same time. 3. The semiconductor device according to claim 1, wherein the fourth semiconductor layer and the second semiconductor layer are formed at the same time. 4. The semiconductor device according to claim 1, wherein the third semiconductor layer and the fourth semiconductor layer are formed simultaneously with the second semiconductor layer.