JPS60202959A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPS60202959A JPS60202959A JP5824284A JP5824284A JPS60202959A JP S60202959 A JPS60202959 A JP S60202959A JP 5824284 A JP5824284 A JP 5824284A JP 5824284 A JP5824284 A JP 5824284A JP S60202959 A JPS60202959 A JP S60202959A
- Authority
- JP
- Japan
- Prior art keywords
- thermal expansion
- semiconductor device
- support wall
- expansion coefficient
- wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体デバイス用パッケージに関する。[Detailed description of the invention] [Field of application of the invention] The present invention relates to packages for semiconductor devices.
従来の半導体デバイス用パッケージとして、セラミック
基板の端部を越えて外方へ水平に延びた環状フランジに
、クランプ部材を介しキャンプを取付ける構造としたも
のがある（特開昭５６−７４５７号）。このような構造
にすると、キャップの熱膨張係数をセラミック基板の熱
膨張係数に整合させる必要がないため、キャップの材料
として。A conventional semiconductor device package has a structure in which a camp is attached via a clamp member to an annular flange extending horizontally outward beyond the edge of a ceramic substrate (Japanese Patent Application Laid-open No. 7457/1983). With this structure, there is no need to match the thermal expansion coefficient of the cap to that of the ceramic substrate, so it is not necessary to match the thermal expansion coefficient of the cap to the ceramic substrate.
アルミニウムのような高熱伝導材料を使うことができ、
パッケージの冷却性能を高めることができる。しかし、
環状フランジとキャップの一部およびクランプ部材がセ
ラミック基板の外側に突き出るため、パッケージ相互間
の配線が長くなり、高密度化、高速化をより要求される
場合には改善の余地がある。High thermal conductivity materials such as aluminum can be used,
The cooling performance of the package can be improved. but,
Since the annular flange, part of the cap, and the clamp member protrude outside the ceramic substrate, the wiring between the packages becomes long, and there is room for improvement when higher density and higher speed are required.
本発明は基板の端部から突き出る部分をなくしたコンパ
クトな半導体デバイス用パッケージを提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a compact package for a semiconductor device that eliminates a portion protruding from the edge of a substrate.
本発明は、基板の端部から外側に突き出る部分をなくす
るために、基板の半導体デバイス搭載面に対しほぼ垂直
に延びた環状支持壁部材を、半導体デバイス搭載面に固
着し、この支持壁部材と共に半導体デバイス搭載面を封
止するための部材を支持壁部材に固着する。また、支持
壁部材を基板の熱膨張係数とほぼ整合する熱膨張係数を
有する材質により形成し、かつ可撓性を付与することに
より、封止のための部材の材料を任意に選べるようにす
る。In order to eliminate the portion protruding outward from the edge of the substrate, the present invention fixes an annular support wall member extending substantially perpendicularly to the semiconductor device mounting surface of the substrate to the semiconductor device mounting surface, and this support wall member At the same time, a member for sealing the semiconductor device mounting surface is fixed to the support wall member. Furthermore, by forming the support wall member from a material having a thermal expansion coefficient that almost matches that of the substrate and providing flexibility, the material for the sealing member can be arbitrarily selected. .
第１図は本発明の一実施例を示す概略断面図である。こ
の図において、１は多層のセラミック基板であり、その
上面（半導体デバイス搭載面）には、複数の半導体デバ
イス２が半田３により電気的および物理的に接続されて
いる。セラミック基（反１の下面にはパッケージ内部と
外部との電気的接続用の１１０ピン４がロー付けされて
いる。FIG. 1 is a schematic sectional view showing an embodiment of the present invention. In this figure, 1 is a multilayer ceramic substrate, and a plurality of semiconductor devices 2 are electrically and physically connected to its upper surface (semiconductor device mounting surface) by solder 3. A 110 pin 4 for electrical connection between the inside of the package and the outside is soldered to the bottom surface of the ceramic base (1).
６は水冷ヒートシンクであり、アルミニウム。6 is a water-cooled heat sink, which is made of aluminum.
銅等の高熱伝導材料で作られており、内部に冷却水を流
すための管路７が設けられている。９は水冷ピー１−シ
ンクロを支持するための環状の支持壁である。この支持
壁９はその下端部において半導体デバイス搭載面にほぼ
垂直に固着されるが、セラミック基板１の熱膨張係数に
ほぼ整合する熱膨張係数を持ったコバール（ＫＯＶＥＲ
）で作られているため、金スズ等により直接的にロー付
け（Ｉ６）されている。上記水冷ヒートシンク６は、環
状ガスケット１１を介してねじ１２により支持壁９の上
端に固着される。このように、ねじ１２によって固着す
るようになっているため、単導体デバイス２の交換、配
線変更等の際にパッケージの開封および再封止を容易に
行うことができる。It is made of a highly thermally conductive material such as copper, and is provided with a pipe 7 for flowing cooling water inside. 9 is an annular support wall for supporting the water-cooled P1 synchro. This support wall 9 is fixed at its lower end almost perpendicularly to the semiconductor device mounting surface, and is made of KOVER, which has a thermal expansion coefficient that almost matches the thermal expansion coefficient of the ceramic substrate 1.
), it is directly soldered (I6) with gold tin, etc. The water-cooled heat sink 6 is fixed to the upper end of the support wall 9 with screws 12 via an annular gasket 11 . Since the package is fixed by the screws 12 in this way, the package can be easily opened and resealed when replacing the single conductor device 2 or changing the wiring.
上記支持壁９には環状の切り込み１０が形成され、支持
壁９の剛性を減らし、支持壁９に可撓性を付与している
。このように支持壁９に可撓性を付与することにより、
水冷ビー１〜シンクロとセラミック基板１の熱膨張係数
の違いによる熱応力を支持壁９によって吸収している。An annular notch 10 is formed in the support wall 9 to reduce the rigidity of the support wall 9 and provide flexibility to the support wall 9. By imparting flexibility to the support wall 9 in this way,
Thermal stress due to the difference in thermal expansion coefficient between the water-cooled bee 1 to the synchro and the ceramic substrate 1 is absorbed by the support wall 9.
その結果、セラミック基板ｌとの熱膨張係数の整合を意
識することなく、水冷ヒートシンク６の材料として高熱
伝導材料を選び冷却効果を最高度に高めることができる
。水冷ヒートシンク６の内面には、半導体デバイス２の
発熱を水冷ヒートシンク６に効率よく伝達するための熱
伝導素子５が設けられ、この熱伝導素子５は半導体デバ
イス２の背面に接触する。As a result, a high thermal conductivity material can be selected as the material for the water-cooled heat sink 6 and the cooling effect can be maximized without being conscious of matching the coefficient of thermal expansion with the ceramic substrate l. A heat conductive element 5 is provided on the inner surface of the water-cooled heat sink 6 for efficiently transmitting heat generated by the semiconductor device 2 to the water-cooled heat sink 6, and this heat conductive element 5 contacts the back surface of the semiconductor device 2.
ここで、第１図に明瞭に示されるように、支持壁９は半
導体デバイス搭載面に対してほぼ垂直に延びており、支
持壁９およびそれに支持された水冷ヒートシンク６は、
従来のようにセラミック基１反１の端部から外側に突出
することはなくなる。Here, as clearly shown in FIG. 1, the support wall 9 extends almost perpendicularly to the semiconductor device mounting surface, and the support wall 9 and the water-cooled heat sink 6 supported by it are
The ceramic base 1 no longer protrudes outward from the end of the ceramic base 1 as in the conventional case.
従って、コンパクトな半導体デバイス用パッケージを実
現でき、パッケージの一層高密度な実装が可能となる。Therefore, it is possible to realize a compact package for a semiconductor device, and it is possible to package the package at a higher density.
さらにパッケージ間相互配線の長さも短縮され、配線遅
延も減少されるため、システ１１の一層の高速化を図る
ことができる。Furthermore, the length of the inter-package interconnections is shortened and the interconnection delay is also reduced, making it possible to further speed up the system 11.
第２図は本発明の他の実施例を示す概略断面図である。FIG. 2 is a schematic sectional view showing another embodiment of the present invention.
本実施例においては、セラミック基板１の熱膨張係数と
ほぼ整合する熱膨張係数を持つ４２７０イの薄板にて可
撓性のある環状支持壁９を形成している。そして、水冷
ヒートシンク６を支持壁９の上端に拡散接合（２１）に
より固着し、支持壁９の下端を低温半田（２２）により
半導体デバイス搭載面に固着している。支持壁９と半導
体デバイス搭載面の着脱は、低温半田２２の部分で容易
に行うことができるので、パッケージの開封、再封止の
作業は簡単である。これ以外は上記実施例と同様である
。In this embodiment, the flexible annular support wall 9 is formed of a 4270 mm thin plate having a coefficient of thermal expansion substantially matching that of the ceramic substrate 1. The water-cooled heat sink 6 is fixed to the upper end of the support wall 9 by diffusion bonding (21), and the lower end of the support wall 9 is fixed to the semiconductor device mounting surface by low-temperature solder (22). Since the support wall 9 and the semiconductor device mounting surface can be easily attached and detached at the low-temperature solder 22, the work of opening and resealing the package is easy. Other than this, this embodiment is the same as the above embodiment.
第３図は第２図に示した実施例の変形例を示す概略断面
図である。この例においては、支持壁９を２山のベロー
ズとして形成し、支持壁９の可撓性を高めている。これ
以外は上記実施例と同様である。FIG. 3 is a schematic sectional view showing a modification of the embodiment shown in FIG. 2. In this example, the support wall 9 is formed as a double bellows to increase the flexibility of the support wall 9. Other than this, this embodiment is the same as the above embodiment.
第４図は本発明の別の実施例を示す概略断面図である。FIG. 4 is a schematic cross-sectional view showing another embodiment of the present invention.
この実施例においては、水冷ヒートシンクの代わりにア
ルミニウムや銅等の高熱伝導材料で作られた空冷ヒート
シンク３６が設けられ、この空冷ヒートシンク３６と半
導体デバイス２は、物理的に不活性な熱伝導ペースト３
５によって熱的に結合されている。支持壁９は、コバー
ルの薄肉材料で１山のベローズに形成されている。また
Ｉ１０ピン４はフラットリードとなっている。これ以外
は上記各実施例と同様である。In this embodiment, an air-cooled heat sink 36 made of a highly thermally conductive material such as aluminum or copper is provided instead of a water-cooled heat sink, and the air-cooled heat sink 36 and the semiconductor device 2 are connected to a physically inert thermally conductive paste 3.
5. The support wall 9 is made of a thin Kovar material and is formed into a single bellows. Also, I10 pin 4 has a flat lead. Other than this, it is the same as each of the above embodiments.
この実施例のパッケージは、搭載される半導体デバイス
の個数が少ない場合や、半導体デバイスの発熱量が少な
い場合に好適である。The package of this embodiment is suitable when the number of semiconductor devices to be mounted is small or when the amount of heat generated by the semiconductor devices is small.
本発明によれば次にような効果が達成できる。 According to the present invention, the following effects can be achieved.
（イ） 基板の端部から外部に突出する部分がなくなり
パッケージがコンパクトになる。従って。(b) There is no part protruding from the edge of the board to the outside, making the package more compact. Therefore.
パッケージ実装密度を従来より向上でき、またパッケー
ジ相互配線の長さが短縮し、その配線遅延の減少により
システムの高速化を達成することができる。The packaging density of the package can be improved compared to the conventional method, and the length of interconnections between the packages can be shortened, and the wiring delay can be reduced, thereby increasing the speed of the system.
（ロ）支持壁部材に可撓性を付与したため、パッケージ
の天板部材（前記各実施例のヒートシンク）を、基板と
の熱膨張係数の整合を考慮することなく、高熱伝導材料
を用いて形成することができ、高い冷却性能を得ること
ができる。(b) Since flexibility is imparted to the support wall member, the top plate member of the package (heat sink in each of the above embodiments) is formed using a highly thermally conductive material without considering matching of the coefficient of thermal expansion with the substrate. It is possible to obtain high cooling performance.
第１図ないし第４図はそれぞれ本発明の別異の実施例を
示す概略断面図である。
１・・・セラミック基板、２・・・半導体デバイス、４
・・・Ｉ１０ピン、５・・・熱伝導素子。
６・・・水冷ヒートシンク、９・・・支持壁、１０・・
・切り込み、３６・・・空冷ヒートシンク、３５・・・
熱伝導ペースト。1 to 4 are schematic sectional views showing different embodiments of the present invention. 1... Ceramic substrate, 2... Semiconductor device, 4
...I10 pin, 5...thermal conduction element. 6...Water-cooled heat sink, 9...Supporting wall, 10...
・Notch, 36... Air cooling heat sink, 35...
Thermal conductive paste.
Claims (1)
導体デバイス搭載面に固着され、該半導体デバイス搭載
面からほぼ垂直に延びた環状の支持壁部材と、該半導体
デバイス搭載面を覆うように該支持壁部材に固着支持さ
れ、該支持壁部材と協働して該半導体デバイス搭載面を
封止する部材とを具備し、該支持壁部材は該基板の熱膨
張係数とほぼ整合する熱膨張係数を有す材質から成り、
かつ可撓性を有することを特徴とする半導体デバイス用
パッケージ。(1) A substrate on which a semiconductor device is mounted, an annular support wall member fixed to the semiconductor device mounting surface of the substrate and extending substantially perpendicularly from the semiconductor device mounting surface, and a ring-shaped support wall member that covers the semiconductor device mounting surface. a member that is fixedly supported by the support wall member and cooperates with the support wall member to seal the semiconductor device mounting surface, the support wall member having a thermal expansion coefficient substantially matching a coefficient of thermal expansion of the substrate. Made of material with a coefficient,
A semiconductor device package characterized by having flexibility.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5824284A JPS60202959A (en) | 1984-03-28 | 1984-03-28 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5824284A JPS60202959A (en) | 1984-03-28 | 1984-03-28 | Package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60202959A true JPS60202959A (en) | 1985-10-14 |
Family
ID=13078639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5824284A Pending JPS60202959A (en) | 1984-03-28 | 1984-03-28 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60202959A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6985668B2 (en) | 2003-07-15 | 2006-01-10 | National Semiconductor Corporation | Multi-purpose optical light pipe |
-
1984
- 1984-03-28 JP JP5824284A patent/JPS60202959A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6985668B2 (en) | 2003-07-15 | 2006-01-10 | National Semiconductor Corporation | Multi-purpose optical light pipe |
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