JPS60200560A - Parallel connecting structure of transistor module - Google Patents

Parallel connecting structure of transistor module

Info

Publication number
JPS60200560A
JPS60200560A JP59056223A JP5622384A JPS60200560A JP S60200560 A JPS60200560 A JP S60200560A JP 59056223 A JP59056223 A JP 59056223A JP 5622384 A JP5622384 A JP 5622384A JP S60200560 A JPS60200560 A JP S60200560A
Authority
JP
Japan
Prior art keywords
main circuit
terminal
conductors
transistor
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59056223A
Other languages
Japanese (ja)
Inventor
Hiroshi Hamaguchi
濱口 宏
Masakatsu Ogami
正勝 大上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59056223A priority Critical patent/JPS60200560A/en
Publication of JPS60200560A publication Critical patent/JPS60200560A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/115Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inverter Devices (AREA)

Abstract

PURPOSE:To minimize a surge voltage at OFF time by forming a balance type parallel conductor structure symmetrical at the right and left sides with a power supplying point as a fulcrum in a main circuit conductor, thereby holding the optimum balance in a main circuit current. CONSTITUTION:Main circuit conductors 2a-2c formed in a balance type symmetrical at the right and left sides with a power supplying point 3a as a fulcrum are formed at the minimum distance from an AC terminal, an N terminal and a P terminal of power receiving point of transistor modules 1a-1f, of plate- shaped parallel conductors, and interposed in contact with an insulator 56 therebetween. A main circuit current from a power source is supplied through lead wirings 4a-4c, from power supplying points 3a-3c to transistor modules 1a-1f through main circuit conductors 2a-2c at equal distance to AC terminal, N terminal and P terminal of power receiving points of the modules 1a-1f. This is performed by forming symmetrical in balance at the right and left sides with the power supply point as a center at the conductors 2a-2c.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は電力機器における複数のトランジスタモジュ
ールに主回路電流を最適バランスで供給できるトランジ
スタモジュールの。並列接続構造ニ関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a transistor module that can supply main circuit current in an optimal balance to a plurality of transistor modules in power equipment. This relates to parallel connection structures.

〔従来技術〕[Prior art]

従来この種のトランジスタモジュールの並列接続構造と
して第1図(a)に示すものがあった。
Conventionally, there has been a parallel connection structure of this type of transistor module as shown in FIG. 1(a).

回圧おいて1はトランジスタモジュール1a〜1fの6
モジユールが集合されたトランジスタモジュール群であ
り、受電点であるAC端子、N端子、P端子を夫々有し
ている。2a〜2Cは上記各トランジスタモジュール1
a〜1fの各端子を夫々種別に連結するブスバーまたは
電線等の主回路導体であり上記受電点に各々接続されて
おり、図の場合、トランジスタモジー−ル1aのAC端
子、N端子、P端子が夫々図示しない電源装置からの給
電点3a、3b、3cとなる。4a〜4Cは上記主回路
導体23〜2Cと電源装置を接続するリード線であり、
ネジ等により主回路導体2a〜2Cを介して給電点に接
続されている。また第1図(b)は第1図(a)の側面
図を示し、図において5は)9ンジスタモジユ一ル群(
1)用の放熱フィンである。第2図は上記構成からなる
従来の並列接続構造を回路図で示したものであり、図中
、第1図と同一符号のものは同一要素を示す。
In the circuit voltage, 1 is 6 of transistor modules 1a to 1f.
This is a transistor module group in which modules are assembled, and each has an AC terminal, an N terminal, and a P terminal as power receiving points. 2a to 2C are each of the above transistor modules 1
It is a main circuit conductor such as a bus bar or electric wire that connects each terminal of a to 1f, respectively, and is connected to the above power receiving point, and in the case of the figure, it is the AC terminal, N terminal, and P terminal of transistor module 1a. The terminals serve as power feeding points 3a, 3b, and 3c from a power supply device (not shown), respectively. 4a to 4C are lead wires connecting the main circuit conductors 23 to 2C and the power supply device,
It is connected to a power feeding point via main circuit conductors 2a to 2C with screws or the like. FIG. 1(b) shows a side view of FIG. 1(a), and in the figure, 5 is a nine-in-one module group (
This is a heat dissipation fin for 1). FIG. 2 is a circuit diagram showing a conventional parallel connection structure having the above configuration, and in the figure, the same reference numerals as in FIG. 1 indicate the same elements.

次に上記構成からなる並列接続構造の作用について説明
する。
Next, the operation of the parallel connection structure having the above configuration will be explained.

第1図において給電点3aから各トランジスタモジュー
ル1a〜1fの受電点である各AC端子までは各々導体
距離が異なり、他の給電点3b。
In FIG. 1, the conductor distances from the power feeding point 3a to each AC terminal, which is the power receiving point of each transistor module 1a to 1f, are different from each other.

3Cに関しても同様である。従って第2図に示すように
給電点3a、3b、3cから見た各トランジスタモジュ
ール1a〜1fのインピーダンス差が非常に大きい為、
各主回路電流がアンバランスとなる。すなわちトランジ
スタモジュール1aには大きな主回路電流が流れ、トラ
ンジスタモジュール1fには小さな主回路電流が流れて
各トランジスタモジュール18〜1f夫々がアンバラン
スを生ずる。
The same applies to 3C. Therefore, as shown in FIG. 2, the impedance difference between the transistor modules 1a to 1f as seen from the feed points 3a, 3b, and 3c is very large.
Each main circuit current becomes unbalanced. That is, a large main circuit current flows through the transistor module 1a, and a small main circuit current flows through the transistor module 1f, causing an imbalance in each of the transistor modules 18 to 1f.

また、主回路導体2a〜2Cの浮遊インダクタンスによ
り、特に給電点1aから最も遠いトランジスタモジュー
ル1fは大きな浮遊インダクタンスを有することになる
Further, due to the floating inductance of the main circuit conductors 2a to 2C, the transistor module 1f that is farthest from the feeding point 1a has a particularly large floating inductance.

従来のトランジスタモジュールの並列接続構造は以上の
ように構成されているので、各トランジスタモジュール
間のインピーダンス差が大きく、また給電点より遠端の
トランジスタモジュールは浮遊インダクタンスが大きい
ため、ターンオン時の主回路電流に大きなアンバランス
が生じ、また、負荷短絡によるオフ時のサージ電圧が大
きくトランジスタを破壊することがあるなどの欠点があ
った。
Since the conventional parallel connection structure of transistor modules is configured as described above, there is a large impedance difference between each transistor module, and the transistor module at the far end from the feed point has a large stray inductance, so the main circuit at turn-on is There were drawbacks such as a large current imbalance, and a large surge voltage when off due to a load short circuit that could destroy the transistor.

〔発明の概要〕[Summary of the invention]

この発明は上記のような従来のものの欠点を除去するた
めになされたもので、主回路導体を給電点を支点として
左右対称な天秤形の平行導体構造として、主回路電流を
最適バランスに保ち、オフ時のサージ電圧を最小にでき
るトランジスタモジュールの並列接続構造を提供するこ
とを目的としている。
This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and the main circuit conductor is made into a horizontally symmetrical parallel conductor structure with the feeding point as the fulcrum to maintain the main circuit current in an optimal balance. The purpose of this invention is to provide a parallel connection structure of transistor modules that can minimize surge voltage when off.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を第3図fa)、(b)に基
づいて説明する。
Hereinafter, one embodiment of the present invention will be described based on FIGS. 3fa) and 3(b).

第3図(a)は本発明の並列接続構造を示し、第3図(
B)は同(21図の側面図を示す。また第4図は第3図
(→、(b)の回路図である。各図中第1図(a)、(
b)、第2図と同一符号のものは同一要素を示す。第3
図(→、(b)において、28〜2Cは給電点3aを支
点として左右対象な天秤形に形成された主回路導体であ
り、各トランジスタモジュール1aかうlfの受電点で
あるAC端子、N端子、P端子夫々に対し最短距離とな
るよう形成されている。また各主回路導体23〜2Cは
各トランジスタモジュール1a〜1fのAC端子、N端
子、P端子に対しネジ等で接続されている。また、各主
回路導体2a〜2Cは板状の平行導体であり、間に、絶
縁物6が密着し゛C介在されている。
Figure 3(a) shows the parallel connection structure of the present invention, and Figure 3(a) shows the parallel connection structure of the present invention.
B) shows the side view of Fig. 21. Fig. 4 is the circuit diagram of Fig. 3 (→, (b)).
b) The same reference numerals as in FIG. 2 indicate the same elements. Third
In the figure (→, (b), 28 to 2C are main circuit conductors formed in a symmetrical balance shape with the power feeding point 3a as the fulcrum, and the AC terminal and N terminal are the power receiving points of each transistor module 1a to lf. , P terminals, respectively.The main circuit conductors 23-2C are connected to the AC terminals, N terminals, and P terminals of each transistor module 1a-1f by screws or the like. Further, each of the main circuit conductors 2a to 2C is a plate-shaped parallel conductor, and an insulator 6 is closely interposed between them.

次に上記構成からなる実施例の作用を説明する。Next, the operation of the embodiment having the above configuration will be explained.

第3図(樟、tb>において、図示しない電源装置から
の主回路電流はリード+1J4a〜4cを介し、トラン
ジスタモジュール13〜1fに給電する給電点3a〜3
Cから各主回路導体28〜2Cを介して、夫々のトラン
ジスタモジュール1a〜1fの受電点である各AC端子
、N端子、P端子に各等距離で給電される。このことは
主回路導体23〜2Cを給電点を中心に左右全く対称に
天秤形として形成したこと姉より実現が可能となったも
のである。
In FIG. 3 (Chorus, tb>), the main circuit current from the power supply device (not shown) is supplied to the transistor modules 13 to 1f via the leads +1J4a to 4c at power supply points 3a to 3.
Power is supplied from C through each main circuit conductor 28 to 2C to each AC terminal, N terminal, and P terminal, which are power receiving points of each transistor module 1a to 1f, at equal distances from each other. This has been made possible by forming the main circuit conductors 23 to 2C in a balance shape that is completely symmetrical left and right with respect to the feed point.

従って、給電点3a〜3Cから各トランジスタモジュー
ル1a〜Ifの受電点に対し等しい主回路電流が流れ、
給電点3a〜3cから見たインピーダンスが第4図によ
り示されている通り同インピーダンスとなり、各トラン
ジスタモジュール間のインピーダンス差を最小限にする
ことが可能である。
Therefore, the same main circuit current flows from the power supply points 3a to 3C to the power receiving points of each transistor module 1a to If.
The impedances seen from the feed points 3a to 3c are the same as shown in FIG. 4, and it is possible to minimize the impedance difference between each transistor module.

同時に、2a〜2Cの各主回路導体が平行に配置され、
各主回路導体2a〜20間に絶縁物が介在されているた
め、浮遊インダクタンスを夫々打消すように作用する。
At the same time, each main circuit conductor of 2a to 2C is arranged in parallel,
Since the insulator is interposed between each of the main circuit conductors 2a to 20, it acts to cancel out stray inductance.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、主回路導体を給電点
から左右対称な天秤形で形成したので、各トランジスタ
モジュールに対し等しい主回路電−流を流すことができ
、ターンオン時の主回路電流が最適バランスとなり、負
荷短絡におけるOFF時の電圧を最小限にできる信頼性
の高いトランジスタモジュールの並列接続構造が得られ
る効果がある。
As described above, according to the present invention, the main circuit conductor is formed in a symmetrical balance shape from the power supply point, so that an equal main circuit current can flow to each transistor module, and the main circuit conductor at turn-on can be This has the effect of providing a highly reliable parallel connection structure of transistor modules in which the current is optimally balanced and the OFF voltage in the event of a load short circuit is minimized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は従来のトランジスタモジュールの並列接
続構造を示す構造図、第1図(b)は同側面図、第2図
は同回路図、第3図(a)はこの発明の一実施例姉よる
トランジスタモジュールの並列接続構造を示す構造図、
第3図(b)は同側面図、第4図は同回路図である。 1a〜1f・・・トランジスタモジュール、23〜2C
・・・主回路導体、38〜3C・・・給電点、6・・・
絶縁物。 なお、図中、同一符号は同一、又は相当部分を示す。 特許出願人 三菱電機株式会社
FIG. 1(a) is a structural diagram showing a parallel connection structure of a conventional transistor module, FIG. 1(b) is a side view of the same, FIG. 2 is a circuit diagram of the same, and FIG. A structural diagram showing a parallel connection structure of transistor modules according to an embodiment,
FIG. 3(b) is a side view of the same, and FIG. 4 is a circuit diagram of the same. 1a to 1f...transistor module, 23 to 2C
...Main circuit conductor, 38~3C...Feeding point, 6...
Insulator. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation

Claims (1)

【特許請求の範囲】[Claims] 複数のトランジスタモジュールを使用したインバータ等
の電力機器において、上記複数のトランジスタモジュー
ルに対する給電経路である複数の導体が給電点を支点と
して左右対称な天秤形で形成され、この天秤の竿先端部
から上記各トランジスタモジュールの受電点までの距離
が最短となる形状を成し、これら複数の導体間に絶縁物
を介在させ上記各導体間が平行忙配置された主回路導体
を備えたことを特徴とするトランジスタモジュールの並
列接続構造。
In a power device such as an inverter using a plurality of transistor modules, a plurality of conductors, which are power supply paths for the plurality of transistor modules, are formed in a symmetrical balance shape with the power supply point as a fulcrum, and from the tip of the pole of the balance to the above-mentioned conductors. The main circuit conductor is shaped so that the distance to the power receiving point of each transistor module is the shortest, and the main circuit conductors are arranged parallel to each other with an insulator interposed between the plurality of conductors. Parallel connection structure of transistor modules.
JP59056223A 1984-03-26 1984-03-26 Parallel connecting structure of transistor module Pending JPS60200560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59056223A JPS60200560A (en) 1984-03-26 1984-03-26 Parallel connecting structure of transistor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59056223A JPS60200560A (en) 1984-03-26 1984-03-26 Parallel connecting structure of transistor module

Publications (1)

Publication Number Publication Date
JPS60200560A true JPS60200560A (en) 1985-10-11

Family

ID=13021103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59056223A Pending JPS60200560A (en) 1984-03-26 1984-03-26 Parallel connecting structure of transistor module

Country Status (1)

Country Link
JP (1) JPS60200560A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62221878A (en) * 1986-03-13 1987-09-29 Mitsubishi Electric Corp Inverter circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62221878A (en) * 1986-03-13 1987-09-29 Mitsubishi Electric Corp Inverter circuit

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