JPS60198760A - Soldering method - Google Patents

Soldering method

Info

Publication number
JPS60198760A
JPS60198760A JP59054909A JP5490984A JPS60198760A JP S60198760 A JPS60198760 A JP S60198760A JP 59054909 A JP59054909 A JP 59054909A JP 5490984 A JP5490984 A JP 5490984A JP S60198760 A JPS60198760 A JP S60198760A
Authority
JP
Japan
Prior art keywords
metal
brazing
gold
layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59054909A
Other languages
Japanese (ja)
Other versions
JPH0230185B2 (en
Inventor
Yuzo Shimada
嶋田 勇三
Kazuaki Uchiumi
和明 内海
Masanori Suzuki
正則 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59054909A priority Critical patent/JPS60198760A/en
Publication of JPS60198760A publication Critical patent/JPS60198760A/en
Publication of JPH0230185B2 publication Critical patent/JPH0230185B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable treatment at low temperatures in a neutral atmosphere by a method wherein a film of a metal of the group VIa is formed at the part of soldering on a ceramic substrate, and a film of a metal of the group VIII is formed thereon; then, an input-output electrical connection pin of solder is soldered thereon. CONSTITUTION:A chromium film 33 of 300Angstrom -1,000Angstrom thickness is formed on the surface of a multilayer ceramic substrate 31. A layer 34 of palladium a metal of the group VIII is successively formed from above the chromium film 33. The ceramic substrate having a metallic pad is placed on a plurality of the input-output electrical connection pins 36 made of kovar or 4.2 alloy to which an alloy 35 having a weight ratio of Au 80% and Sn 20% has been installed respectively to approx. 1-3mg, and is thus bonded on the layer of palladium a metal of the group VIII. The surface of the metallic pin 36 is coated with an Au coat layer 37 formed by plating and the like.

Description

【発明の詳細な説明】 (産業上の利用分野) 発明明祉、パッケージ基板における入出力電気接続ピン
を接着する方法に係シ、更に具体的にいえば多層セラミ
ック基板の接続ピンを基板に結合させるための接合手段
に係る@ (従来技術) 最近のコンビエータシステム等の高密度小型化、高速化
および高パフォーマンス化に対して実装レベルにおける
パッケージ基板の要求はますますきびしいものになって
きている。具体的にはパッケージ基板において配線密度
を高め信号線幅を微細化すること、信号線導体の抵抗値
を下げること、絶縁材料の誘電率を下げること等が要求
されておル、これに応えるようなパッケージ基板技術が
開発されてきた。例えばアルミナグリーンシートを用い
た多層セラミック基板、ガラスセラミックグリーンシー
トを用In900℃程度で焼結出来合および銀−パラジ
ウム系導体が使える低温焼結多層セラミック基板、また
セラミック基板上ヘスバッタ、蒸着等の薄膜技術を用い
たパッケージ基板、更には有機絶縁材料(ポリイミド等
)を用い薄膜導体と組み合せたパッケージ基板等々があ
る□このような高密度化、微細化された実装基板上べは
超LSIチップが多数実装さ鱈′ることになシ、したが
って、基板外部と電気的に接続するための入出力端子数
は極めて多くなってくる◎そのため入出力端子を多層基
板裏面にビンで形成する技術が開発されている◎ る従来技術としては、例えばアルミナ多層基板において
銀ろうを用いてコバール又は4・2アロイ等の材質の接
続ビンを取シ付けていた0第1図は、従来方法を説明す
るための図であシ、アルミナグリーンシートに形成した
モリブデン又はタングステン等の導体パッドおよびスル
ーホール中の導体を1500℃以上の温度で還元雰囲気
中で焼結したのちのセラミック基板1およびモリブデン
又はタングステン等の導体2が示されている0この導体
パッド部分にメッキによルニッケル層3を形成し、次に
、コパール又は4・270イの接続ビン5を銀ろ54に
よシ取シ付けている。銀ろうの組成は、一般にはAg6
0mo/fb−Cu40rrDl!*の共晶合金が使わ
れておル融点は779℃でアル、ろう付は処理温度q8
10℃程度であ)、そリブデン等の導体の酸化を防ぐた
めに水素還元雰囲気中で行なわれる0次に基板に*!!
?付けられた接続ビンおよび導体が劣化しないように金
メッキ処理される。第2図に杜、金層6が形成された接
続ビン付き基板を示す0本方法はろう付は処理温度が高
く、基板上に形成した微細薄膜パターン等は、この温度
に加熱すること位難かしく、一方あらかじめビンを基板
に取シ付妙たのち信号線等の微細薄膜パターンを形成す
る場合においても、ビン付き基板上へ各種パターンを形
成する際の精度が悪くなシ、作業性も低下する0また有
機絶縁フィμム(ポリイミド等)を用いて多層セツミッ
ク基板上へパターンを形成するパッケージ技術の場合で
も同様でちる。更にろう付は後接続ピンおよび導体パッ
ド部を金メッキする工程が含まれ作業性が悪い0 次に処理温度を低げるためにろう材としてAu −8n
又はAu−8i 、 Au−8n−Pd 、 Au−a
n−Ag等が検討され九〇具体的な一例を第3図および
第4図に示す◎第3図においてはセラミック基板11の
表面にモリブデン層12を付着させ、該そリプデン層上
にメッギ法等の手段によシニッケルの被膜13を形成す
る□次に該ニッケル被膜上に金ペーストによシ金の被膜
14を形成し熱処理によル金・ニッケル固溶体を形成し
ている0続いて金メッキ17を施した接続ビン16をA
u−8nろう材15によ多結合している。この方法にお
いて金・ニッケル固溶体を形成する際には約700℃の
温度で水素還元中で行なっている・ま九第4図において
はセラミック基板210表面にモリブデン層22を付着
させ、該モリブデン層上にニッケル被膜′23を形成し
、該ニッケル被膜上へ障壁用の金被膜24を形成してい
る。該金被膜上には8n ゲッタリング金属のソースと
して働く第1族の金属層25で被覆されたのち、金メッ
キ28を施した接続ビン27をAu−8111ろう材2
6によ多結合されている。ζね。
[Detailed Description of the Invention] (Field of Industrial Application) The invention relates to a method for bonding input/output electrical connection pins on a package substrate, more specifically, to a method for bonding connection pins of a multilayer ceramic substrate to the substrate. (Prior art) The requirements for package substrates at the mounting level are becoming increasingly strict due to the recent miniaturization, high speed, and high performance of recent combinator systems, etc. . Specifically, there are demands for increasing wiring density and miniaturizing signal line widths on package substrates, lowering the resistance value of signal line conductors, and lowering the dielectric constant of insulating materials. A new package substrate technology has been developed. For example, multilayer ceramic substrates using alumina green sheets, low-temperature sintered multilayer ceramic substrates that can be sintered at about 900℃ using glass ceramic green sheets, and low-temperature sintered ceramic substrates that can use silver-palladium conductors, and thin films such as Hesbatter or vapor deposition on ceramic substrates. There are package substrates that use advanced technology, and even package substrates that combine organic insulating materials (polyimide, etc.) with thin film conductors.□On these high-density, miniaturized mounting substrates, there are many ultra-LSI chips. Therefore, the number of input/output terminals for electrical connection with the outside of the board becomes extremely large. Therefore, a technology was developed to form input/output terminals in the form of pins on the back side of the multilayer board. ◎ As a conventional technique, for example, a connecting pin made of Kovar or 4.2 alloy was attached to an alumina multilayer board using silver solder. The figure shows a ceramic substrate 1 and a conductor made of molybdenum or tungsten after sintering conductor pads made of molybdenum or tungsten formed on an alumina green sheet and conductors in through holes at a temperature of 1500°C or higher in a reducing atmosphere. A nickel layer 3 is formed on this conductor pad portion by plating, and then a connecting pin 5 made of copal or 4.270 mm is attached to a silver filter 54. The composition of silver solder is generally Ag6
0mo/fb-Cu40rrDl! *The eutectic alloy used has a melting point of 779℃, and the processing temperature for brazing is q8.
(at about 10℃), the zero-order substrate is processed in a hydrogen reducing atmosphere to prevent oxidation of conductors such as sorybdenum. !
? The attached connection pins and conductors are gold-plated to prevent deterioration. Figure 2 shows a board with a connecting bottle on which a gold layer 6 is formed.The brazing method requires a high processing temperature, and it is difficult to heat fine thin film patterns formed on the board to this temperature. However, on the other hand, even when forming fine thin film patterns such as signal lines after attaching the vials to the substrate, the accuracy of forming various patterns on the substrate with vials is poor and the workability is also reduced. The same applies to packaging technology in which patterns are formed on multilayer ceramic substrates using organic insulating films (polyimide, etc.). Furthermore, brazing involves the process of gold-plating the connection pins and conductor pads, resulting in poor workability.Next, in order to lower the processing temperature, Au-8n is used as a brazing material.
Or Au-8i, Au-8n-Pd, Au-a
n-Ag, etc. have been studied, and a specific example is shown in FIGS. 3 and 4. In FIG. □Next, a gold coating 14 is formed using gold paste on the nickel coating, and a gold/nickel solid solution is formed by heat treatment.Next, gold plating 17 is applied. The connection bottle 16 that has been
It is multi-bonded to the U-8N brazing filler metal 15. In this method, the gold-nickel solid solution is formed under hydrogen reduction at a temperature of about 700°C. A nickel film '23 is formed on the nickel film, and a gold film 24 for a barrier is formed on the nickel film. The gold coating is coated with a group 1 metal layer 25 that serves as a source of 8N gettering metal, and then a connection vial 27 plated with gold 28 is coated with an Au-8111 brazing material 2.
6. ζ.

らの方法においては、いずれも中間層として金層を形成
しなければならずコスト的にも不利である。
In both of these methods, a gold layer must be formed as an intermediate layer, which is disadvantageous in terms of cost.

また接続ビンを取シ付けるパッド部分には、あらかじめ
モリブデンパッドを形成しておかなければならず工程的
にもコスト的にも不利であシ、さらにろう付は等の熱処
理に際してもモリブデンの酸化を防ぐために水素還元雰
囲気で行なわなければならなかった口さらにモリブデン
パッドとセラミック基板との密着性をもたせるためにガ
ラスフリット等の添加物をモリブデンペースト中に含め
ねばならず、導体抵抗も高くなる問題があった〇(発明
の目的) 本発明の目的は、このような従来の欠点を除去せしめ、
従来の銀ろう材を用いる方法よシも低温(400℃以下
)でしかも中性雰囲気で熱処理が出来。
In addition, molybdenum pads must be formed in advance on the pads to which the connecting bottles are attached, which is disadvantageous in terms of process and cost.Moreover, even during heat treatment such as brazing, molybdenum oxidation is prevented. In addition, additives such as glass frit must be included in the molybdenum paste to ensure good adhesion between the molybdenum pad and the ceramic substrate, which increases conductor resistance. Yes (Objective of the invention) The object of the present invention is to eliminate such conventional drawbacks,
Unlike the conventional method using silver brazing material, heat treatment can be performed at low temperatures (below 400°C) and in a neutral atmosphere.

また他の従来法で示したような障壁用の金被膜を施さず
、更にはピン取ル付は部分のモリブデンパッドを形成し
ない非常に単純な構造をもち、作業性およびコスト的に
有利でしかも十分なピン接着強度を有するろう付は方法
を提供することにある。
In addition, unlike other conventional methods, the gold coating for barriers is not applied, and the pin attachment has a very simple structure without forming molybdenum pads, which is advantageous in terms of workability and cost. It is an object of the present invention to provide a method for brazing with sufficient pin bond strength.

(発明の構成) すなわち本発明は、セラミック基板上のろう付けする部
分に周期率表第■a族の金属膜を形成する工程と該クロ
ム膜上に周期律表の第1族の金属膜を形成する工程と、
ろう材によル入出力電気接続ピンを第■族金属層上にろ
う付けする工程とを有することを特゛徴とするろう付は
方法である◎(実施例) 以下本褪明を実施例に基づいてその具体例を詳第5図〜
第8図は本発明のろう付は方法を示す図であル第9図は
実施例において作製したピン付きセラミック基板の概略
図である0第5図に示すように多層セラミック基板31
のセラミック表面上に金属の薄板をエツチング等の手段
により形成したろう付は部分の空いているマスク32を
重ね合わせるロ多層セツミック基板31は、アルミナグ
リーンシートを用い導体としてモリブデン又はタングス
テン等を印刷し積層プレス後1500℃以上の水素還元
雰囲気中で焼結したものでもよく、あるいはホウクイ酸
鉛系結晶化ガラスとアルミナから出来ているガラス七2
ぐツクグリーンシートを用い、導体として金二銀、銀−
パラジウム基、金−白金系、銀−白金系等を印刷し、積
層プレス後1000℃以下の酸化性雰囲気中で焼結した
いわゆる低温焼結多層セラミック基板等でもよい◇不実
施例で鉱銀−バ2ジウムを用いた後者の基板を用いた。
(Structure of the Invention) That is, the present invention includes a step of forming a metal film of Group Ⅰa of the periodic table on a portion to be brazed on a ceramic substrate, and a step of forming a metal film of Group 1 of the periodic table on the chromium film. a step of forming;
Brazing is a method characterized by comprising the step of brazing input/output electrical connection pins onto the Group ① metal layer using a brazing filler metal. Detailed examples are shown in Figure 5 based on
FIG. 8 is a diagram showing the brazing method of the present invention. FIG. 9 is a schematic diagram of a ceramic substrate with pins produced in an example. As shown in FIG. 5, a multilayer ceramic substrate 31
For brazing, a thin metal plate is formed by etching or other means on the ceramic surface of the multilayer ceramic board 31, which is formed by overlapping a mask 32 with an open area.The multilayer ceramic board 31 is made of an alumina green sheet and printed with molybdenum or tungsten as a conductor. It may be sintered in a hydrogen reducing atmosphere at 1500°C or higher after laminated pressing, or it may be a glass made from lead borosinate crystallized glass and alumina.
Using Gutsuku Green Sheet, gold, silver and silver are used as conductors.
So-called low-temperature sintered multilayer ceramic substrates printed with palladium, gold-platinum, silver-platinum, etc. and sintered in an oxidizing atmosphere at 1000°C or less after laminated pressing may also be used. The latter substrate using barium was used.

次に第Ma族金属からりpムを選び被膜を形成した◎第
6図に示すように、セラミック基板に重ね合わされたマ
スクの上からスパッタリングによシ300X〜100O
Xの厚さのりpム膜33を形成する口第6図で形成した
りqム膜の上から続けて周期律表の第1族の金属のなか
からパラジウム層34を第7図に示すように形成する。
Next, a film was formed from a Ma group metal.
Forming the PM film 33 with a thickness of to form.

パラジウム層紘り四ム薄膜形成と同様のスパックリング
によ1)100OX〜3000Xの厚さに表るように形
成した◎スパッタは10 torr以下にした後、Ar
ガスを10 torr程度まで導入して行なった。第8
図にはクロム薄膜、第■族金属の膜を形成したのちマス
クを除去したときの断面図を示す。第8図かられかるよ
うに本方法では、セラミック基板表面に直接にクロム膜
が形成されておルこの点が他の方法と大きく異なりてい
る特徴の一つである。
The palladium layer was formed by spackling similar to the process used to form thin films.
The gas was introduced to about 10 torr. 8th
The figure shows a cross-sectional view when the mask is removed after forming a chromium thin film and a Group Ⅰ metal film. As can be seen from FIG. 8, this method is characterized in that a chromium film is formed directly on the surface of the ceramic substrate, which is one of the features that differs greatly from other methods.

このようにして得られ九゛金属パッド部を有するセラミ
ック基板を金80%錫20チの重量比の合金ろう材35
がそれぞれ1〜3mg程度取付けられた複数のコバール
又は4・2アロイ等の材質の入出力電気接続用ビン36
上に置き、第■族金属であるパラジウム層上に結合させ
る0第9図には以上の方法によシ取シ付けられた接続ピ
ン付き多層セラミック基板の模式図を示しであるが、金
属製ビン360表面にはメッキ等によ多形成した金の被
膜層37がコートしである◎ろう付けを行なり処理温度
としては、金80%錫20%の重量比の合金ろう材の融
点が280℃であることから、300℃〜450℃の温
度範囲で10〜30分で行なった0第■族の金属例えば
パラジウム層は金−錫ろう材の錫のゲッタリングを引き
起こし、金の錫に対する見かけの割合を多くすることに
なシ、したがって冷却後又はろう材の凝縮後にろう付け
した結合部分の融点を上昇する効果がある0このことは
ピン取ル付は後の熱サイクルを加える工程を有する場合
に対して有効である0また接続ビンに總した金被膜層に
おいても、ろう付は処理の際、金被膜層が金−錫ろう材
と共に一部融けるととKなル金−錫ろう材中の金の割合
が増加し結合部分の融点を上昇させ同様の効果が得られ
る0本方法によシろう付けした入出力電気接続インと多
層セラミック基板との接着強度は4.OKf/−以上を
示し、実装基板の入出力ビンとして十分な強度を示す◇ (発明の効果) 以上の如く1本発明のろう付は方法を採用することによ
シ、ろう付は処理を400℃以下という極めて低温で、
しかも中性雰囲気中で行なうことが出来、セラミック基
板表面にビンパッド用の厚膜金属(モリブデン、タング
ステン、金、銀;銀−パラジウム等)層をあ゛らかしめ
形成する必要がなく、また障壁用の金被膜も施さない単
純な構造をもりた十分な接着強度を有するビン付き基板
を得ることが出来るようになりた。さらに本発明の方法
はビンパッドの金属層を形成する際にエツチング等の湿
式1程を経ないためにセラミックに対する悪影響は全く
与えず信頼性の高いビン付き基板を提供することが出来
、また作業性およびコスト的にも有利となシ、ピン付は
後の熱サイクルに対しても十分に強いピン付は基板を得
るととが出来るようになつた〇 なお、クロムでなくモリブデンやタングステンなどの第
Via族の金属を使用することができ、またパラジウム
の他の第1族の金属4使用できるロスバッタリングの他
に適時、蒸着、メッキ、スクリーン印刷などの膜形成手
段を用いることができる。
The thus obtained ceramic substrate having a metal pad portion of 9.5 mm was then used as an alloy brazing material of 80% gold and 20% tin.
A plurality of input/output electrical connection bins 36 made of materials such as Kovar or 4.2 alloy, each with approximately 1 to 3 mg of
Figure 9 shows a schematic diagram of a multilayer ceramic board with connection pins attached by the above method. The surface of the bottle 360 is coated with a gold coating layer 37 formed by plating or the like. ◎ Brazing is performed and the processing temperature is such that the melting point of the alloy brazing material with a weight ratio of 80% gold and 20% tin is 280. ℃, a layer of Group 0 metal, such as palladium, formed in a temperature range of 300℃ to 450℃ for 10 to 30 minutes will cause gettering of tin in the gold-tin brazing material, and the appearance of gold with respect to tin will increase. Therefore, it is effective to increase the melting point of the brazed joint after cooling or condensation of the brazing filler metal. 0 Also, with respect to the gold coating layer placed on the connecting bottle, brazing may be difficult if the gold coating layer partially melts together with the gold-tin brazing material during processing. The adhesion strength between the input/output electrical connection ins and the multilayer ceramic substrate, which are brazed using the 0-wire method in which the proportion of gold increases and the melting point of the bonded part is increased to achieve the same effect, is 4. It shows OKf/- or more and shows sufficient strength as an input/output bin of a mounting board. At extremely low temperatures below ℃,
Moreover, it can be carried out in a neutral atmosphere, and there is no need to form a thick metal (molybdenum, tungsten, gold, silver; silver-palladium, etc.) layer for the via pad on the surface of the ceramic substrate, and it is not necessary to form a layer for the barrier pad. It has now become possible to obtain a bottled substrate with a simple structure that does not require any gold coating and has sufficient adhesive strength. Furthermore, since the method of the present invention does not involve a wet process such as etching when forming the metal layer of the bottle pad, it does not have any adverse effects on the ceramic and can provide a highly reliable substrate with a bottle. It is also advantageous in terms of cost, and it has become possible to use pins that are strong enough to withstand subsequent thermal cycles. Via group metals can be used, and film forming means such as vapor deposition, plating, screen printing, etc. can be used as appropriate in addition to loss battering, which can use metals of group 1 other than palladium.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第4図は、従来のピン付はセラミック基板を示
した図であ夛、第5図〜第8図は本発明の方゛法を示す
図であシ、第9図は本発明の方法によシ作製したピン付
き基板の模式図である。 図において、1,11,21,31・・・セラミック基
板、2. 12. 22・・・厚膜導体パッド層、3゜
13、23・・・ニッケル層、4・・・銀ろり、5,1
6゜27.36・;・金属ピン、6,17,28,37
・・・金被膜層、14・・・金被膜、15,26.35
・・・金−錫ろ9.24・・・金被膜、25・・・パラ
ジウム層、32・・・マスク、33・・・クロム膜、3
4・、・・パラジウム膜。 第1図 兜2図 男3図 第4図 第5図 2
Figures 1 to 4 are diagrams showing conventional ceramic substrates with pins, Figures 5 to 8 are diagrams showing the method of the present invention, and Figure 9 is a diagram showing the method of the present invention. FIG. 2 is a schematic diagram of a pin-equipped substrate manufactured by the method of the invention. In the figure, 1, 11, 21, 31...ceramic substrate, 2. 12. 22...Thick film conductor pad layer, 3゜13, 23...Nickel layer, 4...Silver solder, 5,1
6゜27.36・;・Metal pin, 6,17,28,37
... Gold coating layer, 14... Gold coating, 15, 26.35
...Gold-tin layer 9.24...Gold coating, 25...Palladium layer, 32...Mask, 33...Chromium film, 3
4... Palladium membrane. Figure 1 Helmet Figure 2 Man Figure 3 Figure 4 Figure 5 Figure 2

Claims (2)

【特許請求の範囲】[Claims] (1)セラミック基板に金属製接続ピンをろう材によシ
ろう付けする方法でらりて、上2ミック基板上のろう付
けする部分に周期律表第Ma族の金属膜を形成する工程
と、該第Ma族の金属膜上に周期律表の第1族の金属膜
を形成する工程と、ろう材によ多接続ピンを該第■族金
属層上にろう付けする工程とを有することを特徴とする
ろう付は方法0
(1) A step of brazing metal connection pins onto a ceramic substrate using a brazing material, and forming a metal film of group Ma of the periodic table on the part to be brazed on the upper two-layer substrate. , comprising a step of forming a metal film of Group 1 of the periodic table on the metal film of Group Ma, and a step of brazing a multi-connection pin with a brazing material onto the metal layer of Group Ⅰ. Brazing method 0 is characterized by
(2)ろう材は金−錫ろう材である特許請求の範囲第1
項記載のろう付は方法0
(2) Claim 1: The brazing material is a gold-tin brazing material.
Brazing described in section 0 is method 0.
JP59054909A 1984-03-22 1984-03-22 Soldering method Granted JPS60198760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59054909A JPS60198760A (en) 1984-03-22 1984-03-22 Soldering method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59054909A JPS60198760A (en) 1984-03-22 1984-03-22 Soldering method

Publications (2)

Publication Number Publication Date
JPS60198760A true JPS60198760A (en) 1985-10-08
JPH0230185B2 JPH0230185B2 (en) 1990-07-04

Family

ID=12983724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59054909A Granted JPS60198760A (en) 1984-03-22 1984-03-22 Soldering method

Country Status (1)

Country Link
JP (1) JPS60198760A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61146958U (en) * 1985-03-04 1986-09-10

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58119663A (en) * 1981-12-31 1983-07-16 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン Method of bonding connecting pin

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58119663A (en) * 1981-12-31 1983-07-16 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン Method of bonding connecting pin

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61146958U (en) * 1985-03-04 1986-09-10
JPH0132364Y2 (en) * 1985-03-04 1989-10-03

Also Published As

Publication number Publication date
JPH0230185B2 (en) 1990-07-04

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