JPS60198749A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten a signal retardation-time by preventing a division into two of the inside of a fundamental circuit cell for a logic gate circuit by a diffusion resistor and shortening wiring length between a collector in an input transistor (Tr) and a base in a Tr for an emitter follower. CONSTITUTION:A fundamental circuit such as a non-threshold-logic circuit (NTL) constituting a master slice LSI is formed to an active region 1. P type diffusion regions 2 as base regions in three bipolars Trs Q1, Q2, Q3 for inputs are disposed in the active region 1 in an approximately one row in the longitudinal directon. An N type diffusion region 3 as a common collector region for said Trs is shaped to the lower section on the right side of the base regions, and a resistor 4 is formed next the diffusion region 3 and a P type diffusion region 5 as a base region in a TrQ4 for an emitter follower is further shaped. Accordingly, the length of a wiring L is made the shortest becuase the inside of a fundamental circuit cell is not divided by the diffusion resistor 4 and the regions 3, 4, 5 are disposed in an approximately rectilinear manner.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to circuit technology, and more particularly, to a technology that is particularly effective when applied to the layout of elements in electronic circuits.
For example, it relates to techniques that are effective when applied to semiconductor integrated circuits.

[Background Art] As a basic circuit constituting a logic LSI formed by the master slice method (hereinafter referred to as master slice LSI), for example, a non-threshold logic circuit (hereinafter referred to as NTL circuit) as shown in FIG. )It has been known. In this case, the LSI is constructed by using the circuit shown in FIG. 1 as a basic cell (circuit unit) and arranging it like a base.

Therefore, the inventor of the present invention has devised a method of arranging the elements (especially input transistors) in the basic cell as shown in FIG. 1, for example, in the same manner as shown in FIG. However, in the layout method shown in FIG. 2, the active region is divided into two by the collector resistance Re. Therefore, the active region cannot be used effectively, and the common collector C of the input transistors Q1 to Q3 and the emitter follower EF transistor Q4
It has been found that there is a problem in that the length of the wiring that connects the base b of the device to the base b is not the shortest, and the delay time due to the wiring capacitance is also increased.

[Object of the Invention] An object of the present invention is to provide a circuit technology that achieves remarkable results compared to the prior art.

Another object of the present invention is to make it possible to effectively utilize the active region in a basic logic gate circuit and to reduce the signal propagation delay i time when applied to a bipolar logic integrated circuit, for example. The purpose is to make it possible.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief outline of typical inventions disclosed in this application is as follows.

That is, for example, in a master slice LSI whose basic circuit is an NTL circuit, a plurality of input transistors are arranged along one side of a collector resistor, and the common collector of the input transistors, one end of the collector resistor, and the emitter By arranging the base of the follower transistor so that it is aligned with the base of the follower transistor, it is possible to prevent the inside of the basic circuit cell from being divided into two by the diffused resistor and to effectively utilize the active region. This reduces the signal delay time by minimizing the wiring length between the bases of the transistors.

The second invention will be specifically described below with reference to the drawings.

[Embodiment] FIG. 3 shows an embodiment of a basic circuit cell when the present invention is applied to a master slice LSI.

In the figure, 1 is an NT constituting the master slice LSI.
It shows the active region where basic circuits such as L circuits are formed.

This active region 1 corresponds to one basic circuit cell, and its -@ (left side in the figure) includes, but is not particularly limited to,
Three input bipolar transistors Qx, Q2,
P-type diffusion regions 2, 2 .・・・・・・
are arranged substantially in rows along the vertical direction.

Then, the base regions 2, 2 . An N-type diffusion region 3 serving as a common collector region of the transistors Qx, Q2, and Qs is provided at the lower right side of the transistors Qx, Q2, and Qs, and adjacent to this diffusion region 3, a diffusion layer formed in the vertical direction is provided. A resistor 4 is provided. Further, below and further to the right of this resistor 4 (Rc), a P-type diffusion region 5 is formed which becomes the base region of the emitter follower transistor Q4.

Therefore, in the active region l where the basic circuit cell is formed, the input transistors Q, ~Q3 are arranged tightly on one side of the cell (to the left of the diffused resistor 4) as shown in the drawing. Become. Because of this, the interior of the basic circuit cell is no longer divided into two by the diffused resistor 4, and a blank area where other circuit elements can be formed is concentrated on the right side of the diffused resistor 4.

As a result, by utilizing the wide blank area formed in this way, it is now possible to form here a speed-up capacitor C5, etc., which improves the operating speed of the NTL circuit, thereby increasing the activation speed within the cell. Effective use of area becomes possible.

Moreover, as shown in FIG.
The common collector region 3 of Q3, the diffused resistor 4, and the base region 5 of emitter follower transistor Q4 are arranged substantially on a straight line.

Therefore, the length of the wire connecting the common collector region 3, one end of the diffused resistor 4, and the base region 5 of the transistor Q4 is minimized, and the capacitance of the wire connected to the collectors of the input transistors Q1 to Q3 is reduced.゛Thus, N
It has been found that the signal delay time in the TL circuit is shortened and the operating speed of the circuit is improved by approximately 10%.

Furthermore, by utilizing the expanded blank area within the cell, it is possible to form a larger speed-up capacitor than that of FIG. As a result, it was found that by providing a speed-up capacitor C5 with a large capacity, the delay time of the NTL circuit can be further improved by about 10%.

Although not particularly limited, the speed-up capacitor C8 is formed by forming a relatively large bipolar transistor in the blank area, and connecting it between the common emitter of the input transistor and the power supply voltage during wiring formation by the master slicing method, so that its base It uses parasitic capacitance between emitters.

Furthermore, in the blank area to the right of the diffused resistor 4, in addition to the speed-up capacitor Cs, as shown in FIG. 5, resistors R4, R, and a diffusion region 4 that constitutes a resistor Re connected to the emitter side of the input transistors Q1 to Q3 may be provided.

According to the present invention, input transistors Q1 to Q3 are connected to cells (
Since a large blank area is concentrated on the right side of the diffused resistor 4, when an element constituting an emitter follower is formed here as described above, the basic circuit cell is It can be configured in a small area.

In addition, the reference numeral Q6 in FIG. 4 is a transistor that can be selectively connected to the common emitter of the input transistors Q1 to Q3, and its emitter is connected to the common emitter of the input transistors Q1 to Q3, and the base is connected to the common emitter of the input transistors Q1 to Q3. By applying an appropriate reference voltage VBa to the circuit, the circuit can be constructed into a semi-threshold logic circuit as shown in FIG. By configuring the circuit as a semi-threshold logic circuit in this way, the circuit margin can be improved and resistance to noise can be increased.

Further, the basic circuit cells 1 are arranged symmetrically with respect to the chain line A as shown in FIG. 6, and four basic circuits are arranged symmetrically with respect to the chain line B. As one unit, these are arranged in a grid pattern, and the power supply voltage is intensively supplied to each circuit from the intersection of each basic circuit cell as shown by symbols D s , D 2 in Fig. 6. By doing so, it is possible to efficiently feed power to the entire LSI.

Although the above embodiments are applied to a master slice LSI whose basic circuit is an NTL circuit, the present invention can also be applied to an LSI whose basic circuit is an ECL circuit (emitter coupled logic circuit). It is possible.

Further, in the above embodiment, an NTL circuit having three input transistors is shown, but the number of input transistors is not limited to this, and is two.
It goes without saying that the number may be four or more.

The master slice has wiring channels (tracks) in the X and Y directions. The number of channels per circuit is preferably the same in both the X and Y directions.

When considering that wiring is performed between the i-th aluminum layer ALL and the second aluminum layer AL2, the wiring pitch of the aluminum layer ALI is smaller than that of the aluminum layer A.
It is generally smaller than that of L2. Therefore, if the number of channels per circuit is the same in both the X and Y directions,
The element area per circuit becomes horizontally long. According to the embodiments described above, it is possible to make the element area per circuit shorter in the horizontal direction than in the conventional case, and it is possible to make the chip size closer to a square.

[Effect] As explained above, in a logic gate circuit such as an NTL circuit that has a plurality of input transistors connected in parallel to each other, the plurality of input transistors are arranged on one side of the collector resistor along this. In addition, the common collector of the input transistor, one end of the collector resistor, and the base of the emitter follower transistor are arranged in a substantially straight line, so that the collector of the input transistor and the emitter follower transistor can be connected. By minimizing the length of the wiring, the capacitance of the wiring connected to the collector of the input transistor is reduced, which has the effect of shortening the signal delay time.

In addition, multiple input transistors are arranged along one side of the collector resistor, so that the inside of the basic circuit cell is not divided into two by the diffused resistor, and the blank area is concentrated in one place. This effect has the effect that circuit elements such as speed-up capacitors can be efficiently disposed here to reduce the area occupied by the circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. None).

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the master slice LSI, which is the field of application that formed the background of the invention, but it is not limited to this, and is applicable to bipolar logic. This can be applied to LSI in general.

[Brief explanation of the drawing]

Figure 1 shows the NTL which is the basic circuit of the master slice LSI.
2 is a plan view showing an example of the layout of elements constituting the NTL circuit; FIG. 3 is a plan view showing an example of the layout of the logic gate circuit according to the present invention; 4 is a plan view showing another embodiment of the layout of the logic gate circuit according to the present invention, FIG. 5 is a circuit diagram showing another example of the configuration of the logic gate circuit, and FIG. 6 is a plan view showing another example of the layout of the logic gate circuit according to the present invention. Ita Master Slice L
FIG. 2 is an explanatory diagram showing an example of a method of configuring S and I; 1...Active region (basic circuit cell), 2...Base region, 3...Collector region, 4...Diffused resistance, Q1-Q3...Input transistor, Re...・・・
Collector resistance, EF...emitter follower, C8
...Speed-up capacitor. Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device equipped with a logic gate circuit having a plurality of input transistors connected in parallel to each other, the plurality of input transistors are arranged along one side of a collector resistor. A semiconductor integrated circuit device, wherein a common collector terminal of the input transistor, one end of the collector resistor, and a base terminal of the output transistor are arranged substantially in a straight line. 2. A patent claim characterized in that the logic gate circuit is constituted by a non-threshold logic circuit, and is a master slice LSI configured with the non-threshold logic circuit as a basic logic gate circuit. The semiconductor integrated circuit device according to item 1.