JPS6019684B2 - Low power consumption multivibrator - Google Patents
Low power consumption multivibratorInfo
- Publication number
- JPS6019684B2 JPS6019684B2 JP52072500A JP7250077A JPS6019684B2 JP S6019684 B2 JPS6019684 B2 JP S6019684B2 JP 52072500 A JP52072500 A JP 52072500A JP 7250077 A JP7250077 A JP 7250077A JP S6019684 B2 JPS6019684 B2 JP S6019684B2
- Authority
- JP
- Japan
- Prior art keywords
- mosfet
- pair
- voltage
- gate
- mosfets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/354—Astable circuits
Description
【発明の詳細な説明】
本発明はC−MOSFETを採用した低消費電力マルチ
パイプレータに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a low power consumption multipipulator employing C-MOSFETs.
一般にマルチパイプレータには双安定マルチパイプレー
夕(フリップフロッブ回路)、単安定マルチパイプレー
タ、無安定マルチパイプレータ等があり、周波数分周回
路、演算回路、記憶回路、波形整形回路、発振回路等と
して利用されている。In general, multipipulators include bistable multipipulators (flip-flop circuits), monostable multipipulators, and astable multipipulators, which include frequency divider circuits, arithmetic circuits, memory circuits, waveform shaping circuits, and oscillation circuits. It is used as such.
このように利用されているマルチパイプレータ回路を移
動して使う機器例えば水晶腕時計等に内蔵する場合には
、小容量の電池で長時間連続して使用しなければならな
い。When the multipipelator circuit utilized in this manner is built into a mobile device such as a crystal wristwatch, it must be used continuously for a long time with a small capacity battery.
又電算機のように極めて多数の回路をまとめて使用する
場合には、論理演算素子として種々の機能を有するマル
チパイプレータ回路も数多く使用されることが多く、各
マルチパイプレータ回路でも消費される電力の合計は当
然大となる。従って、上述したように汎用性に富むマル
チパイプレータ自体での消費電力の低減を計ることは電
子機器の消費電力の低減を計る上で重要な意味を有する
。現在上記の低消費電力化の観点に立ちマルチパイプレ
ー夕をC一MOSIC回路で構成したものが実施されて
いるが、この回路を双安定マルチパイプレータを例にと
って説明する。In addition, when a large number of circuits are used together, such as in a computer, many multi-pipelator circuits that have various functions as logical operation elements are often used, and each multi-pipelator circuit also consumes energy. Naturally, the total amount of power will be large. Therefore, as described above, reducing the power consumption of the versatile multipipeter itself has an important meaning in reducing the power consumption of electronic equipment. Currently, from the viewpoint of reducing power consumption, a multi-pipe layer constructed of a C-MOSC circuit is being implemented, and this circuit will be explained by taking a bistable multi-pipulator as an example.
実用化されている回路では外部からトリガを加えるため
に周辺に付属の回路が設けられているが、基本的な動作
原理に関連した回路について第1図を参照して説明する
。TP,,TP2はP形MOSFETであり、TN.,
TN2はN形MOSFETであり、TP,とTN,及び
TP2とTN2は夫々相補形に接続されており、各C−
MOSFETのゲートG,,G2は共通に接続されてい
ると共にドレィン電極D,,D2も共通に接続されてい
る。In the circuit that has been put into practical use, an additional circuit is provided in the periphery in order to apply a trigger from the outside, and the circuit related to the basic operating principle will be explained with reference to FIG. TP,, TP2 are P-type MOSFETs, and TN. ,
TN2 is an N-type MOSFET, TP, and TN, and TP2 and TN2 are connected in a complementary manner, and each C-
The gates G, , G2 of the MOSFETs are commonly connected, and the drain electrodes D, , D2 are also commonly connected.
なおS,,9はP‐MOSFETTP,のソース電極、
補助ゲートであり、S,′,g,′はN−MOSFET
TN,のソース電極、補助ゲートである。又S2,g
2はP−MOSFET TP2のソース電極、補助ゲー
トであり、S2′,鞍′はN−MOSFETTN2のソ
ース電極補助ゲートである。1,,12は外部からのト
リガ信号を印加するための入力端でありC,,C2は回
路内の電極接続もしくは配線に基づく分布静電容量であ
って、外部から特別に接続したものではない。Note that S,,9 is the source electrode of P-MOSFETTP,
It is an auxiliary gate, and S,′,g,′ are N-MOSFETs.
This is the source electrode and auxiliary gate of TN. Also S2,g
2 is the source electrode and auxiliary gate of P-MOSFET TP2, and S2' and saddle' are the source electrode and auxiliary gate of N-MOSFET TN2. 1, 12 are input terminals for applying external trigger signals, and C, , C2 are distributed capacitances based on electrode connections or wiring within the circuit, and are not specially connected from the outside. .
第2図にこのマルチパイプレータのチャンネル電流IP
,INを縦軸にゲート電圧VGを機軸にとった特性図が
示されている。Figure 2 shows the channel current IP of this multipipulator.
, IN is shown on the vertical axis and the gate voltage VG is on the axis.
この第2図を参照するならば、直流バイアス電圧VGは
回路の動作開始時にはVthNくVG<(V。一Vth
P)なる不等式が成立する必要がある。言い換えるなら
ば電源電圧VDとしてVo>VthP+VthNを満足
する電圧が回路に印加されることになる。この時、仮に
P一MOSFETTP,がONになっていたとすれば、
ドレィン電極D,の電圧V。Referring to FIG. 2, the DC bias voltage VG is VthN when the circuit starts operating.VG<(V.-Vth
P) must hold. In other words, a voltage satisfying Vo>VthP+VthN is applied to the circuit as the power supply voltage VD. At this time, if P-MOSFETTP is turned on, then
Voltage V of drain electrode D.
,は略電源圧V。に等しくなるので、このドレィン電極
D,に接続された他方のC‐MOSFETの対のゲート
○2の電圧VG2も略電源電圧Voに等しい。それ故、
P一MOSFETTP2はOFFにN一MOSFETT
N2はONになつている。M−MOSFETTN2がO
Nであるためソース電極D2の電圧V。2はグラウンド
即ち略零しベルとなる。, is approximately the power supply voltage V. Therefore, the voltage VG2 at the gate 2 of the other C-MOSFET pair connected to the drain electrode D is also approximately equal to the power supply voltage Vo. Therefore,
P-MOSFET TP2 is OFF and N-MOSFET is OFF.
N2 is turned ON. M-MOSFETTN2 is O
Since the voltage is N, the voltage V of the source electrode D2. 2 is the ground, that is, almost zero and the bell.
従ってこのソース電極D2に接続されているゲートG,
の電圧Vc,は略零となるので、P−MOSFETTP
,はONに、N‐MOSFETTN,はOFFとなりこ
の状態を保持する。勿論、この反対にP−MOSFET
TP2とN−MOS FET TN,がONになり、P
−MOS FETTP,とN‐MOSFETTN2がO
FFの状態も全く同様に安定な状態であり、電流はしや
断されたままとなる。Therefore, the gate G connected to this source electrode D2,
Since the voltage Vc, of P-MOSFETTP is approximately zero,
, is turned ON, and N-MOSFETTN, is turned OFF and maintains this state. Of course, on the other hand, P-MOSFET
TP2 and N-MOS FET TN are turned on, and P
-MOSFETTP, and N-MOSFETTN2 are O
The state of the FF is also stable in exactly the same way, and the current remains briefly cut off.
この状態をB,の状態と呼び、前述したTP,力のNの
状態をA,の状態と呼ぶこととする。今、上述のA,の
状態で安定している回路に何等かの方法で外部からトリ
ガを加えB,の安定状態に移行させる場合を考える。This state will be called the state of B, and the state of TP and force N described above will be called the state of A. Now, let us consider the case where a trigger is applied externally by some method to the circuit which is stable in the above-mentioned state A to shift it to the stable state B.
A,の状態ではコンデンサC2は略電源電圧Voで充電
され、このコンデンサC2には電荷q2≠C2Voが蓄
積されており、コンデンサC,の電圧は略零しベルで電
荷は蓄えられていない。B,の状態になればコンデンサ
C,は略電源電圧Voで充電されコンデンサC2の電圧
は略零しベルとなる。In state A, capacitor C2 is charged with approximately the power supply voltage Vo, and charge q2≠C2Vo is stored in this capacitor C2, and the voltage of capacitor C is approximately zero and no charge is stored. When the state B is reached, the capacitor C is charged with approximately the power supply voltage Vo, and the voltage of the capacitor C2 becomes approximately zero and becomes a bell.
それ故、A,の状態からB,の状態に移る際に電源から
電荷q,≠C,Voが流れてコンデンサC,を充電し、
C2の電荷q2≠C2V。がアースに放流されることに
なる。従ってトリガが1秒間にf回加わってA,の状態
とB,の状態を交互に繰り返すとすれば、電源から流れ
る電流1,1,=(C,十C2)VD×f/2
…mとなる。Therefore, when moving from state A to state B, charge q,≠C,Vo flows from the power supply and charges capacitor C,
Charge of C2 q2≠C2V. will be discharged to earth. Therefore, if the trigger is applied f times per second and the states A and B are alternately repeated, the current flowing from the power supply is 1, 1, = (C, 10C2) VD x f/2
...m.
即ち電源から流出する鰭銃8,はコンデンサC,,C2
を電源電圧Voでf/幻団充放電する電流となるので、
回路で消費される電力を少なくするためにはコンデンサ
C,,C2の値を小さく抑えるか、電流電圧Voを低く
すれば可能となる。That is, the fin gun 8, which flows out from the power supply, is connected to the capacitor C, , C2.
is the current that charges and discharges f/phantom group at the power supply voltage Vo, so
In order to reduce the power consumed by the circuit, it is possible to reduce the values of the capacitors C, C2, or to lower the current voltage Vo.
しかしながり、コンデンサC,,C2はC一M06FE
Tの構造そのもので決るパラメータであり、電源電圧V
oは、VthP tv thNの値以上に設定すること
が必要であり、このVoも結局C−MOSFET自体の
特性から決定される。従って、原理的に従来の第1図に
示されるようなマルチパイプレータの回路では上記{1
1式で与えられる電流と電源電圧Voの積で決定される
電力より消費電力を少なくすることは困難となる。本発
明は、上記の従来例の欠点に鑑みてなされたもので、本
出願人が既に特磯昭52一2233「C−MOS回路」
に開示した個別バイアスをゲートに与える考え方にたっ
て、マルチパイプレータの消費電力の低減を計った低消
費電力マルチパイプレータを提供することを目的とする
。However, the capacitors C, , C2 are C-M06FE
It is a parameter determined by the structure of T itself, and the power supply voltage V
It is necessary to set o to a value greater than or equal to the value of VthP tv thN, and this Vo is also ultimately determined from the characteristics of the C-MOSFET itself. Therefore, in principle, in the conventional multipipulator circuit as shown in FIG.
It is difficult to reduce power consumption below the power determined by the product of the current given by Equation 1 and the power supply voltage Vo. The present invention has been made in view of the drawbacks of the above-mentioned conventional examples, and the present applicant has already published the "C-MOS circuit" published by Tokiso Sho 52-2233.
It is an object of the present invention to provide a low power consumption multi-pipelator which aims to reduce the power consumption of the multi-pipelator based on the concept of applying individual biases to the gates disclosed in .
以下本発明の一実施例を添附された図面の第3図及び第
4図と共に説明する。An embodiment of the present invention will be described below with reference to FIGS. 3 and 4 of the accompanying drawings.
なお第1図、第2図と同一符号は同一又は相当部分を示
し、その説明は省略する。第3図は本発明に係るマルチ
パイプレータの一回路例の原理図であって、G3,G4
,G5,G6は夫々P−MOSFETTP,,N−MO
SFETTN,.P−MOSFETTP2,N−MOS
FET TN2のゲートであり、D3,D4,D5,D
6は夫々G3,G4,G5,G6に対応したドレイン電
極である。Note that the same reference numerals as in FIGS. 1 and 2 indicate the same or corresponding parts, and the explanation thereof will be omitted. FIG. 3 is a principle diagram of an example of a circuit of a multipipulator according to the present invention, in which G3, G4
, G5, G6 are P-MOSFETTP, ,N-MO respectively.
SFETTN,. P-MOSFETTP2, N-MOS
This is the gate of FET TN2, and D3, D4, D5, D
Reference numeral 6 indicates drain electrodes corresponding to G3, G4, G5, and G6, respectively.
又C3,C4,C5,C6は各MOSFETがアースに
対してもっている静電容量を示したもので、外部から接
続したものではない。Tzは各対のMOSFETのドレ
ィン電極■3とD4及びD5とD6間に接続されたツェ
ナーダイオードもしくは普通ダイオードであり、Cは各
MOSFETのゲートとトリガ入力端1,及び12との
間に接続されたカップリングコンデソサであり、Rは一
方の対のMOSFETと他方の対のMOSFETのゲー
ト及びドレィン電極間に介挿された所要の抵抗である。
この第3図に示される回路に直流電圧VD/2を印加す
る。Further, C3, C4, C5, and C6 indicate the capacitance that each MOSFET has with respect to the ground, and are not connected externally. Tz is a Zener diode or an ordinary diode connected between the drain electrodes 3 and D4 and D5 and D6 of each pair of MOSFETs, and C is connected between the gate of each MOSFET and trigger input terminals 1 and 12. R is the required resistance inserted between the gate and drain electrodes of one pair of MOSFETs and the other pair of MOSFETs.
A DC voltage VD/2 is applied to the circuit shown in FIG.
このV。/2と各回路構成素子の特性は第4図に示され
るように設定しておく。即ちVthP,VthNをP形
、N形MOSFETの関値電圧とした時、このV。/2
をこれら2つの関値電圧の夫々よりわずかに大きく設定
し、ッェナーダィオードもしくは普通のダイオードTz
の関値電圧V2をVthP,VthNの夫々よりわずか
に小さく選んでおく。このように予じめ電源電圧と回路
素子の特性を決めておいて、第3図に示される回路にV
D/2の電圧を印加する。This V. /2 and the characteristics of each circuit component are set as shown in FIG. That is, when VthP and VthN are the function voltages of P-type and N-type MOSFETs, this V. /2
are set slightly larger than each of these two function voltages, and a Zener diode or an ordinary diode Tz
The function voltage V2 is selected to be slightly smaller than each of VthP and VthN. By determining the power supply voltage and the characteristics of the circuit elements in advance in this way, the voltage applied to the circuit shown in FIG.
Apply a voltage of D/2.
今この電源電圧の印加によってP一MOSFET TP
,がON‘こなっているとすれば、ドレィン電極D3の
電圧Vo3は略Vo/2となり、このドレィン電極D3
に接続されているN−MOSFET TN2のゲート○
6の電圧VG6も略VD/2になる。従ってN一MOS
FETTN2はONになり、TN2がONであるためド
レイン電極D6の電圧は略零しベルである。このドレイ
ン電極D6に接続されているゲートG3の電圧は略零し
ベルとなるので、P−MOS FET Tp,がON,
N−MOSFETTN,がOFFの状態を保持する。一
方ドレィン電極D4の電圧はドレィン電極D3の電圧よ
りもVzだけ低いので略(V。Now, by applying this power supply voltage, P-MOSFET TP
, is ON', the voltage Vo3 of the drain electrode D3 becomes approximately Vo/2, and the voltage Vo3 of the drain electrode D3 becomes approximately Vo/2.
Gate of N-MOSFET TN2 connected to ○
6 voltage VG6 is also approximately VD/2. Therefore, N-MOS
FET TN2 is turned on, and since TN2 is turned on, the voltage of the drain electrode D6 is approximately zero, and is at a level of 1. Since the voltage of the gate G3 connected to this drain electrode D6 becomes approximately zero and becomes a bell, the P-MOS FET Tp is turned ON.
N-MOSFETTN, maintains the OFF state. On the other hand, the voltage of the drain electrode D4 is lower than the voltage of the drain electrode D3 by Vz, so approximately (V).
/2−Vz)となり、このドレィン電極D4に接続され
ているゲートG5の電圧も略(Vo/2一Vz)となり
、第4図から理解されるように、この電圧ではP−MO
S FET TP2はOFFとなっている。又ドレィン
電極■5の電圧はドレィン電極D6の電圧よりVz以上
に高くなることはできないので略V2となるはずであり
、このドレィン電極D5に接続されているゲートG4の
電圧も略Vzとなり、第4図から理解されるように、こ
の電圧ではN−MOSFET TN,はOFFとなって
いる。従ってP−MOSFETTP,がONになってい
れば必然的にN一M〇SFET TN2は〇N,N−M
〇SFET TN,とP−MOSFETTP2はOFF
になって安定状態となっている。この状態をA2の状態
と呼ぶことにし、これとは逆にP−MOSFET TP
2と、N‐MOSFET TN,がONで、P−MOS
FET Tp,とN−MOSFETTN2がOFFの状
態も前述の説明と全く同機な理由で安定状態であり、こ
の状態を&の状態とする。A2の状態で安定している回
路に何等かの方法でトリガを加え、Zの安定状態に変化
させる場合を考える。/2-Vz), and the voltage of the gate G5 connected to this drain electrode D4 also becomes approximately (Vo/2-Vz). As understood from FIG. 4, at this voltage, the P-MO
S FET TP2 is OFF. In addition, the voltage of the drain electrode 5 cannot be higher than the voltage of the drain electrode D6 by more than Vz, so it should be approximately V2, and the voltage of the gate G4 connected to this drain electrode D5 will also be approximately Vz, and the voltage of the drain electrode D6 will be approximately Vz. As can be understood from Figure 4, the N-MOSFET TN is OFF at this voltage. Therefore, if P-MOSFETTP, is ON, inevitably N-M〇SFET TN2 is 〇N, N-M
〇SFET TN, and P-MOSFET TP2 are OFF
It is now in a stable state. This state will be referred to as the A2 state, and conversely, the P-MOSFET TP
2 and N-MOSFET TN, are ON, P-MOS
The state in which FET Tp and N-MOSFET TN2 are OFF is also a stable state for the same reason as explained above, and this state is referred to as the state &. Consider the case where a trigger is applied to a circuit that is stable in state A2 by some method to change it to stable state Z.
んの状態ではコンデンサC3の端子間電圧は略V。/2
で、コンデンサC4の端子間電圧は略(Vo/2.Vz
)で、コンデンサC5は略Vzで充電されコンデンサC
6の端子間電圧は略零しベルである。このA2の状態を
外部からのトリガにより&の状態に反転させれば、各コ
ンデンサC3,C4,C5,C6の端子間電圧は夫々略
V2、略奪レベル、略Vo/2、略(Vo/2−Vz)
に変化する。このんの状態からB2の状態に移行する際
に電源から回路に流入する電荷は、コンデンサC5とC
6を充電する電荷q=(Vo/2−V2)・(C5十C
6)であって、この電荷がP−MOSFET TP2を
通って充電される。In this state, the voltage between the terminals of capacitor C3 is approximately V. /2
So, the voltage between the terminals of capacitor C4 is approximately (Vo/2.Vz
), capacitor C5 is charged at approximately Vz and capacitor C
The voltage between the terminals of 6 is approximately zero bell. If the state of A2 is reversed to the state of & by an external trigger, the voltage between the terminals of each capacitor C3, C4, C5, and C6 will be approximately V2, the predation level, approximately Vo/2, approximately (Vo/2 -Vz)
Changes to The electric charge that flows into the circuit from the power supply when transitioning from the state of this to the state of B2 is the capacitor C5 and the capacitor C5.
Charge to charge 6 = (Vo/2-V2)・(C50C
6), and this charge is charged through P-MOSFET TP2.
又コンデンサC3とC4の電荷q=(V。/2−V2)
・(C3十C4)がN−MOSFETTN,を通ってア
ースに放電される。従ってトリガが1秒間にf回加わっ
てA2の状態とB2の状態を交互に繰返すならば、電源
から回路に流れ込む電流12は、12=(V。Also, the charge q of capacitors C3 and C4 = (V./2-V2)
- (C30C4) is discharged to ground through N-MOSFETTN. Therefore, if the trigger is applied f times per second and the states A2 and B2 are alternately repeated, the current 12 flowing into the circuit from the power supply is 12=(V).
/2−V2)・(C3十C4十C5十C6)xf/2
・・・‘21
となる。ここで(C3十C4十C5十C6)は上述の‘
1)式で示される(C,十C2)と同程度の値と見なし
得る。 .上述のよう
に、本発明の一実施例によれば、各C−MOSFETに
個別にバイアスを与える立場をとることから、電源電圧
を従釆の約半分にすることができる。/2-V2)・(C30C40C50C6)xf/2
...'21
becomes. Here, (C30C40C50C6) is the above '
1) It can be regarded as a value comparable to (C, 10C2) shown in formula. .. As described above, according to one embodiment of the present invention, since each C-MOSFET is individually biased, the power supply voltage can be reduced to about half that of the slave.
又、Vzは回路が安定に動作する限りにおいてできるだ
け大きく選択すればよいので(Vo/2一Vz)の値は
非常に小さく設定できる。即ち電源から回路内に流入す
る電流1,と12の比をとれば,./.2≠VD等;V
2=三 ‐‐‐‘31となる。Further, since Vz should be selected as large as possible as long as the circuit operates stably, the value of (Vo/2-Vz) can be set very small. That is, if we take the ratio of the currents 1 and 12 flowing into the circuit from the power supply, we get . /. 2≠VD, etc.; V
2 = 3 ---'31.
従って本発明に係るマルチパイプレータで消費される電
力P2は、P2=12xV。Therefore, the power P2 consumed by the multipipulator according to the present invention is P2=12xV.
/2=(V。/2一V2)・(C3十C4十C5十C6
)f/2×会となるので・第1図こ示される従来例に比
較して1/幼にすることが可能ある。なお上記実施例で
はC−MOSFETを用いた双安定マルチパイプレータ
回路を用いて説明したが、単安定もしくは無安定のマル
チパイプレータ回路でも全く同様である。以上述べてき
たように本発明に係るマルチ/ゞィプレー夕によれば、
FETやトランジスタあるいはダイオードのように、電
流を流すためにある最低電圧別ち闇値電圧を有する回路
をON,OFFさせるためには、この閥値電圧よりやや
高い電圧とやや低い電圧の間を変化させればよいことに
着目し、これを実現するためにゲート電圧を分離するこ
とにより上記変化中を動作可能範囲にまで小さくするこ
とにより、FETの電極がもっている静電容量を通じて
電圧変化による放電電流を小さくして、回路の消費電力
を従来に比して大幅に低減できる。/2=(V./2-V2)・(C30C40C50C6
) Since it is f/2×, it is possible to make it 1/smaller than the conventional example shown in FIG. Although the above embodiment has been described using a bistable multipipelator circuit using C-MOSFET, the same applies to a monostable or astable multipipelator circuit. As described above, according to the multi/player according to the present invention,
In order to turn on and off a circuit that has a threshold voltage, such as a FET, transistor, or diode, which has a minimum voltage for current to flow, it is necessary to change the voltage between a voltage slightly higher and a voltage slightly lower than this threshold voltage. In order to realize this, we separated the gate voltage to reduce the above change to an operable range, thereby reducing the discharge due to voltage changes through the capacitance of the FET electrode. By reducing the current, the power consumption of the circuit can be significantly reduced compared to conventional circuits.
【図面の簡単な説明】
第1図は従来のC−MOSICマルチ/ゞィブレ−夕の
原理を示す回路図であり、第2図は第1図に示される回
路の特性図であり、第3図は本発明に係る低消費電力マ
ルチパイプレータの回路図であり、第4図は第3図に示
される回路の特性図である。
TP,,TF2……P−MOS FET、TN,,TN
2……N−MOS FET、G3,04,G5,G6・
・・・・・ゲート、D3,D4,D5,D6……ドレィ
ン電極、C3,C4,ち,C6……分布静電容量、Vt
hP……P−MOSFETの閥値、V比N……N−MO
SFETの閥値、Vz……整流素子の閥値、Vz・・・
・・・電源電圧。
第1図
第2図
第3図
第4図[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a circuit diagram showing the principle of a conventional C-MOSC multi/disable brake; FIG. 2 is a characteristic diagram of the circuit shown in FIG. 1; The figure is a circuit diagram of a low power consumption multipipulator according to the present invention, and FIG. 4 is a characteristic diagram of the circuit shown in FIG. 3. TP,, TF2...P-MOS FET, TN,, TN
2...N-MOS FET, G3, 04, G5, G6・
...Gate, D3, D4, D5, D6...Drain electrode, C3, C4, C6...Distributed capacitance, Vt
hP...P-MOSFET threshold, V ratio N...N-MO
SFET threshold value, Vz... Rectifier element threshold value, Vz...
···Power-supply voltage. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
ETを相補的に接続した2対のC−MOSFETを所定
の電源に接続したマルチバイブレータにおいて、前記一
方の対のP−MOSFETのゲート及びドレイン電極を
他方の対のN−MOSFETのドレイン電極及びゲート
に夫々接続すると共に、前記一方の対のN−MOSFE
Tのゲート及びドレイン電極を他方の対のP−MOSF
ETのドレイン電極及びゲートに接続し、前記各対のP
−MOSFETとN−MOSFETの各ドレイン電極間
にNチヤンネル側からPチヤンネル側に順方向に整流素
子を介挿し、前記電源の値を前記各対のP−MOSFE
T及びN−MOSFETの閾値より大きく設定すると共
に前記整流素子の閾値を各対のP−MOSFET及びN
−MOSFETの閾値より小さく設定してなる低消費電
力マルチバイブレータ。 2 PチヤンネルMOSFETとNチヤンネルMOSF
ETを相補的に接続した2対のC−MOSFETを所定
の電源に接続したマルチバイブレータにおいて、前記一
方の対のP−MOSFETのゲート及びドレイン電極を
所定の抵抗を介して他方の対のN−MOSFETのドレ
イン電極及びゲートに夫々接続すると共に、前記一方の
対のN−MOSFETのゲート及びドレイン電極を所定
の抵抗を介して他方の対のP−MOSFETのドレイン
電極及びゲートに接続し、各対のC−MOSFETのト
リガ入力端と各P−MOSFET及びN−MOSFET
のゲート間にカツプリンブコンデンサを介挿し、前記各
対のP−MOSFETとN−MOSFETの各ドレイン
電極間にNチヤンネル側からPチヤンネル側に順方向に
整流素子を介挿し、前記電源の値を前記各対のP−MO
SFET及びN−MOSFETの閾値より大きく設定す
ると共に前記整流素子の閾値を各対のP−MOSFET
及びN−MOSFETの閾値より小さく設定してなる低
消費電力マルチバイブレータ。[Claims] 1 P-channel MOSFET and N-channel MOSF
In a multivibrator in which two pairs of C-MOSFETs with ETs connected complementary to each other are connected to a predetermined power source, the gate and drain electrodes of one pair of P-MOSFETs are connected to the drain electrodes and gate of the other pair of N-MOSFETs. and one pair of N-MOSFEs.
The gate and drain electrodes of T are connected to the other pair of P-MOSFs.
connected to the drain electrode and gate of the ET, and connected to the P of each pair.
- A rectifying element is inserted between each drain electrode of the MOSFET and the N-MOSFET in the forward direction from the N channel side to the P channel side, and the value of the power source is set between the drain electrodes of each pair of P-MOSFETs.
The threshold value of the rectifying element is set to be larger than the threshold value of each pair of P-MOSFET and N-MOSFET.
- A low power consumption multivibrator that is set smaller than the MOSFET threshold. 2 P-channel MOSFET and N-channel MOSFET
In a multivibrator in which two pairs of C-MOSFETs with ETs connected complementary to each other are connected to a predetermined power source, the gate and drain electrodes of one pair of P-MOSFETs are connected to the N- of the other pair through a predetermined resistance. The drain electrode and gate of the MOSFET are connected to each other, and the gate and drain electrode of the one pair of N-MOSFET is connected to the drain electrode and gate of the other pair of P-MOSFET through a predetermined resistance. Trigger input terminal of C-MOSFET and each P-MOSFET and N-MOSFET
A cut-off capacitor is inserted between the gates of the P-MOSFET and the N-MOSFET, and a rectifying element is inserted between the drain electrodes of each pair of P-MOSFET and N-MOSFET in the forward direction from the N channel side to the P channel side, and the value of the power supply is for each pair of P-MO
The threshold value of the rectifying element is set to be larger than the threshold value of the SFET and the N-MOSFET, and the threshold value of the rectifying element is set larger than the threshold value of the P-MOSFET of each pair.
and a low power consumption multivibrator configured to be set smaller than the threshold value of the N-MOSFET.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52072500A JPS6019684B2 (en) | 1977-06-18 | 1977-06-18 | Low power consumption multivibrator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52072500A JPS6019684B2 (en) | 1977-06-18 | 1977-06-18 | Low power consumption multivibrator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS546754A JPS546754A (en) | 1979-01-19 |
JPS6019684B2 true JPS6019684B2 (en) | 1985-05-17 |
Family
ID=13491108
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52072500A Expired JPS6019684B2 (en) | 1977-06-18 | 1977-06-18 | Low power consumption multivibrator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6019684B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61140080U (en) * | 1985-02-22 | 1986-08-30 | ||
JPS6242689U (en) * | 1985-09-04 | 1987-03-14 | ||
JPS6311783A (en) * | 1986-03-24 | 1988-01-19 | 山崎 慶市郎 | Outdoor space forming device |
JPH0423192Y2 (en) * | 1985-03-08 | 1992-05-28 |
-
1977
- 1977-06-18 JP JP52072500A patent/JPS6019684B2/en not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61140080U (en) * | 1985-02-22 | 1986-08-30 | ||
JPH0423192Y2 (en) * | 1985-03-08 | 1992-05-28 | ||
JPS6242689U (en) * | 1985-09-04 | 1987-03-14 | ||
JPS6311783A (en) * | 1986-03-24 | 1988-01-19 | 山崎 慶市郎 | Outdoor space forming device |
Also Published As
Publication number | Publication date |
---|---|
JPS546754A (en) | 1979-01-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5136181A (en) | Power-on-reset circuit | |
US5245524A (en) | DC-DC converter of charge pump type | |
JPS6244597Y2 (en) | ||
KR20020019390A (en) | Semiconductor integrated circuit device | |
JPH031609A (en) | Ring oscillator having frequency unrelated to supply voltage | |
US4467227A (en) | Channel charge compensation switch with first order process independence | |
US8970313B2 (en) | Area efficient single capacitor CMOS relaxation oscillator | |
JPS6019684B2 (en) | Low power consumption multivibrator | |
CN210431350U (en) | Novel temperature compensation oscillator | |
US20070188250A1 (en) | Ultra low power cmos oscillator for low frequency clock generation | |
US4283690A (en) | Low power CMOS oscillator | |
JPH06216733A (en) | Driver circuit of electronic switch | |
JPH11163647A (en) | Switched capacitor circuit | |
JPH0428226Y2 (en) | ||
US6909335B2 (en) | Oscillator for DC—DC converter | |
JPH0267817A (en) | Cmos analog switch | |
US5793260A (en) | Current controlled oscillator with voltage independent capacitance | |
JPS63260316A (en) | Oscillation circuit | |
JP2995396B2 (en) | CR oscillation circuit | |
JPH09326687A (en) | Semiconductor integrated circuit | |
JP3047828B2 (en) | Comparator circuit | |
JP2566931B2 (en) | Level comparator | |
JP2005175540A (en) | Inverter circuit and piezoelectric oscillator using the same | |
JPS6239447B2 (en) | ||
JP2004295705A (en) | Constant voltage power supply circuit and electronic clock using it |