JPS60196825A - Reactive power compensating device - Google Patents

Abstract

PURPOSE:To compensate varied loads while suppressing the deflected magnetism of a high impedance voltage transformer by making compensating current flow in accordance with the varied load and comparing current on the primary side of the high impedance voltage transformer in a compensating circuit for suppressing the variation of a bus voltage with that on the secondary side to detect deflected magnetism current. CONSTITUTION:A CT11 is coupled with respective phase windings on the primary side of the high impedance transformer 4 and a CT14 for detecting secondary side current is coupled with a serial circuit consisting of the high impedance voltage transformer 4 and a thyristor switch 5. The outputs of both the CTs 11, 14 are inputted to a compensating circuit 12, a synchronizing signal from a PT6 is simultaneously inputted also to the compensating circuit 12, the output of the circuit 12 and the output of a Q detector 9 are inputted to an adder 13, and the output of the adder 13 is inputted to a pulse generator 10. Namely, a feedback loop is constituted of the compensating circuit 12, the adder 13, the pulse generator 10, the thyristor switch 5, and the CT11 coupled with the high impedance voltage transformer 4 and the primary side of the voltage transformer 4 is prevented from unbalanced state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention provides a high-impedance compensator for a variable load in a reactive power compensator comprising a high-impedance transformer and an antiparallel-connected si-risk switch that controls energization of the high-impedance transformer. Involved in preventing unbalanced magnetism in transformers.

[Conventional technology and problem 1 As a reactive power compensator, a high impedance transformer connected in series with an anti-parallel connected thyristor switch can control its secondary current at high speed by controlling the phase of the thyristor switch. , a magnetic bias phenomenon sometimes occurs.

First, a conventional reactive power compensator of this type and the magnetic bias phenomenon that occurs will be explained with reference to FIG. 1 and others.

In FIG. 1(A), l indicates an infinite bus, 2 indicates a power supply impedance, and 8 indicates a bus. A variable load 8 with delayed current, such as an arc furnace, is connected to this bus bar 8.
In order to suppress the voltage fluctuation of the bus bar 8 due to this, a high impedance transformer 4 and an anti-parallel connected thyristor switch 5 are connected in series to the bus bar 8 to form a compensation circuit, and the phase control of the thyristor switch 5 controls the bus bar voltage. Reduce fluctuations.

6 is a PT for detecting bus voltage, 7 is an OCT for detecting fluctuating load current, and the generated power is input to a Q (reactive power) detector 9 to calculate a reactive power value. The pulse generator IO generates a pulse of a predetermined phase based on the output signal of the Q detector 9, and inputs it to the firing pole of the thyrisk switch 5 to control the energization of the high impedance transformer 40.

Note that the figure shows one phase.

The high impedance transformer 4 generally has a conductive reactance inside it, but in this specification, as shown in FIG.
1. Those using a series circuit of the reactor 42a are also included in the scope of the high impedance transformer 4.

The Q detector 9 detects the reactive power consumption of the load 8 at high speed, and detects the reactive power consumption of the load 8 via the pulse generator IO.
As already mentioned, the operation is explained using the single-phase circuit shown in FIG. 2 to simplify the explanation. In order to correspond to FIG. 1, a dash is added to each instruction. Further, FIG. 3(A) shows the voltage and current waveforms at no load, and FIG. 3(B) shows the voltage and current waveforms at unbalance.

When the variable load is no load (IL=0), the transformer current 1□
1 is passing currents of equal positive and negative polarity as shown in FIG. 3(A).

Next, when the fluctuating load consumes a positive/negative unbalanced current l as shown in Figure 3 (b), the transformer current 'TI corresponds to the unbalanced current flowing, and the power supply side current Is
will be kept constant. Note that the shaded area in the figure (b) indicates the biased magnetic current.

However, such an unbalanced state of the transformer current 'TI occurs in the transformer 4! of FIG. A' is biased, and as shown in FIG. Unbalanced positive and negative currents flow on both sides, causing biased magnetism, which is not desirable for the transformer 418'.

[Disclosure of the Invention] If the magnetic bias described above becomes extreme, the overcurrent on the next side of the transformer may cause damage in the worst case. A compensating circuit that suppresses voltage fluctuations detects a biased current by comparing the currents on the primary and secondary sides of a high-impedance transformer, performs feedback control to cancel it, and eliminates the bias of the high-impedance transformer. The present invention provides a reactive power compensator capable of compensating for fluctuating loads while suppressing magnetic fields.

The embodiment of the present invention shown in FIG. 4, the partial circuits 0), (B), and (C) of FIG. 4 shown in FIG. 5, and FIGS. Figure 7 (a) to (e)
The present invention will be explained below.

In FIG. 4, the same parts as in FIG. 1 are indicated by the same symbols. The difference from Fig. 1 is that each phase winding [CTII] on the primary side of the high-impedance transformer 4 is coupled, and the secondary current is detected in the series circuit of the high-impedance transformer 4 and the thyrisk switch 5. The outputs of the CT11 and CT14 are input to the correction circuit 12, the synchronization signal from the simultaneous vcPT6 is also input to the correction circuit 12, and the output of the correction circuit 12 and the output of the Q detector 9 are connected to an adder. 13, and the output of this adder 13 is input to the pulse generator 10. That is, the correction circuit 12, the adder 18, the pulse generator 10, the thyrisk switch 5,
A feedback loop is formed by the CTII coupled to the high impedance transformer 4, which suppresses the primary side of the transformer 4 from becoming unbalanced.

Correction circuit 12I′i 121 as shown in FIG. 5 (/f)
~126.

The outputs j'T+ and 1'T2 of CT]1 and 14 are converted into voltages by the shunt resistor 15, and are input to the sample holder 121K. The outputs of both sample holders +21 are input to an adder 125 in positive and negative form, and the output vIT is input to an adjuster 122. The regulator 122 is: However, K1 is a gain T1: Time constant S: j(A) Output of the regulator 122 ■. Input the polarity switch +23VC.

On the other hand, the voltage V from PT6 is input to the comparator 124, and the polarity switch 123 of the comparator 124 is switched every half cycle. Movable switching contact 1 of polarity switch 123
7 is connected to an adder 13 and outputs QE, and the adder 13 is also connected to a Q detector 9 and sends an output corrected by Q6 to a pulse generator 10.

Furthermore, the voltage from PI3 is applied to the timing noise generator +
Quimming noggles P input into 26 and emitted from this
is input to sample holder +21. The structure of the sample holder +21 is shown in FIG. 5(c).

When normal OCT is used as the CTI+ and +4, DC components cannot be transmitted. To explain this with reference to Fig. 7, if an unbalanced current flows as shown in Fig. 5 (a) on the primary side (i72) of the OCTI4 as shown in Fig. The DC component is cut, and the secondary current i'T2 of CTl4 becomes as shown in FIG. Therefore, the timing noise generator +26
Therefore, at the peak point of the line voltage Y shown in Figure 7 (a),
) At the timing shown in the figure, the detected secondary current i'T2 is sampled and the 17 that should have been cut is
2. Sample and hold the DC component (IDc) every half cycle. By correcting 1'T2 using the IDC detected in this way, the j T2 signal now required can be detected. (E) The figure shows the output from the sample hold 121.

(The primary side jT1 signal can be detected on the Tll side as well.

Next, the difference output vIT from the adder +25 is inputted to the regulator 122, which has a certain gain, a time constant of 11, and V
The AC component in IT is sufficiently attenuated and detected as DC, resulting in vo.

The polarity of vo is switched every half cycle by the polarity switch 123 to become Q, and the output of the Q detector 9 is corrected.

The portion consisting of the polarity switch +23 and the comparator 124 may be replaced with a circuit as shown in FIG. 5(b). This is because Qt is equivalent to amplitude modulating a rectangular carrier wave by vo, so a rectangular wave converter (comparator) 124' outputs a rectangular wave with a constant amplitude and in phase with the signal V as a carrier wave, Signal X is input to the next multiplier 123'. Next is V. is input as signal Y. Then, the output of the multiplier 23' is output in the form of X×Y, and the same signal Qε as that of the polarity switch 123 is obtained.

Next, the overall operation will be explained with reference to FIG.

First, (A) As shown in the figure, when the secondary current signal j 72 is small at each half-wave and becomes too thick at every next half-wave, that is, when there is an imbalance. , DC will be included in the signal, but the signal value will be detected by the sample holder 121 depending on the timing of every half wave due to the power supply frequency, and similarly, as shown in (b) figure, - next-side current The signal t T1 can also capture this, and (c) the difference signal VI from the adder +25 shown in the figure
T removes the alternating current component with regulator +22 and converts it into direct current) V as shown in the figure. is obtained as a value that gradually fluctuates with the gain in the DC component of VIT and the time constant T1.

Next, by using the polarity switch +2fll, (e) V is set every half cycle as shown in the figure. The polarity of Q is reversed.

This Q6 means that when determining the firing angle of ■ and ■, the value is largely corrected, and the opposite is true for ■ and ■. By this, so that the DC component in VIT is always zero,
Feedback controlled. Q.

This only acts to cancel the unbalanced command signal contained in the Q detector 9, and does not adversely affect the flicker compensation effect.

In the apparatus shown in FIG. 5, before inputting the VIT to the regulator 122, it may be passed through a filter circuit that removes the alternating current component, and the regulator 122 does not need to be a first-order delay system.

〔effect〕

As explained above, according to the present invention, the biased magnetic phenomenon occurring in a high impedance transformer used as a compensator can be suppressed by detecting the biased current signal and disabling it from a normal fluctuating load. By simply adding this signal to the power signal, the addition of this biased current signal often defeats the original purpose of reactive power compensation, that is, to prevent flicker. Unbalanced magnetism can be suppressed, unnecessary power loss in the compensation device can be prevented, and stable operation can be performed.

[Brief explanation of the drawing]

FIG. 1(a) shows a schematic circuit of a reactive power compensator for a transformer load using a high impedance transformer and a thyrisk switch. In addition, (b) shows an impedance device consisting of a transformer driver and an handle having the same effect as a high impedance transformer. Figure 2 shows Figure 1←) as a single-phase circuit. FIGS. 3A and 3B are explanatory diagrams of waveforms in the circuit of FIG. 2. FIG. 4 shows an embodiment of the invention. Figure 5 (a) is a detailed block diagram of the correction circuit in Figure 4, in which (b) Jd is a Q and detector used in place of the polarity switch in (a), and (c) is a The sample holder 12+ of (A) is shown. Figure 6 (a), (b), (c), ni), (e) are the fifth
FIG. 6 is an explanatory diagram of waveforms during the operation of each part in the block diagram of FIG. 7(a), (b), (u, ni), and (e) are explanatory diagrams of waveforms during the operation of each part in the embodiment of FIG. 4. 1... Infinite bus bar, 2... Power supply impedance, 3
...Bus bar, 4...High impedance transformer, 5...
・Thyristor switch, 6...PT, 7...CT,
8...Variable load, 9...Q detector, 10...Pulse generator, I+, +4...CT, +8...Adder, 15...Soyanto resistor, 16...Ana Long switch, 17... switching contact. Wi diagram (a) Piece 2 diagram W3 diagram (a) Prayer 4 diagram R5 diagram C mouth) (c) Yoshi 6th

Claims (1)

[Claims] (1) In a reactive power compensator comprising a high-impedance transformer and a thyrisk switch connected in antiparallel that controls energization of the high-impedance transformer for a fluctuating load, the energization control of the thyrisk switch is performed for the fluctuating load. Sample and hold the secondary current signal and the secondary current signal of the high impedance transformer in the reactive power signal obtained by using a timing pulse, and compare the two current signals to obtain a biased current signal detected. A reactive power compensator further comprising the step of suppressing biased magnetization of the high impedance transformer.