JPS60195988A - Method of forming through hole circuit - Google Patents

Method of forming through hole circuit

Info

Publication number
JPS60195988A
JPS60195988A JP5103984A JP5103984A JPS60195988A JP S60195988 A JPS60195988 A JP S60195988A JP 5103984 A JP5103984 A JP 5103984A JP 5103984 A JP5103984 A JP 5103984A JP S60195988 A JPS60195988 A JP S60195988A
Authority
JP
Japan
Prior art keywords
plating
thin
manufactured
film thickness
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5103984A
Other languages
Japanese (ja)
Inventor
真弓 喜行
亮平 小山
馨 大村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Kasei Corp
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
Asahi Kasei Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd, Asahi Kasei Kogyo KK filed Critical Asahi Chemical Industry Co Ltd
Priority to JP5103984A priority Critical patent/JPS60195988A/en
Publication of JPS60195988A publication Critical patent/JPS60195988A/en
Expired - Lifetime legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発“明は高信頼性めスルーホール回路な゛製造する改
良された方法に関す”るものである。 従来、厚膜導電
体の製造法では、金属薄板上にレジストを回路部以外の
所に設け、電解メッキして回路部に導電体を形成し、次
いで得られた導電体を絶縁層に金属薄板を外側にして貼
り付けた後、スルーホール用穴あけを行ない、それから
金属薄板をエツチング除去し、再び導電体上に電解メッ
キ′を行なって、電解メッキのみでスルーホールを形成
していた。しかしながら、電解メッキだけでは絶縁層の
厚みに左右され、絶縁層が厚い場合、スルーホールの内
壁部に若干のくぼみが生じるという欠点があった。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved method of manufacturing high reliability through-hole circuits. Conventionally, in the manufacturing method of thick film conductors, a resist is provided on a thin metal plate in areas other than the circuit area, electrolytic plating is performed to form a conductor in the circuit area, and then the obtained conductor is applied to the thin metal plate as an insulating layer. After pasting the conductor on the outside, a hole for the through hole was made, the thin metal plate was etched away, and electrolytic plating was performed again on the conductor to form the through hole using only electrolytic plating. However, electrolytic plating alone is dependent on the thickness of the insulating layer, and when the insulating layer is thick, there is a drawback that some depressions occur on the inner wall of the through hole.

本発明は、無電解メッキを行ない、導電体をスルーホー
ル内壁部に形成した後、電解メッキを行なうことにより
上記問題点を解決したものである。
The present invention solves the above problems by performing electroless plating to form a conductor on the inner wall of the through hole, and then performing electrolytic plating.

即ち、金gill板上に電解メッキにより導電体を設け
たものを絶縁層の両面に金属薄板を外側にして貼り合わ
せた後に、スルーホール用の穴あけを行ない、次いで無
電解メッキのための活性化液による前処理を行ない、そ
の後、無電解メッキ→金属薄板除去→電解メッキするか
、或いは、金属薄板除去→無電解メッキ→電解メッキに
よりスルーホール接続を行なう事を特徴とする、信頼性
の高いスルーホールを均一に形成し得る方法を提供する
ものである。
That is, after a gold plate with a conductor provided by electrolytic plating is bonded to both sides of an insulating layer with the metal thin plate facing outward, holes for through holes are drilled, and then activated for electroless plating. Highly reliable, characterized by pre-treatment with a liquid, followed by electroless plating → thin metal plate removal → electrolytic plating, or thin metal plate removal → electroless plating → electrolytic plating to make through-hole connections. The present invention provides a method for uniformly forming through holes.

本発明に使用される金属薄板としては、導電体でありか
つエツチングが可能なものであれば良いが、好ましくは
電解メッキ導電体と異なるエツチング特性を持つものが
良く、この場合は金属薄板をエツチング除去する際に電
解メッキ導電体はエツチングされず、高精度の金属薄板
エツチングが可能となる。これに適したものとしては、
アルミニウム、スズ、亜鉛などがある。またJyX厚と
しては、7〜500μm特に5〜200μm更には70
〜700μmが好ましい範囲である。78m以下の膜厚
では、取り扱い難く、かつメッキ膜厚に分布が生じ易い
。また5θθμm以上の膜厚では、エツチング除去に時
間がかかり生産性が低下する。
The thin metal plate used in the present invention may be any material as long as it is a conductor and can be etched, but it is preferably one that has etching characteristics different from those of electroplated conductors; in this case, the thin metal plate can be etched. During removal, the electrolytically plated conductor is not etched, allowing highly accurate thin metal plate etching. Appropriate for this,
These include aluminum, tin, and zinc. In addition, the JyX thickness is 7 to 500 μm, particularly 5 to 200 μm, and even 70 μm.
A preferable range is 700 μm. If the film thickness is 78 m or less, it is difficult to handle and the plating film thickness tends to be uneven. Further, if the film thickness is 5θθμm or more, it takes time to remove the film by etching, and productivity decreases.

本発明において行われる回路部以外の部分にレジストを
形成する方法としては、スクリーン印刷或いはグラビア
印刷などで形成しても良いが、ファインパターンが得易
いフォトレジストを用い露光、現像プロセスを経て得る
事が出来る。フォトレジストとしては、イーストマンコ
ダック社のKPR,KOR,KPL%KTFR,東京応
化社のTPR,0MR81,富士薬品工業のFARなど
のネガ型、およびイーストマンコダック社のKADR,
VプV−社17)AZ−1350などのポジ型などがあ
るが、耐メッキ性に優れたものが好ましく、特にネガ型
が好ましく使用される。また、ドライフィルムレジスト
も使用可能である。膜厚は厚い方がメッキの太り防止と
して役立つが、余り厚過ぎるとファインパターンが得ら
れなくなってしまい、0.7〜504m1特に7〜70
4mが好ましい。0.14m以下ではピンホールが生じ
易い。
In the present invention, the resist may be formed on parts other than the circuit part by screen printing or gravure printing, but it is also possible to form the resist through an exposure and development process using a photoresist that can easily form a fine pattern. I can do it. As photoresists, negative types such as Eastman Kodak's KPR, KOR, KPL%KTFR, Tokyo Ohka Co.'s TPR, 0MR81, Fuji Pharmaceutical's FAR, and Eastman Kodak's KADR,
There are positive types such as AZ-1350 manufactured by V-Pub Co., Ltd. 17), but those with excellent plating resistance are preferred, and negative types are particularly preferably used. A dry film resist can also be used. The thicker the film, the more useful it will be in preventing the plating from thickening, but if it is too thick, it will be impossible to obtain a fine pattern.
4 m is preferred. If the distance is 0.14 m or less, pinholes are likely to occur.

電解メッキの種類としては、導電性及び経済性の点から
銅が好ましいが、銀、金、ニッケル等なんでも良い。メ
ッキ液の種類としては、銀メッキならばシアン化銀浴、
金メッキならば酸性、中性アルカリ性浴、ニラ”ケルメ
ッキならば硫酸ニッケル浴、スルフアミノ酸ニッケル浴
等が使用できる。
As for the type of electrolytic plating, copper is preferable from the viewpoint of conductivity and economy, but any metal such as silver, gold, or nickel may be used. The type of plating solution is silver cyanide bath for silver plating,
For gold plating, acidic or neutral alkaline baths can be used, and for chive-kel plating, nickel sulfate baths, sulfur amino acid nickel baths, etc. can be used.

銅の電解メッキとしては、シアン化銅メッキ、ビロリン
酸鋼メッキ、硫酸銅メッキ、ホウフッ化鋼メッキなどが
ある。電解メッキ条件は通常の条件で行なえば良いが、
厚み方向に選択的にメッキすし゛かし、金−薄板にアル
ミニ“ラム、□亜鉛、スズを使用し起場合、pHが高す
ぎたり截すぎたりした時にメッキ液中に金゛属の溶出が
息こる苑めに、17レキ液は中性領域のもの、pH4t
〜IO1特へ3〜りのものを使用した方が好ましい。銅
メ′ツ岑の場合には一ビロリン酸鋼メッキ11好ましい
Examples of copper electrolytic plating include cyanide copper plating, birophosphate steel plating, copper sulfate plating, and borofluoride steel plating. Electrolytic plating can be carried out under normal conditions, but
When selectively plating in the thickness direction or using aluminum, zinc, or tin on a thin gold plate, metal elution may occur in the plating solution when the pH is too high or the plating is too thin. Koruen Mei, 17 Reki liquid is in the neutral range, pH 4t
It is preferable to use one of ~IO1 and especially ~3~. In the case of copper metal plates, monopyrophosphate steel plating 11 is preferred.

電解メッキ工程は通常のやり方で良“いが、iに金属−
一“)゛ニアルミーレム、スズ、−鉛な鷹を用いるとき
は、初めにθ、θs −,2h/dvri、好ましくは
θ、7〜/、りA/dm”の電流密度で膜厚θ、3〜/
θμm好ましく1マθ、1−1μm、電解メッキを行う
The electrolytic plating process can be carried out in the usual way, but if the metal is
1) When using aluminum, tin, lead, the film thickness θ, 3 is initially applied at a current density of θ, θs −, 2 h/dvri, preferably θ, 7 to /, 2 A/dm. ~/
Electrolytic plating is performed at θ μm, preferably 1 μm, 1-1 μm.

電流密度=2A/drr?以上ではメツ゛□キ層の金属
−以下ではメッキ時間がかかりjぎ生産性カー低量する
。膜厚も0.3 ’Jim’以下では”璋は、り十分な
密着性が得られず、次に所定の膜厚までさらに前メッキ
工程より高い電流密度でメッキを行う。鶏の陰−電流密
度としては3 A/dm’以上、特にj′”A/dd以
上、更にはJ’ A/dm’以上が好ましく、陰極電流
密度な大きくすると幅方向への太りが抑制される。陰極
電流密度は高い程好ましく、パルスメッキなども好まし
く用いられる。陰極電流密度の上限はやけにより決定さ
れる。
Current density = 2A/drr? If the metal layer is more than that, the plating time will be longer and the productivity will be lower. If the film thickness is less than 0.3 'Jim', sufficient adhesion cannot be obtained, and plating is then carried out at a higher current density than in the pre-plating process until the desired film thickness is reached. The density is preferably 3 A/dm' or more, particularly j''' A/dd or more, and more preferably J'A/dm' or more, and increasing the cathode current density suppresses thickening in the width direction. The higher the cathode current density, the better, and pulse plating is also preferably used. The upper limit of cathode current density is determined by burnout.

本発明の方法は1、配線密度の低い所で使うことシ可能
であるが、壬業的には3本、4以上特に!本廊以害の配
線薫、度に対し好適である。
1. The method of the present invention can be used in places with low wiring density, but it is practical for use with 3, 4 or more wiring lines. Suitable for wiring in the main hall and beyond.

更に本発明は導電パターンの占積率がjOS以上特に7
θチ以上の場合好適である。
Furthermore, the present invention has a conductive pattern whose space factor is more than jOS, especially 7.
It is suitable when θ is greater than or equal to θ.

また絶縁層としては、ポリイミド、ポリアミドイミド、
ポリエステル、ポリパラバン酸、エポキシ(2)脂、フ
ェノール樹脂、アルキッド樹脂及びこれらの複合物など
からなる基板を用いて接着剤で貼り合わせても良く、基
板を用いずフェスを塗布して接着剤で貼り合わせても良
い。また接着剤を直接塗布してそのまま貼り合わせても
良い。膜厚は特に限定されないが、好ましくはj−20
θμm特に10〜/!θμmが好ましい。絶縁層の厚さ
が58m以下だと機械強度が不足し、また場合によって
は表裏導体パターン間の絶縁性が悪くなる。
In addition, as an insulating layer, polyimide, polyamideimide,
It is also possible to use a substrate made of polyester, polyparabanic acid, epoxy (2) resin, phenolic resin, alkyd resin, or a composite thereof and attach it with an adhesive, or it is possible to apply a face without using a substrate and attach it with an adhesive. You can also match them. Alternatively, the adhesive may be directly applied and bonded as is. The film thickness is not particularly limited, but preferably j-20
θμm especially 10~/! θμm is preferred. If the thickness of the insulating layer is less than 58 m, the mechanical strength will be insufficient, and in some cases, the insulation between the front and back conductor patterns will deteriorate.

絶縁層の厚さが200μm以上だと導体占積率が低下す
る。
When the thickness of the insulating layer is 200 μm or more, the conductor space factor decreases.

次にスルーホールの穴あけは、パリやカス等が発生せず
、穴の周囲の導体層が絶縁層から剥離しなければいかな
る方法によっても良く、例えばドリルやパンチ等を使え
ば良い。
Next, the through-holes may be formed by any method as long as no particles or debris are generated and the conductor layer around the holes does not peel off from the insulating layer, such as using a drill or punch.

無電解メッキのための活性化処理では、通常の無電解メ
ッキ用活性化剤が用いられるが、金属薄板がアルミニウ
ム、亜鉛、スズの場合は、通常の活性化剤は使用出来ず
、浴中に金属薄板が溶出し浴を著しく劣化させたり、あ
るいは金属薄板が全て溶出し回路部の導電体以外の部分
が活性化処理されない様に浴を中性領域、pH=4〜1
0、特はpH= j〜す、jに管理出来るものが使用さ
れる。
In the activation process for electroless plating, a normal activator for electroless plating is used, but when the metal sheet is aluminum, zinc, or tin, a normal activator cannot be used and The bath should be kept in a neutral region with a pH of 4 to 1 to prevent the metal thin plate from eluting and significantly deteriorating the bath, or from eluting all the metal thin plates and activating parts other than the conductor of the circuit.
0, especially those that can be controlled to pH = j to s, j are used.

これに使用出来るものとしては、パラジウムの有機錯体
があり、例えば活性化液としては、シェーリング社のア
クテベーター・ネオガント834、還元液としては、シ
エーリング社のりデューサー・ネオガン)WAをそれぞ
れ硫酸、はう酸でpH調節して使用することが出来る。
Things that can be used for this include palladium organic complexes.For example, the activating liquid is Schering's Activator Neogant 834, and the reducing liquid is Schering's Glueducer Neogant (WA), sulfuric acid, etc. It can be used after adjusting the pH with an acid.

また、活性化処理の前処理には、金属薄板上あるいはス
ルーホール内壁部の汚れをとるために表面活性化剤によ
る脱脂工程及び無電解メッキにより析出する金属の密着
性向上のための粗面上のために過硫酸アンモニウム水溶
液からなるソフトエツチング工程を設けた方が良い。
In addition, pre-treatment for activation treatment includes a degreasing process using a surface activator to remove dirt from the thin metal plate or the inner wall of the through hole, and a process on the rough surface to improve the adhesion of metal deposited by electroless plating. Therefore, it is better to provide a soft etching process consisting of an aqueous ammonium persulfate solution.

無電解メッキの種類としては、導電性と経済性の点から
銅が好ましいが、ニッケル、鏝、金環導電体ならば何で
も良い。金属薄板がアルミニウム、亜鉛、スズの場合、
金属薄板除去→無電解メッキのプロセスをとれば通常の
無電解メッキ液が使用出来るが、無電解メッキ→金風薄
板除去のプロセスの場合は中性領域、pH= Q〜IO
の無電解メッキ液を使用する必要がある。これらの例と
しては、ニッケルの場合日本カニゼン社製シューマー8
−680などがある。
As for the type of electroless plating, copper is preferable from the viewpoint of conductivity and economy, but any metal such as nickel, trowel, or ring conductor may be used. If the metal sheet is aluminum, zinc, or tin,
If the process of metal thin plate removal → electroless plating is used, a normal electroless plating solution can be used, but in the case of electroless plating → metal style thin plate removal process, the pH is in the neutral range, pH = Q ~ IO.
Electroless plating solution must be used. For example, in the case of nickel, Schumer 8 manufactured by Nippon Kanigen Co., Ltd.
-680 etc.

金属薄板をエツチング除去する方法としては、使用した
金fil#板を電解する溶液を用いて、スプレー或いは
浸漬などによりエツチングする方法が用いられる。金@
薄板としてアルミニウム、スズ、亜鉛を用いた場合は、
電解メッキ導電体をエツチングしない例えばアルカリ水
溶液でエツチングする事が好ましいが、希塩酸等の酸性
水溶液でエツチングする事も可能である。・ また、金属薄板エツチング除去後の導電体上の汚れを取
り除くために、後処理として希硝酸への漬浸を行なうこ
とが好ましい。
As a method for removing the metal thin plate by etching, a method is used in which the used gold fil# plate is etched by spraying or dipping using a solution that electrolyzes the plate. Money@
When aluminum, tin, or zinc is used as the thin plate,
Although it is preferable not to etch the electrolytically plated conductor, for example, to etch it with an alkaline aqueous solution, it is also possible to etch it with an acidic aqueous solution such as diluted hydrochloric acid. - Also, in order to remove dirt on the conductor after etching the thin metal plate, it is preferable to immerse it in dilute nitric acid as a post-treatment.

以下に本発明の態様を一層明確にするために、実施例を
あげて説明するが、本発明は以下の実施例に限定される
ものではなく、種々の変形が可能である。
EXAMPLES In order to further clarify aspects of the present invention, examples will be described below, but the present invention is not limited to the following examples, and various modifications can be made.

実施例/ 膜厚<10μmアルミニウム薄板上に、イーストマンコ
ダック社製ネガ型Vシスト「マイクロレジスト7471
10csIJを乾燥後、膜厚がjamになる棟に塗布、
プレベークして、回路パターンマスクを通して高圧水銀
ランプで露光し、専用の現像液およびリンス液を用いて
現像し、ポストベークして、回路部以外の部分にレジス
トを形成した。
Example/ On a thin aluminum plate with a film thickness of <10 μm, a negative type V-syst “Microresist 7471” manufactured by Eastman Kodak was applied.
After drying 10csIJ, apply it to the ridge where the film thickness becomes jam,
It was prebaked, exposed to light using a high pressure mercury lamp through a circuit pattern mask, developed using a special developer and rinse solution, and postbaked to form a resist in areas other than the circuit portion.

次いでバーショク村山社製ビロリンメツメッキ液を用い
て、アルミニウム薄板を陰極とし、初め電流密度Q、 
j A7’d−で平均膜厚2μm115メンキした後、
電流密度を/ A/ddに増加させ、計/θθμm厚の
銅を回路部に形成した。その後、デュポン社製ポリイミ
ドフィルム「カプトン」(膜厚、2すμffI)の両面
にボスチック社製フェノール樹脂−二トリルゴム系接着
剤[XA364−4Jを乾燥後の膜厚が59mになるよ
うに塗布した絶縁性基板の両側から、上記電解メッキを
行ったものをアルミニウム薄板を外側にして750℃で
3θ分間熱圧看して貼り付け、次にスルーホール形成部
にドリルでθ、7θ鴎りの穴をあけた。その後すでに9
に4調整済みのシューリング社製の活性化液アクチベー
ター・ネオガント834、還元液リデューサ−・ネオガ
ン)WAを使って活性化処理し、それからアルミニウム
薄板を36重Il係の塩酸を水で2:3に希釈した液で
エツチング除去した。そのあと無電解メッキ(室町化学
製MK−430)を行ない、次い°CCCCバーショク
社製ロリン酸鋼メツキ液を用いて、電流密度♂A/d−
で膜厚lθθμm(配線槽度夕本/W)鋼メッキを行っ
た。メッキ終了後、スルーホールを介して表裏パターン
間の電気抵抗を測定したところどのスルーホールも5m
Ω以下であった。また、スルーホール内壁部には全くく
ぼみが見られなかった。
Next, using a biroline plating solution manufactured by Bershoku Murayama Co., Ltd., and using a thin aluminum plate as a cathode, the current density was initially Q,
j After coating with A7'd- to an average film thickness of 2 μm,
The current density was increased to /A/dd, and copper with a total thickness of /θθμm was formed in the circuit portion. Thereafter, a phenolic resin-nitrile rubber adhesive [XA364-4J manufactured by Bostic Co., Ltd.] was applied to both sides of the polyimide film "Kapton" manufactured by DuPont (film thickness, 2 μffI) so that the film thickness after drying was 59 m. The above electrolytically plated material is pasted on both sides of the insulating substrate with the thin aluminum plate facing outside under heat and pressure at 750°C for 3θ minutes, and then holes are drilled into the through-hole formation areas with θ and 7θ holes. I opened it. Already 9 after that
Activation treatment was performed using Schuling's activating liquid activator Neogant 834 and reducing liquid reducer Neogant (WA), which had been adjusted to 4 times, and then the aluminum thin plate was treated with 36-fold diluted hydrochloric acid in water for 2 hours. It was removed by etching with a diluted solution. After that, electroless plating (MK-430 manufactured by Muromachi Kagaku Co., Ltd.) was performed, and then using a rophosphate steel plating solution manufactured by CCCC Bershoku Co., Ltd., the current density ♂A/d-
Steel plating was performed with a film thickness of lθθμm (wiring tank thickness: Yumoto/W). After plating, we measured the electrical resistance between the front and back patterns through the through holes, and each through hole was 5m.
It was less than Ω. Further, no depression was observed on the inner wall of the through hole.

実施例コ 膜厚グθμmアルミニウム薄板上に、イーストマンコダ
ツ、り社製ネ“ガ型レジスト「マイクロレジスト747
−110cst Jを乾燥後、膜厚が5μmになる様に
塗布、プレベークして、回路パターンマスクを通して高
圧水銀ランプで露光し、専用の現像液およびリンス液を
用いて現像し、ポストベークして、回路部以外の部分に
レジストを形成した。
Example 1 A negative type resist "Microresist 747" manufactured by Eastman Kodatsu Co., Ltd.
-110cst J was dried, applied to a film thickness of 5 μm, prebaked, exposed to a high pressure mercury lamp through a circuit pattern mask, developed using a special developer and rinse solution, and postbaked. A resist was formed on parts other than the circuit part.

次いでバーンヨウ村山社製ビロリンメツメッキ液を用い
て、アルミニウム薄板を陰極とし、初め電流密度θ、j
 A/dFFI″で平均膜厚2μmμmツメツキ後、電
流密度を♂ly’dnlに増加させ、計/ 、、(: 
、、OAm厚の銅を回路部に形成した。その、後1.デ
ュポン社製ポリイミドフィルム1力、プトン」膜厚2j
μm)の両面にボスチック社製フェノール樹脂−二トリ
ルゴム系接着剤[XA364−4Jを乾燥後の膜厚が5
μmになるように塗布した絶縁性基板の両側から、上記
電解メッキを行なったものをアルミニウム薄板を外側に
して/J−θ℃で3θ分間熱圧着して貼り付け、次にヌ
ル−ホール形成部にドリルでθ、7θmBの穴をあけた
。その後すでにpH111整ずみのン二−リング社製の
活性化液アクチベーター・ネオガン)834、還元液リ
デューサ−・ネオガン)WAを使って活性化処理し、無
電解ニッケルメッキ(日本カニゼン社製シューマーS−
680)を行なった。その後アルミニウム薄板を336
重tsの塩酸を水で2:3に希釈した液でエツチング除
去した。次いでバーショク村山社製ビロリン酸銅メッキ
液を用いて、電流密度、l’ A/d/で膜厚10θμ
m(配線密度5本/s++ )銅メッキを行った。メッ
キ終了後、スルーホールを介して表裏パターン間の電気
抵抗を測定したところどのスルーホールも5mΩ以下で
あった。また、スルーホール内壁部(二は全くくぼみが
見られなかった。
Next, using a biroline plating solution manufactured by Burnyou Murayama Co., Ltd. and using a thin aluminum plate as a cathode, the initial current density θ, j
After plating with an average film thickness of 2 μm μm using A/dFFI'', the current density was increased to ♂ly'dnl, and the total thickness was
. . OAm thick copper was formed in the circuit portion. After that, 1. Polyimide film made by DuPont Co., Ltd., film thickness 2J
The film thickness after drying of Bostik's phenolic resin-nitrile rubber adhesive [XA364-4J] was 5 μm).
On both sides of the insulating substrate coated to a thickness of μm, the electrolytically plated material was attached with the aluminum thin plate on the outside by thermocompression bonding for 3θ minutes at J-θ°C, and then the null-hole forming area was A hole of θ and 7θmB was made with a drill. Thereafter, activation treatment was performed using activating liquid activator (Neogan) 834, reducing liquid reducer (Neogan) WA, manufactured by Nippon Kanigen Co., Ltd. (pH 111), and electroless nickel plating (Schumer S, manufactured by Nippon Kanigen Co., Ltd.). −
680) was carried out. After that, 336 aluminum thin plates were added.
It was removed by etching with a solution prepared by diluting deuterium ts hydrochloric acid with water at a ratio of 2:3. Next, using a birophosphate copper plating solution manufactured by Bershoku Murayama Co., Ltd., a film thickness of 10θμ was obtained at a current density of l'A/d/.
m (wiring density 5 lines/s++) copper plating was performed. After the plating was completed, the electrical resistance between the front and back patterns was measured through the through holes and found to be 5 mΩ or less for all through holes. In addition, no depression was observed on the inner wall of the through hole (No. 2).

実施例3 膜厚50μm亜鉛薄板上に、イーストマンゴダック社製
ネガ型レジスト[マイクロレジスト747−110 c
at 」を乾燥後、膜厚が2μmになる様に塗布、プレ
ベークして、回路パターンマスクを通して高圧水銀ラン
プで露光し、専用の現1fII液およびす・−ヴス液を
用いて現律し、ポストベークして、回路部以外の部分に
レジストを形成した。
Example 3 A negative resist [Microresist 747-110c manufactured by Eastmango Duck Co., Ltd.] was applied on a zinc thin plate with a film thickness of 50 μm.
After drying, the film was coated to a thickness of 2 μm, pre-baked, exposed to light using a high-pressure mercury lamp through a circuit pattern mask, and treated with special current 1fII and S-Vs solutions, and then post-coated. Baking was performed to form a resist on portions other than the circuit portion.

次いでハーンヨク村田社製ビロリン酸銅メッキ液を用層
で、亜鉛薄板を陰極とし、初め電流密度/ A/dm’
で平均膜厚!μm銅メッキした後、電流密度なr A/
dm″に増加させ、計jθμm厚の銅を回路部に形成し
た。その後絶縁フェス(日立化成製WI−640)で導
電パターン面をオーバーコートし、セメダイン社製5G
−EPOEF−008工ポキシ樹脂系接着剤を用いて、
他船薄板を外側にして2枚貼り合わせる。
Next, a copper birophosphate plating solution manufactured by Hahnyoku Murata Co., Ltd. was used as a layer, and a thin zinc plate was used as a cathode, and the initial current density / A / dm' was applied.
The average film thickness! After μm copper plating, the current density r A/
dm", and a total of jθμm thick copper was formed on the circuit part. After that, the conductive pattern surface was overcoated with an insulating film (WI-640 manufactured by Hitachi Chemical Co., Ltd.), and 5G copper manufactured by Cemedine Co., Ltd.
-Using EPOEF-008 engineered poxy resin adhesive,
Attach the two sheets with the other ship's thin plates on the outside.

次にスルーホール形成部にドリルでθ、70wall。Next, drill the through-hole forming part to θ, 70wall.

の穴をあけた。その後すてにpH調整済みのシューリン
グ社製の活性化液アクテベーター・ネオガント834、
還元液リデューチー・ネオガン)WAを使って活性化処
理し、それから亜鉛薄板を5重li憾の水酸化ナトリク
ム水醪液でエツチング除去した。そのあと無電解銅メッ
キ(室町化学製〜に−430)を行ない、次いでノ九−
シヨウ村田社製ピロ4リン酸鋼メッキ液を用いて、電流
密度j A/dnIで膜厚jθμm(配線密度1本/、
、 )銅メッキを行なった。メッキ終了後、スルーホー
ルを介して表裏パターン間の電気抵抗を測定したところ
どのスルーホールも1mΩ以下であった。また、スルー
ホール内壁部(二は全くくぼみが見られなかった。
I made a hole in it. After that, the activation liquid activator Neogant 834 manufactured by Schuling Co., Ltd., which had already been pH adjusted,
Activation treatment was performed using a reducing solution (Reduci Neogan) WA, and then the zinc thin plate was removed by etching with a 5-layer sodium hydroxide solution. After that, electroless copper plating (-430 manufactured by Muromachi Chemical Co., Ltd.) was performed, and then No.9-
Using a pyrotetraphosphate steel plating solution manufactured by Murata Co., Ltd., a film thickness of jθμm (wiring density of 1 line/,
) Copper plating was performed. After the plating was completed, the electrical resistance between the front and back patterns was measured through the through holes and found to be less than 1 mΩ for all through holes. In addition, no depression was observed on the inner wall of the through hole (No. 2).

実施例グ 膜厚20μmスズ薄板上に、イーストマンゴダック社製
ネガ型レジスト「マイクロレジスト747−110 c
st Jを乾燥後、膜厚がs 11mになる様に塗布、
プレベークして、回路パターンマスクを通して高圧水銀
ランプで露光し、専用の現像液およびリンス液を用いて
現イ象し、ポストベークして、回路部以外の部分に7ジ
ストを形成した。
Example: A negative resist "Microresist 747-110c" manufactured by Eastmango Duck Co., Ltd. was applied on a thin tin plate with a film thickness of 20 μm.
After drying st J, apply it to a film thickness of s 11m.
After prebaking, it was exposed to light using a high pressure mercury lamp through a circuit pattern mask, developed using a special developer and rinse solution, and postbaked to form a 7-gist in areas other than the circuit area.

次いでハーンヨク村田社製ビロリン酸銅メッキ液を用い
て、スズ薄板を陰極とし、初め電流密度O6/Vd−で
平均膜厚O,Sμm鋼メッキした後、電流密度をj A
7dm’に増加させ、!θμm厚の銅を回路部に形成し
た。その後絶縁フェス(日立化成製WI−640) で
導電パターン面をオーバーコートし、セメダイン社製8
G−BPOHP−008工ポキシ樹脂系接着剤を用いて
、スズ薄板を外側にして2枚貼り合わせる。次にスルー
ホール形成部にドリルで0.7θ1θの穴をあけた。そ
の後すでにpH調整ずみのVニーリング社製の活性化液
アクチペーター・ネオガント834.還元液リデューサ
−・ネオガン)WAを使って活性化処理し、それからス
ズ薄板をj重量係の水酸化ナトリウム水溶液でエツチン
グ除去した。そのあと無電解鋼メッキ(室町化学製MK
−430)を行ない、次いでバーショウ材用社製ビロリ
ンメツメッキ液を用いて、電流密度夕A/dm’で膜厚
jθμm(配線密度り呻−)銅メッキを行なった。メッ
キ終了後、スルーホールを介して表裏パターン間の゛磁
気抵抗を測定したところどのスルーホールもjmQ以下
であった。
Next, using a birophosphate copper plating solution manufactured by Hahnyoku Murata Co., Ltd., and using a thin tin plate as a cathode, steel was plated with an average film thickness of O, S μm at a current density of O6/Vd-, and then the current density was changed to jA.
Increased to 7dm'! Copper with a thickness of θ μm was formed in the circuit portion. After that, the conductive pattern surface was overcoated with an insulating face (WI-640 manufactured by Hitachi Chemical Co., Ltd.), and
Using G-BPOHP-008 poxy resin adhesive, stick the two sheets together with the thin tin plate facing outside. Next, a hole of 0.7θ1θ was drilled in the through hole forming portion. After that, the activation liquid activator Neogant 834 manufactured by V Nealing, which had already been pH adjusted. Activation treatment was performed using a reducing solution reducer (Neogan) WA, and then the thin tin plate was removed by etching with an aqueous sodium hydroxide solution having a weight ratio of J. After that, electroless steel plating (MK manufactured by Muromachi Chemical Co., Ltd.)
-430), and then copper plating with a film thickness of jθμm (wiring density) was performed using a Viroline plating solution manufactured by Barshaw Materials Co., Ltd. at a current density of A/dm'. After the plating was completed, the magnetic resistance between the front and back patterns was measured through the through holes, and it was found to be less than jmQ in all through holes.

また、スルーホ−ル形成部には全くくぼみが見られなか
った。
Furthermore, no depression was observed in the through-hole formation area.

特許出願人 旭化成工業株式会社Patent applicant: Asahi Kasei Industries, Ltd.

Claims (1)

【特許請求の範囲】[Claims] 金属薄板上にレジストを回路部以外の所に設け、電解メ
ッキして回路部に導電体を形成し、次いで得られた導電
体番絶縁層の両面に金属薄板を外側にして貼り゛付けた
i、スルーホール用穴あけを行にい、それから無電解メ
ッキのための活性化処理を行ない、その後無電解メッキ
を台なってから金属薄板を除去するか、或い゛は、金属
薄板を除去してから無電解メッキを行なった後電解メッ
キを行なう事を特徴とするスルー糸−゛ル回露の形成方
法。
A resist was provided on a thin metal plate in areas other than the circuit area, electrolytic plating was performed to form a conductor in the circuit area, and then the thin metal plate was attached to both sides of the resulting conductive insulation layer with the metal thin plate facing outward. , perform the drilling for the through-hole, then perform the activation treatment for electroless plating, and then remove the metal sheet after electroless plating has been completed, or alternatively, remove the metal sheet. 1. A method for forming a through-thread diode, characterized by performing electroless plating from the beginning and then performing electrolytic plating.
JP5103984A 1984-03-19 1984-03-19 Method of forming through hole circuit Expired - Lifetime JPS60195988A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5103984A JPS60195988A (en) 1984-03-19 1984-03-19 Method of forming through hole circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5103984A JPS60195988A (en) 1984-03-19 1984-03-19 Method of forming through hole circuit

Publications (1)

Publication Number Publication Date
JPS60195988A true JPS60195988A (en) 1985-10-04

Family

ID=12875656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5103984A Expired - Lifetime JPS60195988A (en) 1984-03-19 1984-03-19 Method of forming through hole circuit

Country Status (1)

Country Link
JP (1) JPS60195988A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177796A (en) * 1985-02-01 1986-08-09 旭化成株式会社 Manufacture of through hole circuit
JPS62160792A (en) * 1986-01-09 1987-07-16 旭化成株式会社 Manufacture of through-hole circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5143571A (en) * 1974-10-09 1976-04-14 Hiroki Katsuki KEESUISOSOCHI
JPS5249468A (en) * 1975-10-20 1977-04-20 Fujitsu Ltd Method of producing bothhside printed circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5143571A (en) * 1974-10-09 1976-04-14 Hiroki Katsuki KEESUISOSOCHI
JPS5249468A (en) * 1975-10-20 1977-04-20 Fujitsu Ltd Method of producing bothhside printed circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177796A (en) * 1985-02-01 1986-08-09 旭化成株式会社 Manufacture of through hole circuit
JPS62160792A (en) * 1986-01-09 1987-07-16 旭化成株式会社 Manufacture of through-hole circuit

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