JPS6019252A - Memory address control circuit - Google Patents

Abstract

PURPOSE:To process programs at a high speed and with high efficiency by converting the areas where the program steps and time are extremely needed for program processing into an exclusive circuit. CONSTITUTION:A control part 310 receives both the mode signal and initial information from a control computer 100 via a control line 500. Then the part 310 selects one of address generating parts 320 and 330-340 that is designated by the mode information. The initial data is produced and set to the address generating part which is selected in response to the initial information. The address produced at the selected address generating part is supplied to a picture memory 200 via a multiplexer 350. The picture element data corresponding to said address is transferred to the computer 100 via a data line 400. Hereafter the part 310 supplies the timing signal TMG to the selected address generating part every time the computer 100 outputs the continuous signal to a control line 500. Thus an address is produced for a desired picture element.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to memory address control when controlling addresses from a control converter to a peripheral area located at an arbitrary position from an arbitrary point on an image memory at an arbitrary address interval. Regarding control method.

[Technical background of the invention and its problems]

In image processing, there are quite a lot of processes such as analyzing and tracking the target image (therefore, image data information around the point of interest is required. However, memory address control dedicated to obtaining such peripheral image data is necessary) There was no equipment, and everything was processed by a program.However, current conbeaters can only perform sequential processing, and are not suitable for image processing that requires two-dimensional arrays or plane parallel processing, so there is no program to do this. Address calculation, address output,
The program becomes complicated and the number of steps increases, such as data input/output, analysis, address return, and address calculation. Furthermore, since the address of the image memory is two-dimensional, calculation is not simple. It is still possible to input/output within a certain area using the TV scan method, but when it comes to analysis and tracking, memory address control is not simple. As a result, the time required for memory access increases significantly, the efficiency of the system decreases significantly, and even faster processing cannot be expected.

[Purpose of the invention]

The present invention has been developed in view of the current situation, and eliminates the complexity of the program by converting it into a dedicated circuit for the steps that take an hour to process in a program, making it efficient and fast. The purpose of the present invention is to provide a memory address control circuit that can perform various processing.

[Summary of the invention]

The present invention is a memory address control circuit configured to receive at least the address of a pixel of interest in an image memory, and then sequentially generate addresses of pixels located on a closed curve that includes the pixel of interest therein. .

〔Effect of the invention〕

In image analysis and tracking, it is very important to know information around a point of interest, and performing this at high speed is an issue of increasing efficiency and speed of processing.

For example, in Figures 1 and 2, 10 and 20 are line figures, 11.21 is the point of interest, ' l 2 and 22 are points a certain distance away from the point of interest, and 13', 14.23, and 24°2.
5 is the obtained image data. In Figure 11, it is estimated that 11 and 13 are connected by a straight line due to 13,
Since the straight line from 11 in the X direction is not on 12, it is presumed that it is cut or curved in the middle. 14 is a new point, and by changing the distance from the point of interest, its surrounding relationship is known using other surrounding data.

In addition, in Fig. 5, around the distance 22 from the point of interest, 2
3, 24.25 are obtained, and it is also possible to know the number of branches from the point of interest, as well as the angle between each branch line.

In this way, the state of the point of interest, for example, one end point, one branch point, an isolated point, a continuous line, etc., can be obtained depending on the surrounding conditions of the point of interest. Therefore, being able to easily input this surrounding information is the key to efficient processing and separation. In the conventional technology, everything is processed by programs, and the images are two-dimensional data, but computers inherently do not perform such processing.
! Because of this, it was not possible to improve efficiency or speed.

In the present invention, this weak point, which requires two hours, is implemented in a dedicated circuit, so the processing speed is significantly improved. Furthermore, the computer can obtain data from any distance away from the point of interest by simply making initial settings, which simplifies the program, eliminates complexity, and improves efficiency.

Furthermore, as the distance from the point of interest increases, the interval between the desired surrounding data becomes thicker (although in the present invention, the data interval can also be specified arbitrarily, so there is no need to transfer unnecessary data, making it much more efficient.

[Embodiments of the invention]

FIG. 3 is a diagram showing the overall configuration of an embodiment of the present invention.

In the figure, 100 is a computer, 200 is an image memory, and 300 is an LSI memory address control circuit (MAc), which are interconnected by a data line 400 and a control 11500.

The MAC 300 has a control section 310 and a plurality of address generation sections 320, 330, 340 having different functions. 1lill Hff1l 3 i 0 is MAC3
The overall control of 0 and 0 is performed, for example, according to the flow shown in FIG. 4, and initial data is set in each address generation section and its operation is controlled.

That is, when the MODE signal is supplied from the control computer 1oo via the control line 500, the MC sent by the control computer 1oo to the data line 400 at this time is
Receives initial information from the DE17iij4 and its associated components.

This MOD Ehi information is sent to the address generator 320, 3
30° to 340, and the control unit 310 selects one address generation unit specified by the MOD E i blueprint. Thereafter, the control section 310 creates initial data for activating the selected address generation section according to the received initial information and sets it in the address generation section. The address generated by the selected address generator is supplied to the image memory 200 via the multiplexer 350%, and the pixel data corresponding to this address is transferred to and from the control computer OO via the data bag 400. Thereafter, every time the control computer 100 outputs a continuation signal to the control line 500, the TFT control section 310 supplies the selected timing signal TMG to the selected address generation section, and the next necessary pixel address is created. B9. Ru. When the selected address generating section detects that the generation of the necessary pixel address has been completed using a predetermined logic, it sends an end signal E to the control section 310.
Output ND. When the control unit 3i0 receives the END signal, it notifies the control computer 100 of the END signal, but before this, the control computer 100 stores the image memory 20 on the way.
If it is determined that the input/output with 0 is unnecessary, a new M
It is also possible to specify ODE and move on to the next process.

In this embodiment, one pixel data is input/output between the control computer 100 and the image memory 200, but it is possible to input and output one pixel data for each predetermined number by using an appropriate buffer. It goes without saying that all the data may be transferred at once.

This S-match control section uses an internal counter to periodically
It is sufficient to generate a predetermined number of G signals, so it is not necessarily necessary to supply a continuation signal.

FIG. 5 shows the configuration of the address generator 320 used in this embodiment. The function of this address generation section 320 will be explained using FIG. 6. When an arbitrary pixel 220 of interest is designated by the control computer 100 for a certain image 210 in the image memory 200, a rectangle containing this pixel of interest is designated. Pixel addresses located on 230 are sequentially generated. That is, M that specifies this address generation section 320
After posting the initial report following the OD Ei blue report, the address of the pixel of interest IX, IY, the distance LX from the rectangle 230, the step widths DX, D, and Y in the LYX and Y directions are obtained. The address generation unit 320 uses the upper left point 240 as a reference,
First, the addresses of the pixels located on the upper side of the rectangle 230 are sequentially generated with the step width DX, and then the addresses of the pixels located on the upper side of the rectangle 230 are generated with the step width DX.
The addresses of the pixels located on the sides of the rectangle 230 are generated in +ni order from top to bottom, and the addresses of the pixels located on the bottom side of the rectangle 230 are generated in order from right to left with increments of +1= and D. 1llll increments? iDY generates addresses of pixels located on the left side of the rectangle 230 in order from bottom to top. (When the fileJ fa11 unit 310 receives the first report, it stores X and DY in registers 3 in FIG. 5 in increments of 1).
Set it to 1.32. Further, the address (XS, YS) of the upper left point 240 in FIG. 6 is determined by XS = I X-LX YS = I Y-LY and set in registers 33 and 34.

Similarly, the address (XE) of the lower right point 250 in FIG.

YE) by XE -I X+LX YE-I Y+LY and set these in registers 35 and 36. Also, the end address (XIE; Nl), YEND)
As luck would have it, the addresses Xs and Ys of the upper left point are stored in register 37.
Set it to 38. After setting the current address, move from the upper left point 240 to the first pixel position XN on the rectangle 230.
=XS, Y', N=YS is sent to the current register 39.40, selector 41.42 selects input terminal 2, respectively, and output address X.

The first 1υJ cents of X in register 39.40 as Y
N, , YN are supplied to the image memo IJ 200.

Below, there is a continuation signal from the control computer 100! i1] When the signal is supplied to the control unit 310, the control unit 310 generates the signal TMG each time. Address generation section 310 shown in FIG.
Thereafter, pixel addresses located on the sides of the rectangle 230 are sequentially output based only on this signal TMG. For this purpose, the address generator 310 has control logics 43, 44, and 45 that generate internal control signals by themselves. Input signals for these control logics are obtained by comparators 47-49. Comparator 47 compares the contents of register 33 with XS and
When XN≦XS, A-J" is obtained.

The comparator 48 compares the contents XE and XN of the register 35, and when XN≧XE, outputs B-$ 1 //.

The comparator 48 compares the contents YS and YN of the register 34, and when YN≦YS, the output C=“V1”.

The comparator 49 compares the contents YE and YN of the register 36, and when YN≧YE, the output D='1''.

The control logic 43 inputs the signals A and B to the selector 4.
It outputs control signals XI, X'2°XS for switching input terminals of 1. Similarly, the control logic 44 receives the signals C and D as input and outputs control signals Yl, Y2, Y2,
Output Y3. Talented 1. FIG. 7 shows the relationship between the input and output signals of the control logic 43.

On the other hand, the current addresses XN and YN are divided into increments of DX,
Arithmetic units 50 and 51 are provided to increase or decrease the DY.

The control logic 45 generates control signals for controlling the operations of these computing units 50 and 51, and the relationship between the input and output signals is shown in FIG.

The signal X I N H is a signal for inhibiting calculation by the arithmetic unit 50 and is used when generating pixel addresses located on the left side and on the left side of the rectangle 230 . The signal YINH is a signal for inhibiting the calculation by the calculation unit 51, and the signal XUD used when generating the pixel addresses located on the upper and lower sides of the rectangle 230 is a signal for prohibiting the calculation by the calculation unit 51. For register 3
This specifies whether the content DX of 1 is to be added (']") or subtracted. When generating a pixel address for the position iQ ("1") on the upper side of the rectangle 230, the signal YUD is
specifies whether the arithmetic unit 51 adds (when it is '1'') or subtracts the content I) of the register 32 from the content Yll of the register 40 or subtracts it from the pixel at 1 located on the right side of the rectangle 230. It becomes '1'' when generating /.

Now, from the initial state described above, when the signal TMG is supplied, XINH is now 10'' and 'z'INH is '1''.
Therefore, the signal TMG is supplied to the arithmetic unit 50 via the gate 52, but since the gate 53 is closed, the operation of the arithmetic unit 51 is prohibited. Also, since XUD is also 'I'', the arithmetic unit 50 calculates the contents of the register 39, XN (=XS+
Add DX to DX) and set this in register XN'39. As a result, XN>XS, so the signal X2 becomes '
1", and the -trector 41 extracts it as X N total output address X.

On the other hand, since the Y direction is an area where increase/decrease is prohibited,
2 (Y YS is output address Y 7 and extracted.Hereafter, the nth
When the signal TMC is supplied for the second time, the address XS+nDX,Y is output. In this way, XN is added by the j1st order, but when XN≧XE, the output B of the comparator 47 becomes ゝJ''(!
:The selector 41 outputs XE as address X.

Therefore, XINH is '1' and is prohibited from increasing or decreasing in the X direction, while Y/NH becomes % 0 //, and the inhibition is lifted. From then on, the output address X is constant X'FJ, and the Y address depends on the signal TMG. lliNth increase (
right-hand side interval).

Thereafter, addresses for the lower side section and the left side section are sequentially generated in the same manner, and when the upper left point 240 is reached, the end determination circuit 54 detects this and outputs an END signal to end address generation. The end determination circuit 54 converts the output addresses X and Y into the contents of the end address registers 37 and 38, XEND and YgNI, respectively.
),! : Compare and detect if both match.

Note that by adding the end addresses XEND and YEND to the initial information transferred from the control computer 100, and placing the supplied end addresses in the registers 37 and 38, the pixel positions on the middle of the rectangle 230 can be moved without going around the sides of the rectangle 230. You can also end it with .

FIG. 9 is a block diagram of address generator 330 of FIG. 3. This address generator 330G can sequentially access pixel data on a circle of radius r centered on any pixel of interest (IX, IY) as shown in FIG. 1O. In this case, the control combiner 100 supplies the address of the pixel of interest IX, IY, radius r, step angle Δθ, start angle θS, end angle θE, following the MODE information that defines the address generator 330. . However, if θS and θE are omitted, all addresses on the circumference are generated.

In Figure 9, 60.61 is the attention point Atres IX
, IY register, 62 is the distance r register from the point of interest,
63 is a tick register for the address to be accessed; 64 is an accumulator for angle θ; 65 is a register for holding the accumulated value θ;
6.67 is a circuit that calculates the values of Sinθ and CO8θ based on the accumulated value of θ, and is usually made into a table in ROM etc. 6B and 69 are multiplication circuits that calculate rcosθ and rsinθ, 70° and 71 are rcosθ+IX ,rsinθ
This is an addition circuit that calculates +IY.

When the control unit 310 receives the parameters of the initial information, it sets IX, IY, r, and Δθ to registers 60, 61, and 62.63, respectively, as initial cents. At the same time, O8 is set in the θ cumulative value register 65 (0 when θS is not supplied). Also, θE is selected into the register 72 (2π if θE is not supplied).

Therefore, sin θ according to the contents of register 65.

The cos θ value is read from ROM9.10. ．． ．． Sent to 69. At this time, the accumulator 7 of θ performs addition of registers 63 and 65, and the result is
Although it is output on the output line, the register 65i is still not latched. In the multipliers 68 and 69, the r register 62
Multiply the contents of by sinθ and cosθ to obtain rCO8
θ.

1 Find sin θ. In addition, the contents of these output G and IX registers 60, and the contents of the IY register 61 (subtraction)
sin θ, cos θ), and the X, Y address of the first pixel on the circle I X + cos θ, IY−
l-sin θ is full. However, although this result includes values below the decimal number, the image memory address is valid only for integer values, so the decimal part is discarded and only the integer part is supplied to the image memory 200. Once the X and Y addresses are determined, the control computer 100 transfers data to the image memory 200. When this data transfer is completed, the control unit 310 transmits the signal T.
MG is output, and the output of the θ accumulator 64 is latched into the register 65. Therefore, based on these values, <x, y addresses are calculated as described above. Here, the X and Y addresses are determined after θ is determined. Since f is constructed of no hardware, it goes without saying that the X and Y addresses can be determined instantly from θ.

On the other hand, the contents of the register 65 are determined by the comparator 73 by θE(
! : Since it is compared, when θ>θE, the comparator 73
generates an END signal and notifies the control unit 310. The control unit 310 knows the end from this, and the control computer 100
Also let me know this.

As described above, by performing peripheral address control in arbitrary increments at a point that is an arbitrary distance away from an arbitrary digit 1·t in the image memory, data is transferred from the control computer to a circular peripheral area from an arbitrary point. can do.

Although the explanation of the remaining address generator 340 in FIG. 3 is omitted, it is also possible to use one that sequentially generates pixel addresses located on closed curves of other different shapes. can.

Alternatively, 8 Rie is an address generator with other functions, and when a pixel of interest (IX, I'Y) is specified, it continuously generates all the pixel addresses of eight points around the pixel of interest (IX, I'Y). After specifying the position, it receives the direction data from the control converter that corresponds to the position change.
There can be 114 devices that move according to the direction data of jfK and sequentially generate pixel addresses for each day.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams for detailed explanation of the present invention;
FIG. 3 is a diagram showing one embodiment of the present invention, FIG. 4 is a diagram for explaining the operation of one embodiment of the present invention, and FIG. 5 is a diagram showing an embodiment of the present invention. 6 is a diagram for explaining the operation of the address generation section shown in FIG. 5. FIGS. 7 and 8 are control signals for the address generation section shown in FIG. 5. 9 is a diagram illustrating another configuration of the address generation section used in an embodiment of the present invention. FIG. 10 is a diagram illustrating the operation of the address generation section shown in FIG. 9. It is.

Claims (3)

[Claims] (1) Memory address control that is connected between an image memory and a control unit that inputs and outputs pixel data between the image memory and generates the address of pixels to be input and output in the image memory. In the circuit, the means for receiving the address of a desired pixel of interest from the control unit and generating initial data includes at least some pixel addresses located on a predetermined closed curve including the pixel of interest therein according to the initial data. 1. A memory address control circuit comprising: address calculation means for generating an address; and means for controlling timing so that the address calculation means sequentially generates an address at predetermined increments along the closed curve. (2) The memory address control circuit according to claim 1, wherein the closed curve is a circle or a square. (3) The timing control means includes means for storing an end pixel address, and means for detecting a match between the end pixel address and the pixel address outputted by the address calculation means, and the detecting means detects a match. 2. The memory address control circuit according to claim 1, wherein no pixel address is generated thereafter.