JPS60192438A - Multiplex circuit - Google Patents

Abstract

PURPOSE:To attain ease of multiplex for data of plural terminal devices by generating a transfer clock corresponding to a transfer speed of each signal based on a clock and a frame signal applied from the line and extracting data sequentially from a buffer memory in response to the said transfer speed. CONSTITUTION:When a fixed bit is detected from data of a data line 219 in a fixed bit detection/addition circuit 220, a clock from a transfer clock line 206 of a line is supplied to a transfer clock line 215 and a part excluding the preceding and succeeding fixed bit out of the data from the data line 219 is written on a buffer memory 209. If the fixed bit representing the youngest number is detected before the n-th buffer memory is not written, the clock from the transfer clock line 206 at the line side is switched immediately to the transfer clock line 215 to write the data on the buffer memory 209. Bits (n-set) are transmitted at the same time by using the clock of a terminal device data clock line 208 asynchronously with writing on the terminal device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplexing circuit connected between a line control device and a terminal.

Conventionally, in this type of circuit, the number of uplink and downlink lines was one to one, and even if the ratio of transfer speeds was large, multiplexing was not considered. An object of the present invention is to provide a multiplexing circuit capable of multiplexing and transmitting a plurality of signals having different transfer speeds.

The multiplexing circuit of the present invention is supplied from the line side! A transfer clock corresponding to the transfer speed of each signal is created based on the lock and frame signals, data is sequentially retrieved from the puffer memory according to the transfer speed, and a clock is created that identifies the data of the terminal with the lowest number. The system is characterized by adding bits and identifying the line number from the bits, making it possible to multiplex data from multiple terminals, which has not been considered until now.Next, referring to the drawings, Explain in detail.

FIG. 1 is a block diagram showing an example of a conventional system that does not take multiplexing into consideration. The terminal side has a terminal device 101, and
A terminal side register 102, a line side register 103, a clock generation circuit 104, and a bit addition circuit 105 are provided between a data line 106 and a clock line 107 on the line side.

These circuits have a one-to-one correspondence between the terminal side and the line side, and if the transfer speeds on the terminal side and the line side are different, they simply convert the transfer speeds.

Next, time charts of the multiplexing circuit and data transfer in the present invention are shown in FIGS. 2 and 3. In Figure 2,
200 to 202 are n terminal devices. 203-20
A data line 5 connects the terminal devices 200-202 and the corresponding buffer memories 209-211. In the buffer memories 209 to 211, the write clock and read clock are asynchronous and have different speeds. 206 is a transfer clock line supplied from the line side, and this transfer clock is synchronized with data transfer on the line side.

Reference numeral 20 designates a clock generation circuit that generates a clock for transmitting and receiving data in the terminal devices 200 to 202 from the clock on the transfer clock line 206 and sends it to the clock line 208. 218 is the buffer memory 209 to 21
1 is time-division multiplexed and sent to line 219. Or, conversely, the data from line 219
This is a circuit that distributes the data to the memory 209-211. 212
~214 is the buffer memory and multiplexing/distribution circuit 2
This is a data line connecting the 1st day. 21δ to 21ma are clocks supplied to the buffer memory, and are synchronized with the clock 206 supplied from the line side, but the multiplexing/distributing circuit 218 divides them one by one in a time-division manner. Supplied sequentially. 220 adds a fixed bit to the beginning of the data from the memory 209, that is, the data from the terminal device 200 with the lowest number. Conversely, it is a circuit that detects the fixed bit from data from the data line 219. 22
1 is a frame signal indicating the delimiter of a data group and is supplied from the line side.

First, the operation will be explained along the flow of data from the terminal device to the line side. Data from terminal devices 200-202 are sent through data lines 203-206, sampled every 20 days, and stored in puffer memories 209-211 corresponding to each terminal. Sending to the line side is based on the frame signal 221. First, a clock signal from the clock signal line 206 is supplied to the transfer clock line 215, and the clock signal is sent from the buffer memory 5a09 until the next frame signal comes to the frame signal line 221. The data is read out, and the fixed bit detection/addition circuit 220 adds a fixed bit (101 or ゛II) to the beginning of the data.
A fixed bit is added to the end of the data and sent to the data line 219. This bit adds the same bit to data read from any memory.

Then, it receives the next frame signal and transfers it to the next frame signal.
15 is switched to the transfer clock line 216, data is read from the buffer memory 210 in the same way until the next frame signal arrives on the frame signal line 121, and the fixed bit detection/addition circuit At step 220, a fixed bit is added and sent to the data line 219. Similarly, when data has been sent to the n-th buffer memory 211, it returns to the first buffer memory 209 and repeats the data transfer.

Next, the operation will be explained along the flow of data from the line side to the terminal device. When the fixed bit detection/addition circuit 220K detects a fixed bit (the same bit added to the data read from the puffer memory 209) from the data on the data line 219, the transfer clock and stitch 20 on the line side are detected.
6 is supplied to the transfer clock line 215, and the portion of the data from the data line 219, excluding the preceding and following fixed bits, is written to the batza memo 135aO9. When the next frame signal is received, the clock supply is switched from the transfer clock line 21δ to the transfer clock line 216,
Similarly to the above, the data is written to the buffer memory 210 except for the preceding and following fixed bits. In the same way, after writing to the nth buffer memory 211, write to the first buffer memory 20.
Go back to 9 and continue writing. However, before writing to the nth buffer memory, the fixed bit indicating the smallest number (
As soon as the same bit as the bit added to the data read from the puff memory 209 is detected, the clock from the transfer clock line 206 on the line side is transferred.
data is written into the buffer memory 209. Then, when the next frame signal arrives, it is sequentially written into the buffer memory 210. The terminal device data clock line 208 is sent to the terminal device asynchronously with the above writing.
Send n pieces at the same time using black and white.

The time chart in FIG. 3 shows the relationship between data on the line side and the terminal device side. 31 is a frame signal, 32
is the data on the line side, and 33 to 35 are the data on the terminal device. Data from the lowest terminal is a●, am..., data from the next terminal is b, pb,... and the next is C●
, 01..., a 0° bit synchronized with the frame signal is added to the beginning of the a1 data group. This is a fixed bit added to the data read from the buffer memory 209 mentioned above.

As explained above, the present invention uses this circuit that uses a buffer memory, etc., to connect several terminal devices with a slow transfer speed to a line with a high transfer speed, and to connect a plurality of terminal devices with one line. This has the advantage that the number of lines with high transfer speeds capable of transmitting and receiving data is small compared to the number of terminal devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional circuit, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart showing an embodiment of data transfer in the present invention. 206=Transfer clock line on line side, 20'/: Data transfer clock Gl for terminal device, block creation circuit, 20BS data transfer clock line for terminal device, 209-211: Puffer memory, 212-214=Data line, 216- 21 Ma: Transfer clock line, 218: Multiplexing/distribution circuit% 219: Data line (line), 220: Fixed bit detection/addition circuit, 2
2:t$7 frame signal line,! s1: frame signal, 32
: Data on the line side, 33 to 36: Data on the terminal device. −212=

Claims (1)

[Claims] In a multiplexing circuit that multiplexes and transmits multiple signals with different transfer speeds, a circuit that creates a transfer clock corresponding to the transfer speed of each signal based on the clock supplied from the line side; #A circuit that sequentially extracts signals from the battery memory according to the transfer speed and multiplexes signals for multiple terminals,
1. A multiplexing circuit comprising: a circuit for determining a line code by adding a bit for identifying the signal of the lowest terminal number.