JPS60192157U - noise reduction circuit - Google Patents

noise reduction circuit

Info

Publication number
JPS60192157U
JPS60192157U JP7889784U JP7889784U JPS60192157U JP S60192157 U JPS60192157 U JP S60192157U JP 7889784 U JP7889784 U JP 7889784U JP 7889784 U JP7889784 U JP 7889784U JP S60192157 U JPS60192157 U JP S60192157U
Authority
JP
Japan
Prior art keywords
noise reduction
circuit
reduction circuit
output
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7889784U
Other languages
Japanese (ja)
Other versions
JPH0627023Y2 (en
Inventor
茂 三木
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP1984078897U priority Critical patent/JPH0627023Y2/en
Publication of JPS60192157U publication Critical patent/JPS60192157U/en
Application granted granted Critical
Publication of JPH0627023Y2 publication Critical patent/JPH0627023Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
  • Picture Signal Circuits (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案−実施例のブロック図、第2図はノンリ
ニアエンファシスの特性図、第3図は従来例のブロック
図である。 2・・・FM復調器、10・・・ノイズキャンセル回路
、14・・・ディエンファシス回路。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a characteristic diagram of non-linear emphasis, and FIG. 3 is a block diagram of a conventional example. 2... FM demodulator, 10... noise cancellation circuit, 14... de-emphasis circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ノンリニアエンファシスされた映像信号をFM変調して
記録した媒体より前記映像信号を再生する磁気記録再生
装置のノイズ低減回路において、再生FM信号を復調す
る復調手段と、該復調手段出力を入力とするバイパスフ
ィルタ型ノイズキャンセル回路と、該バイパスフィルタ
型ノイズキャンセル回路出力を入力とするノンリニアデ
ィエンファシス回路とを備えることを特徴とするノイズ
低減回路。
In a noise reduction circuit of a magnetic recording and reproducing device that reproduces a video signal from a medium recorded by FM modulating a video signal subjected to non-linear emphasis, a demodulation means for demodulating the reproduced FM signal and a bypass inputting the output of the demodulation means are provided. 1. A noise reduction circuit comprising a filter-type noise canceling circuit and a non-linear de-emphasis circuit which inputs the output of the bypass filter-type noise canceling circuit.
JP1984078897U 1984-05-29 1984-05-29 Noise reduction circuit Expired - Lifetime JPH0627023Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984078897U JPH0627023Y2 (en) 1984-05-29 1984-05-29 Noise reduction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984078897U JPH0627023Y2 (en) 1984-05-29 1984-05-29 Noise reduction circuit

Publications (2)

Publication Number Publication Date
JPS60192157U true JPS60192157U (en) 1985-12-20
JPH0627023Y2 JPH0627023Y2 (en) 1994-07-20

Family

ID=30623302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984078897U Expired - Lifetime JPH0627023Y2 (en) 1984-05-29 1984-05-29 Noise reduction circuit

Country Status (1)

Country Link
JP (1) JPH0627023Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5880107A (en) * 1981-11-04 1983-05-14 Hitachi Ltd Preephasizing circuit of video tape recorder

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5880107A (en) * 1981-11-04 1983-05-14 Hitachi Ltd Preephasizing circuit of video tape recorder

Also Published As

Publication number Publication date
JPH0627023Y2 (en) 1994-07-20

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