JPS6019149B2 - thyristor - Google Patents

thyristor

Info

Publication number
JPS6019149B2
JPS6019149B2 JP10316779A JP10316779A JPS6019149B2 JP S6019149 B2 JPS6019149 B2 JP S6019149B2 JP 10316779 A JP10316779 A JP 10316779A JP 10316779 A JP10316779 A JP 10316779A JP S6019149 B2 JPS6019149 B2 JP S6019149B2
Authority
JP
Japan
Prior art keywords
layer
type
concentration
thyristor
base layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10316779A
Other languages
Japanese (ja)
Other versions
JPS5627967A (en
Inventor
正美 内藤
篤雄 渡辺
勉 八尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10316779A priority Critical patent/JPS6019149B2/en
Publication of JPS5627967A publication Critical patent/JPS5627967A/en
Publication of JPS6019149B2 publication Critical patent/JPS6019149B2/en
Expired legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0839Cathode regions of thyristors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Description

【発明の詳細な説明】 本発明はサィリスタに係り、特に電力制御に好適な高耐
圧・大電流サィリス外こ関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thyristor, and particularly to a high voltage and large current thyristor suitable for power control.

一般にサィリスタは、隣接する層間にpn接合を形成す
るように交互に導電型の異なる連続したpnpnの4層
構造を有する半導体基体と、半導体基体の両外側のp層
及びn層にオーミック接触した1対の主電極と、主電極
間を非導通状態から導適状態に変換するための電気的、
光学的等のトリガー手段とを具備した構成となっている
In general, a thyristor consists of a semiconductor substrate having a four-layer structure of consecutive pnpn layers of alternating conductivity types so as to form a pn junction between adjacent layers, and a single layer in ohmic contact with the p-layer and n-layer on both outer sides of the semiconductor substrate. A pair of main electrodes and an electrical connection for converting the non-conducting state to the conducting state between the main electrodes.
The structure includes an optical trigger means.

その一典型を図面により説明する。A typical example will be explained with reference to the drawings.

一般的な製法に従って、n型半導体ウェハを出発素材と
して、拡散によりp型層を形成するものと仮定する。第
1図において半導体基体10は、半導体基体10の一方
の主表面101に露出するp型ェミツ夕層1,p型ェミ
ツタ層1に隣接するn型ベース層2,n型ベース層2に
隣接するp型ベース層3,およびp型ベース層3に隣接
し、p型ベース層3と共に半導体基体10の他方の主表
面102に露出するn型ェミッタ層4から構成されてい
る。そしてp型ェミッタ層1とn型ベース層2の間、n
型ベース層2とp型ベース層3の間、及びp型ベース層
3とn型ェミッタ層4の間には、それぞれpn接合J,
,J2及びJ3が形成されている。
It is assumed that a p-type layer is formed by diffusion using an n-type semiconductor wafer as a starting material according to a general manufacturing method. In FIG. 1, a semiconductor substrate 10 includes a p-type emitter layer 1 exposed on one main surface 101 of the semiconductor substrate 10, an n-type base layer 2 adjacent to the p-type emitter layer 1, and an n-type base layer 2 adjacent to the n-type base layer 2. It consists of a p-type base layer 3 and an n-type emitter layer 4 adjacent to the p-type base layer 3 and exposed on the other main surface 102 of the semiconductor substrate 10 together with the p-type base layer 3. Between the p-type emitter layer 1 and the n-type base layer 2, n
Between the type base layer 2 and the p-type base layer 3 and between the p-type base layer 3 and the n-type emitter layer 4, pn junctions J,
, J2 and J3 are formed.

半導体基体10の一方の主表面101上、他方の主表面
102上で少くともn型ェミッタ層4の露出部及び他方
の主表面102上でp型ベース層3の露出部の一部には
、それぞれ1対の主電極及びトリガー信号付与手段、即
ちアノード電極5,カソード電極6及びゲート電極7が
形成されている。n型ェミッタ層4とp型ベース層3と
は、領域8において、カソード電極6によって部分的に
短絡されており、いわゆる短絡ヱミッタ構造となつてい
る。第2図は、従来の電力用高耐圧サィリスタの、pn
pn部分における不純物濃度分布の一例を示す。
At least the exposed portion of the n-type emitter layer 4 on one main surface 101 and the other main surface 102 of the semiconductor substrate 10 and the exposed portion of the p-type base layer 3 on the other main surface 102 include: A pair of main electrodes and trigger signal applying means, ie, an anode electrode 5, a cathode electrode 6, and a gate electrode 7, are formed respectively. The n-type emitter layer 4 and the p-type base layer 3 are partially short-circuited by the cathode electrode 6 in the region 8, forming a so-called short-circuit emitter structure. Figure 2 shows the pn
An example of impurity concentration distribution in the pn portion is shown.

p型ェミッタ層1の半導体基体表面101付近では、ア
ノード電極5と良いオーミック接触をとるためと、導適
状態で多量のホールをn型ベース層2に注入するために
、不純物濃度が高くなっている。この種サィリスタは、
主電極5,6間に、アノード側を正、カソード側を負と
して、通常順方向耐圧と呼ばれる限界電圧以下の順方向
電圧を印加した場合は阻止状態を保ち、ゲート電極等の
トリガー手段によってトリガー信号を付与すると導適状
態に移行する。
The impurity concentration near the semiconductor substrate surface 101 of the p-type emitter layer 1 is high in order to make good ohmic contact with the anode electrode 5 and to inject a large amount of holes into the n-type base layer 2 in a conductive state. There is. This kind of thyristor is
When a forward voltage below the limit voltage, usually called forward breakdown voltage, is applied between the main electrodes 5 and 6, with the anode side positive and the cathode side negative, the blocking state is maintained and the trigger is triggered by a trigger means such as a gate electrode. When a signal is applied, it shifts to the conductive state.

サィリスタは、このように、オン(導通状態)、オフ(
阻止状態)のスイッチ機能を有するものであるから、阻
止状態では耐圧が高く、かつ漏れ電流が小さく、導適状
態では電圧降下(オン電圧)が低く、さらにスイッチン
グ速度の速いもの理性能が良いといえる。
The thyristor is thus turned on (conducting state) and off (
Since it has a switching function (blocking state), it has high withstand voltage and low leakage current in blocking state, low voltage drop (ON voltage) in conductive state, and has high switching speed and good mechanical performance. I can say that.

良く知られているように、日頃阻止状態での漏れ電流n
‘ま11二MIg/{1一M(Q,十Q2 )}で表わ
される。
As is well known, the leakage current n in the blocking state is
'Ma112MIg/{11M(Q, 10Q2)}

ここで1gは逆バイアスされたJ2接合の空乏層で生成
されるキャリャによる電流、Mは雪崩増倍係数、Q,は
pnpトランジスタ部分の電流増幅率、Q2 はnpn
トランジスタ部分の電流増幅率である。順方向耐圧VB
Oは、M(Q,十Q2)が1となるときのアノード・カ
ソード間印加電圧である。このことから、漏れ電流を小
さく、また耐圧を高くするには、M及び(Q,十Q2)
を小さくすればよいことがわかる。電力用サィリスタで
は、通常、第1図に示す短絡ェミッタ構造等によって、
小電流レベルにおけるn型ェミツタ層4からの電子注入
をおさえるようにしてあるので、一般にQ2 はQ,
に比べて小さく、電流増幅率としてはQ,が支配的であ
る。
Here, 1g is the current due to carriers generated in the depletion layer of the reverse biased J2 junction, M is the avalanche multiplication coefficient, Q, is the current amplification factor of the pnp transistor part, and Q2 is the npn
This is the current amplification factor of the transistor part. Forward breakdown voltage VB
O is the voltage applied between the anode and cathode when M(Q, +Q2) becomes 1. From this, in order to reduce the leakage current and increase the withstand voltage, M and (Q, 10Q2)
It turns out that you can make it smaller. Power thyristors usually have a short-circuit emitter structure as shown in Figure 1.
Since electron injection from the n-type emitter layer 4 is suppressed at a small current level, Q2 is generally Q,
Q is smaller than Q, and Q is dominant as a current amplification factor.

そこで、阻止特性を良くするには、n型ベース層2の抵
抗率を高くし、pn接合J2接合での電界を弱めて係数
Mを小さくすると共に、pnpトランジスタ部分の電流
増幅率Q,を小さくすることが大切である。電流増幅率
Q,は、p型ェミッタ層1からn型ベース層2へのホー
ルの注入効率y,とn型べ−ス層2でのホールの輸送効
率8,との積8,y,で与えられる。
Therefore, in order to improve the blocking characteristics, the resistivity of the n-type base layer 2 is increased, the electric field at the pn junction J2 is weakened, and the coefficient M is decreased, and the current amplification factor Q of the pnp transistor portion is decreased. It is important to do so. The current amplification factor Q, is the product of the hole injection efficiency y from the p-type emitter layer 1 to the n-type base layer 2 and the hole transport efficiency 8 in the n-type base layer 2, 8,y. Given.

8,は、p型ェミッタ層1から注入されたホールのうち
どれだけの割合のものがpn接合J2の空乏層に到達す
るかを表すものである。
8 represents the percentage of holes injected from the p-type emitter layer 1 that reach the depletion layer of the pn junction J2.

即ち、ホールがn型ベース層2の空乏化されていない領
域を通過して、どれだけの量が再結合で消滅することな
いこ空乏層に達するかを表わすものである。従ってn型
ベース層2の厚さが厚い程3,は小さくなる。この観点
から、従来は、サィリスタの高耐圧化に当ってはn型ベ
ース層を十分に厚くする方策が取られていた。
In other words, it represents how many holes pass through the non-depleted region of the n-type base layer 2 and reach the depletion layer without being annihilated by recombination. Therefore, the thicker the n-type base layer 2, the smaller 3 becomes. From this point of view, conventional measures have been taken to increase the breakdown voltage of thyristors by making the n-type base layer sufficiently thick.

しかし、n型ベース層を厚くすると、‘1’ n型ベー
ス層の抵抗が大きくなってオン電圧が増大する。
However, when the n-type base layer is made thicker, the resistance of the '1' n-type base layer increases and the on-state voltage increases.

‘2} n型ベース層の抵抗が注入キャリャで変調され
るのに時間がかかるために、ターンオン時間が長くなる
、さらに【3} n型ベース層に蓄積されるキャリャ量
が多くなるのでターンオフ時間が長くなる。
'2} Since it takes time for the resistance of the n-type base layer to be modulated by the injected carriers, the turn-on time becomes longer, and [3} The turn-off time increases because the amount of carriers accumulated in the n-type base layer increases. becomes longer.

といった特性上重大な欠点が生ずる。This causes serious drawbacks in terms of characteristics.

このため、オン特性、スイッチング特性を良好に保つた
ままサィリスタを高耐圧化することは従来困難であった
。本発明の目的は、上記の欠点を除去した新規な高耐圧
サィリス夕を提供することであり、その特徴とするとこ
ろは、ェミッタ層の構造を規定することにより注入効率
を小さくして、電流増幅率を小さくし、これにより、ベ
ース層を厚くすることなしに高耐圧化をはかる点にある
For this reason, it has conventionally been difficult to increase the withstand voltage of a thyristor while maintaining good on-characteristics and switching characteristics. An object of the present invention is to provide a new high-voltage silister which eliminates the above-mentioned drawbacks, and its characteristics are that the injection efficiency is reduced by defining the structure of the emitter layer, and current amplification is achieved. The objective is to reduce the ratio and thereby achieve high breakdown voltage without increasing the thickness of the base layer.

本発明によるサィリスタの特徴とするところをさらに具
体的に言えば、2つの中間ベース層のうち低不純物濃度
を有するベース層に隣接し、半導体基板の一方の主表面
に露出するェミッ夕層の不純物濃度分布が、前記一方の
主表面からの深さが大きく低濃度である部分と、半導体
中に不純物として入った場合に該ェミッタと同じ導亀型
を与える金属等と半導体とを合金化した際に生ずる再結
晶層により形成され、前記一方の表面からの深さの小さ
い高濃度部分とから成り、低濃度部分の最大濃度が1.
5×1び6aめms/の以下、かつ低濃度部分と高濃度
部分の境界からpn接合までの深さが60仏m以上とな
るようにした点にある。以上の構成によりサィリスタの
高耐圧化をはかれることを、本発明者らの実験結果をも
とに、図面により説明する。
More specifically, the thyristor according to the present invention is characterized by impurities in the emitter layer adjacent to the base layer having a low impurity concentration among the two intermediate base layers and exposed on one main surface of the semiconductor substrate. When the semiconductor is alloyed with a part where the concentration distribution is deep and low from the one main surface, and a metal etc. that gives the same conductive turtle type as the emitter when it enters the semiconductor as an impurity. It is formed by a recrystallized layer formed by a recrystallized layer, and consists of a high concentration portion having a small depth from the one surface, and the maximum concentration of the low concentration portion is 1.
The depth from the boundary between the low-concentration portion and the high-concentration portion to the pn junction is set to be less than 5 × 1 × 6 am ms/and more than 60 mm. The fact that the thyristor can be made to have a high breakdown voltage with the above configuration will be explained with reference to the drawings based on the experimental results of the present inventors.

問題となるェミッタ層の導電型はp型でもn型でも同じ
なので、p型ェミッタについて説明する。第3図は、本
発明によるサイリスタのp型ェミッタ層の不純物濃度分
布の模式図の一例である。
Since the conductivity type of the emitter layer in question is the same whether it is p-type or n-type, the p-type emitter will be explained. FIG. 3 is an example of a schematic diagram of the impurity concentration distribution of the p-type emitter layer of the thyristor according to the present invention.

本発明のようにェミッタ層表面の高濃度層を合金法で形
成すると、高濃度部分と低濃度部分の境界は、一般に図
のように段階状になる。ここで、図に示すように、低濃
度部分の最大濃度をN,高濃度部分の厚をZ,高濃度部
分と低濃度部分の境界からpn接合J,までの距離をW
とする。第4図に、順方向耐圧VBとWの関係を示す。
When the high concentration layer on the surface of the emitter layer is formed by an alloy method as in the present invention, the boundary between the high concentration portion and the low concentration portion generally becomes stepwise as shown in the figure. Here, as shown in the figure, the maximum concentration of the low concentration part is N, the thickness of the high concentration part is Z, and the distance from the boundary between the high concentration part and the low concentration part to the pn junction J is W.
shall be. FIG. 4 shows the relationship between forward breakdown voltage VB and W.

ここでの順方向耐圧は高温(125qo)での漏れ電流
密度を3mA/塊に制限したときの電圧であり、前述の
サィリスタが非導適状態から導適状態へ移行する電圧V
Boよりも低い。前記VBは、素子の信頼性の面から、
素子の実質的な順方向耐圧を与えるものである。図から
わかるように、Wを4・さくすると耐圧VBも低くなる
The forward breakdown voltage here is the voltage when the leakage current density at high temperature (125 qo) is limited to 3 mA/block, and is the voltage V at which the thyristor described above transitions from the non-conducting state to the conducting state.
Lower than Bo. The VB is determined from the viewpoint of device reliability.
This provides a substantial forward breakdown voltage of the device. As can be seen from the figure, when W is reduced by 4.0, the withstand voltage VB also becomes lower.

これは、ェミッタPEの高濃度部分がpn接合に近いと
、低濃度部分からn型ベース層へのホール注入の外にホ
ールを多量に有する高濃度部分からもホールがn型ベー
ス層に注入されるため、pn接合J,からn型ベース層
へのホール注入が増し、ッ,が大きくなって電流増幅率
Q,が大きくなるからである。Wが大きくなり、高濃度
部分がpn接合J,から遠くなるに従って高濃度部分の
影響が弱くなり、Wが60〆mを超えると高濃度部分の
影響がなくなって、VBが一定の高いに保たれる。即ち
、Wを60仏m以上とすることによって、耐圧が高く、
かつエッチングのばらつき等でWが多少ばらついても、
耐圧のばらつきの少し、サィリスタを得ることができる
This is because when the high concentration part of the emitter PE is close to the pn junction, in addition to holes being injected from the low concentration part into the n type base layer, holes are also injected into the n type base layer from the high concentration part which has a large number of holes. This is because the injection of holes from the pn junction J, into the n-type base layer increases, and the current amplification factor Q, increases. As W becomes larger and the high concentration part becomes farther from the pn junction J, the influence of the high concentration part becomes weaker, and when W exceeds 60 m, the influence of the high concentration part disappears and VB is kept at a constant high level. dripping That is, by setting W to 60 fm or more, the withstand voltage is high;
And even if W varies slightly due to etching variations,
It is possible to obtain a thyristor with little variation in breakdown voltage.

ただし、Wを不必要に大きくするとオン電圧が高くなる
ので好ましくない。Wの上限としては200〜250山
m以下とすることが好ましい。本発明のようにェミッタ
層表面の高濃度部分を合金による再結晶層により形成す
ると、高濃度部分と低濃度部分の境界付近のキャリャラ
ィフタィムが短くなるため、、低注入時の高濃度部分か
らのホール注入がさえられる。
However, unnecessarily increasing W increases the on-state voltage, which is not preferable. The upper limit of W is preferably 200 to 250 m. When the high-concentration part on the surface of the emitter layer is formed by a recrystallized layer made of alloy as in the present invention, the carrier lifetime near the boundary between the high-concentration part and the low-concentration part becomes short. Hole injection from

このため、高濃度部分を拡散等で形成する場合に比べて
低濃度部分の厚さWの下限を小さくすることができ、低
濃度部分形成のプロセス自由度が増えるという効果があ
る。第5図は順方向耐圧VBとェミッタ層の低濃度部分
の最大濃度Nとの関係を示す図である。
Therefore, the lower limit of the thickness W of the low concentration portion can be made smaller than in the case where the high concentration portion is formed by diffusion or the like, and there is an effect that the degree of freedom in the process of forming the low concentration portion is increased. FIG. 5 is a diagram showing the relationship between the forward breakdown voltage VB and the maximum concentration N of the low concentration portion of the emitter layer.

Wが60仏m以上のとき、第5図に示す関係はWに依ら
なかった。低濃度部分の最大濃度Nが小さくなると、ェ
ミツタ層からのホール注入効率y,が小さくなり、図の
ように耐圧VBが上がる。この効果はNが1.5×1び
6atoms/嫌以下の範囲で現われ、Nが1×1び6
atoms/が以下になると効果が顕著になることが図
から明らかである。この傾向は、Wが60山m以上であ
ればほとんど変化しない。従って、不純物濃度Nを1.
5×1び6atoms/が以下、好ましくは1×1び6
atoms/倣以下とすれば、ェミッタ層の注入効率を
小さくして耐圧を上げるという本発明の効果を得ること
ができる。このとき、不純物濃度Nの最小値は、ェミッ
タ層の低濃度部分を拡散で形成するときには必然的に隣
援するベース層の濃度以上になり、また、他の方法、例
えばェピタキシャル生長により形成するようなときには
、製造技術の制限で決まる。また、今問題にしているェ
ミツタ層と隣接ベースの間のpn接合で逆耐圧をもたせ
る場合には、Nの下限値を、ェミッタ層側の空乏層が高
濃度部分まで伸びない程度におさえることが、素子表面
での電界強度を弱めて表面でのブレークダウンをおさえ
るために望ましい。以下、本発明の一実施例を説明する
。抵抗率が200〜3000弧,厚さ約900ムmのn
型シリコン単結晶ゥェハを出発材料とし、この両面から
1250qoで約4■時間アルミニウムを拡散し、深さ
約120仏mの低濃度p型拡散層を形成した。
When W was 60 m or more, the relationship shown in FIG. 5 did not depend on W. When the maximum concentration N of the low concentration portion becomes smaller, the hole injection efficiency y from the emitter layer becomes smaller, and the breakdown voltage VB increases as shown in the figure. This effect appears when N is less than 1.5 × 1 and 6 atoms/atoms, and N is 1 × 1 and 6
It is clear from the figure that the effect becomes more pronounced when atoms/ is less than or equal to . This tendency hardly changes if W is 60 m or more. Therefore, the impurity concentration N is set to 1.
5 x 1 and 6 atoms/ is less than or equal to, preferably 1 x 1 and 6 atoms/
If it is less than atoms/copy, the effect of the present invention of reducing the injection efficiency of the emitter layer and increasing the withstand voltage can be obtained. At this time, the minimum value of the impurity concentration N is inevitably higher than the concentration of the adjacent base layer when the low concentration portion of the emitter layer is formed by diffusion, and when formed by other methods such as epitaxial growth. In such cases, it is determined by the limitations of manufacturing technology. In addition, in order to provide a reverse breakdown voltage in the pn junction between the emitter layer and the adjacent base, which is the current problem, it is possible to suppress the lower limit of N to such an extent that the depletion layer on the emitter layer side does not extend to the high concentration area. , is desirable in order to weaken the electric field strength on the element surface and suppress breakdown on the surface. An embodiment of the present invention will be described below. n with a resistivity of 200 to 3000 arc and a thickness of about 900 mm
Using a type silicon single crystal wafer as a starting material, aluminum was diffused from both sides of the wafer at 1250 qo for about 4 hours to form a low concentration p-type diffusion layer with a depth of about 120 m.

次に、ウェハの両面をそれぞれ約20〆mエッチング除
去し、ウェハの片面から燐を1100午0で選択拡散し
て厚さ7〜10umのn型ェミツタ層を形成した。さら
にウェハのn型ェミツタ層と反対側の表面にアルミニウ
ムを約20仏mの厚さに蒸着し、このアルミニウム膜を
介してタングステン板のアノード電極を730℃,約2
0分間の熱処理によりウェハに合金接着した。
Next, both sides of the wafer were etched away by approximately 20 m, and phosphorus was selectively diffused from one side of the wafer at 1100 pm to form an n-type emitter layer with a thickness of 7 to 10 um. Furthermore, aluminum was vapor-deposited to a thickness of about 20 mm on the surface of the wafer opposite to the n-type emitter layer, and the anode electrode of the tungsten plate was heated at 730°C for about 20 cm through the aluminum film.
The alloy was bonded to the wafer by heat treatment for 0 minutes.

これにより、合金接着した側のウェハ表面に不純物濃度
約1×1びもtoms/の,厚さ約3山mの高濃度p型
層ができた。次に、ウェハのn型ェミッタ層がある側の
表面上に、アルミニウムを所定の形状に蒸着してカソー
ド電極及びゲート電極とした。さらにウェハ端面を所定
の形状に形成し、素子を完成した。この素子のn型ベー
ス厚さは約650仏mであり、p型ヱミッタ層の不純物
濃度分布は第6図に示すとおりであった。
As a result, a highly concentrated p-type layer with an impurity concentration of about 1×1 toms/m and a thickness of about 3 m was formed on the surface of the wafer on the side to which the alloy was bonded. Next, aluminum was vapor-deposited in a predetermined shape on the surface of the wafer on the side where the n-type emitter layer was located to form a cathode electrode and a gate electrode. Furthermore, the end face of the wafer was formed into a predetermined shape, and the device was completed. The n-type base thickness of this device was about 650 mm, and the impurity concentration distribution of the p-type emitter layer was as shown in FIG.

本実施例のサィリスタの特性は、順方向の高温耐圧が4
.2kv,オン電圧が2.0V,ターンオン時間が約4
ムs,ターンオフ時間は200〃s以下であつた。
The characteristics of the thyristor of this example are that the high temperature withstand voltage in the forward direction is 4.
.. 2kV, on-voltage is 2.0V, turn-on time is about 4
The turn-off time was less than 200 seconds.

これと比較するために、p型ェミッタ層の低濃度部分の
最大濃度を3×1び7atoms/地とした従来型のサ
ィリスタでは、本実施例と同じ4.2kvの高温耐圧を
得るのに要するn型ベース層の厚さが約800山mとな
り、このとき、オン電圧が約2.3V,ターンオン時間
が約7仏s,夕−ンオフ時間が約300仏sであった。
For comparison, in a conventional thyristor in which the maximum concentration of the low concentration portion of the p-type emitter layer is 3 x 17 atoms/ground, it is necessary to obtain the same high temperature withstand voltage of 4.2 kV as in this example. The thickness of the n-type base layer was about 800 mm, the on-voltage was about 2.3 V, the turn-on time was about 7 seconds, and the turn-off time was about 300 seconds.

このように、本実施例のサィリスタでは、導通特性及び
スイッチング特性が良好で、かつ高耐圧の素子が得られ
た。以上の実施例では、アノード電極金属板をウェハに
接着する例を述べたが、本発明はそのような合に限られ
るものではなく、例えば蒸着等でアルミニウム膜を付着
したゥヱハに金属板を接着することなく熱処理を加えて
アルミニウムとウェハ面を合金化し、そのときに生じる
再結晶層をェミッタ表面の高濃度部分としても良い。さ
らに、合金化する膜を蒸着等でウェハに付着させず、金
属薄膜とゥェハを接触させて熱処理し、合金化しても良
い。
Thus, in the thyristor of this example, an element with good conduction characteristics and switching characteristics and high breakdown voltage was obtained. In the above embodiments, an example was described in which an anode electrode metal plate was bonded to a wafer, but the present invention is not limited to such a case. For example, a metal plate may be bonded to a wafer on which an aluminum film has been attached by vapor deposition Alternatively, heat treatment may be applied to alloy aluminum and the wafer surface, and the resulting recrystallized layer may be used as a high concentration portion on the emitter surface. Furthermore, instead of attaching the film to be alloyed to the wafer by vapor deposition or the like, the metal thin film and the wafer may be brought into contact and heat treated to form an alloy.

要するに、合金化により再結晶層を生ずる方法でさえあ
れば、どのような方法でも本発明に適用できる。また、
合金化する膜もアルミニウムに限ることなく、例えばN
−Si共晶のように合金化して半導体ウェハ中に入った
とき、ェミッタ層と同じ導電型を与えるものなら何でも
良い。本発明は、第3図や第6図に示されたように、p
型ェミッタ層の低濃度部分の濃度最大になる位置が、高
濃度部分と低濃度部分の境界に位置するものに限られず
、第7図に示すように低濃度部分内に濃度最大の位置が
あるものにも適用可能である。
In short, any method can be applied to the present invention as long as it produces a recrystallized layer through alloying. Also,
The film to be alloyed is not limited to aluminum; for example, N
-Any material may be used as long as it gives the same conductivity type as the emitter layer when alloyed into a semiconductor wafer such as -Si eutectic. The present invention, as shown in FIGS. 3 and 6,
The position of the maximum concentration in the low concentration part of the emitter layer is not limited to the boundary between the high concentration part and the low concentration part, and as shown in FIG. 7, there is a position of maximum concentration within the low concentration part. It can also be applied to things.

このような濃度分布は、例えば拡散中にアウトデフユー
ジヨン(OutDiff瓜ion)によりウエハ表面付
近の濃度が下がる場合に生じる。以下本発明をn型シリ
コンウェハを用いた例により説明したが、p型シリコン
基板を用いて上記の実施例におけるp型領域とn型領域
を逆にしても本発明の効果に変わりはない。
Such a concentration distribution occurs, for example, when the concentration near the wafer surface decreases due to out diffusion during diffusion. Although the present invention has been described below using an example using an n-type silicon wafer, the effects of the present invention remain the same even if a p-type silicon substrate is used and the p-type region and n-type region in the above embodiments are reversed.

また、本発明の効果はトリガー手段に影響されないため
、トリガー手段として実施例で説明した電気的トリガー
の他の手段、例えば光トリガーとしても良いし、またシ
ョートェミツタでないサィリスタにも本発明は適用でき
る。以上に述べたように、本発明によれば、ェミッタの
注入効率を小さくすることにより、ベース幅を厚くせず
にサィリスタを高耐圧化できるので、オン特性やスイッ
チング特性を損うことなく高耐圧化できるという効果を
有する。
Further, since the effect of the present invention is not affected by the trigger means, other means than the electric trigger described in the embodiments, such as an optical trigger, may be used as the trigger means, and the present invention is also applicable to thyristors other than short emitters. can. As described above, according to the present invention, by reducing the injection efficiency of the emitter, the thyristor can be made to have a high breakdown voltage without increasing the base width. It has the effect of being able to be converted into

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は典型的なサィリスタの構造図、第2図はサィリ
スタの一般的な不純物濃度分布図、第3図は本発明にお
けるサィリスタのェミッタ層の濃度と寸法の定義図、第
4図,第5図は本発明の効果を説明するための説明図、
第6図は本発明の実施例におけるpェミッタ層の不純物
濃度分布図、第7図は本発明の実施例におけるpェミッ
タ層の・純物濃度分布の変形例を示す図である。 1……p型ェミッタ層、2……n型ベース層、3……p
型ベース層、4……n型ヱミッタ層、5・・・・・・ア
ノード電極、6・・・・・・カソード電極、7・・・・
・・すート電極。 鉾1図 第2図 夫3図 ズ4図 矛5図 プ6図 矛7図
Fig. 1 is a structural diagram of a typical thyristor, Fig. 2 is a general impurity concentration distribution diagram of a thyristor, Fig. 3 is a definition diagram of the concentration and dimensions of the emitter layer of the thyristor in the present invention, Figs. Figure 5 is an explanatory diagram for explaining the effects of the present invention,
FIG. 6 is a diagram showing the impurity concentration distribution of the p emitter layer in the embodiment of the present invention, and FIG. 7 is a diagram showing a modified example of the impurity concentration distribution of the p emitter layer in the embodiment of the present invention. 1...p-type emitter layer, 2...n-type base layer, 3...p
Type base layer, 4... n-type emitter layer, 5... anode electrode, 6... cathode electrode, 7...
...Soot electrode. Hoko 1 Figure 2 Husband 3 Figures 4 Spear 5 Figure 6 Spear 7 Figure

Claims (1)

【特許請求の範囲】 1 互いに反対側に位置する一対の主表面および前記主
表面間で隣接層間にpn接合を形成するように交互に導
電性の異なるpnpnの連続した4層を有する半導体基
体と、両主表面においてそれぞれ外側層にオーミツク接
触された一対の主電極と、主電極間を非導通状態から導
通状態に移行するためのトリガー信号を付与する手段と
を具備し、2つの中間層のうち、低不純物濃度を有する
一方の中間層に隣接し、一方の主表面に露出する一方の
外側層の不純物濃度分布が、前記一方の主表面からの深
さが大きくて低濃度である部分と、前記一方の主表面か
らの深さが小さくて高濃度である部分とから成るサイリ
スタにおいて、該高濃度部分が合金による再結晶層によ
り形成され、低濃度部分の最大濃度が1.5×10^1
^6atoms/cm^3以下であり、かつ、低濃度部
分と高濃度部分の境界から一方の中間層と一方の外側層
との間に形成されるpn接合までの深さが60μm以上
であることを特徴とするサイリスタ。 2 上記一方の外側層の導電型がp型であることを特徴
とする特許請求の範囲第1項記載のサイリスタ。 3 上記一方の外側層の導電界がn型であることを特徴
とする特許請求範囲第1項記載のサイリスタ。
[Scope of Claims] 1. A semiconductor substrate having a pair of main surfaces located on opposite sides and four consecutive pnpn layers having different conductivities alternately so as to form a pn junction between adjacent layers between the main surfaces. , a pair of main electrodes each in ohmic contact with the outer layer on both main surfaces, and means for applying a trigger signal for transitioning between the main electrodes from a non-conducting state to a conducting state, Among them, the impurity concentration distribution of one of the outer layers adjacent to one of the intermediate layers having a low impurity concentration and exposed on one of the main surfaces is such that the impurity concentration distribution is a part that has a large depth from the one of the main surfaces and has a low concentration. , the high concentration portion is formed by a recrystallized layer of the alloy, and the maximum concentration of the low concentration portion is 1.5×10 ^1
^6atoms/cm^3 or less, and the depth from the boundary between the low concentration part and the high concentration part to the pn junction formed between one intermediate layer and one outer layer is 60 μm or more. A thyristor featuring: 2. The thyristor according to claim 1, wherein the conductivity type of the one outer layer is p-type. 3. The thyristor according to claim 1, wherein the conductive field of the one outer layer is n-type.
JP10316779A 1979-08-15 1979-08-15 thyristor Expired JPS6019149B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10316779A JPS6019149B2 (en) 1979-08-15 1979-08-15 thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10316779A JPS6019149B2 (en) 1979-08-15 1979-08-15 thyristor

Publications (2)

Publication Number Publication Date
JPS5627967A JPS5627967A (en) 1981-03-18
JPS6019149B2 true JPS6019149B2 (en) 1985-05-14

Family

ID=14346942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10316779A Expired JPS6019149B2 (en) 1979-08-15 1979-08-15 thyristor

Country Status (1)

Country Link
JP (1) JPS6019149B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142531U (en) * 1984-02-28 1985-09-20 株式会社明電舎 Gate turn-off thyristor

Also Published As

Publication number Publication date
JPS5627967A (en) 1981-03-18

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