JPS60191324A - Clock transmission circuit - Google Patents

Abstract

PURPOSE:To transmit a fault of own device and to display assuredly the working state of the device by supplying a command signal given from own data processor or a command signal given from another data processor which receives the clock of a data transmission line and then transmitting the clock after a fixed period of time. CONSTITUTION:A clock signal (a) is produced from a clock generating circuit 1 of a clock transmission circuit and supplied to the input of one side of a logical integration circuit 11 of a transmission clock generating circuit 2. While the output of a monostable multivibrator 12 is supplied to the input of the other side of the circuit 11. The output of the circuit 11 is sent to a transmission circuit from the circuit 2 in the form of a transmission clock signal (d) via a driver 3. A command signal given from an own data processor and a command signal given from another data processor are supplied to the multivibrator 12. Then a clock signal is transmitted from the circuit 2 after a fixed period of time. The state of a fault of the own data processor is transmitted accurately to another data processor connected via a transmission line. Thus the working state of the data processor is displayed assuredly.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of application on parallel racks) The present invention relates to a clock sending circuit for sending a clock signal from a data processing device to another device via a transmission path.

(Prior Art) Conventionally, a clock signal sent to a transmission path in a data processing device has also been used to indicate the status of the source data processing device. That is, it was also used to indicate a data processing enabled state when the clock signal was being sent out, and to indicate a data processing disabled state when the clock signal was disconnected. On the other hand, in some conventional data processing devices, clock transmission can be started and clock transmission can be stopped by internal control of the data processing device. However, even if a data processing disabled state is displayed due to disconnection of the clock signal, other data processing devices connected via the transmission path will be able to see the details of the disabled state, i.e., the 'vt critical dynamic operation of the power cut-off ring is disabled. The problem with the display was that it was not clear whether the device was currently in operation or whether it was temporarily inoperable during initial settings.

(Object of the Invention) The object of the present invention is to input a continuously generated clock signal, input a command signal from its own data processing device, or receive a clock signal transferred via a transmission path. A data processing device configured to eliminate boarding defects and accurately display the operation of the device by sending out a clock signal for as long as VC within a certain period of time after inputting a command signal from another data processing device. The purpose is to provide one route for clock transmission.

(Structure of the Invention) The clock transmission p1 path according to the present invention transfers the clock signal between the own data processing device and another data processing device that is not connected to the own data processing device via the transmission path. This clock signal is used in a data processing device configured to perform data transfer using this clock signal, and is configured to include a clock generation means and a clock generation drive means.

The clock generating means is for continuously generating a clock signal.

The clock generation drive means inputs a clock signal from the clock generation means and a command signal from its own data processing device, or receives a clock signal from another data processing device that is receiving a clock signal transferred via a transmission line. σ is also used to send out the clock signal +3' only for a certain period of time after the 41st command is input manually.

(Operation of the Invention) The present invention provides the following features: when a data processing device is in a state capable of data processing;
The internal control of the own data processing device can continuously resend the clock sending command to its own clock sending circuit at fixed intervals, and other data processing devices connected via the transmission line can also transmit the data. This method focuses on the fact that, if the processing is possible, the control of another device can send a clock sending command to the clock sending circuit of the own data processing device that is the clock sending source and is connected via a transmission line.

Start clock transmission to the transmission line by command No. 48 under internal control of the own data processing device or a command signal under control of another data processing device connected via the transmission path,
It has a function that cuts off the clock if no command is given again within a certain amount of time after the command.

Normally, the clock transmission operation is performed only by a command from the internal control of the own data processing device, and when the own data processing device is able to collect data, the clock is sent out for a certain period of time from the internal control of the own data processing device. A continuous clock is transmitted by commanding the transmission of the clock. If data processing is not possible, the clock transmission command will be stopped by the internal control of the own data processing device, so the clock transmission will be automatically cut off after a certain period of time after the final Ronx transmission command. It waits for a clock transmission command under the control of another connected data processing device, and based on the detection of clock disconnection of the transmission source data processing device, it issues a clock transmission command to the other data processing device connected via the transmission path. If the signal is issued, the clock transmission operation is performed in the same manner as the clock transmission command signal from the own data processing device.

In this way, it is possible to display to the other data processing apparatus that has issued the clock transmission command that data processing is not possible after the internal control of the own data processing apparatus has stopped.

(Example) Next, the present invention will be explained in detail with reference to one item.

FIG. 1 is a block diagram showing an example of the actual width of a clock sending circuit of a data processing device according to the present invention.

In Figure 1, 1 is a clock generation circuit for generating clocks, 2 is a transmission clock generation circuit for generating a clock signal to be sent to a transmission line, and 3 is for sending the generated transmission clock signal to a transmission line. These circuits constitute the clock transmission circuit of the data processing device.

Next, the main points of the operation of the clock sending circuit will be explained. The clock generation circuit 1 generates a base clock signal of a sending clock. This baselock signal is supplied to the transmission clock generation circuit 2. The transmission clock generation circuit 2 generates a clock transmission command generated by internal control of a data processing device including the transmission clock generation circuit 2,
The transmission line is fully closed and a clock transmission command generated under the control of another data processing device that receives the generation lock of the circuit 2 and generates a transmission clock is input. The sending clock generation circuit 2 does not generate a sending clock when it does not receive any of the above clock sending commands. According to item 1, the clock signal is not sent from the driver circuit 3 to the transmission line, and the clock is cut off. When the transmission clock generation circuit 2 receives a clock transmission command generated by the internal control of its own data processing device, the transmission clock generation circuit 1
Based on the base clock signal from the base clock, generation of the transmission clock is started from the time of the clock transmission command, and generation is continued for a certain period of time. The generated sending clock is sent from the driver circuit 3 to the transmission path. If the clock sending command is re-sent due to the internal control of the own data processing device within a certain period of time while the sending clock generation circuit 2 is generating the sending clock, the sending clock continues for a certain period of time after the command is input. In this way, if the clock sending command is continuously input within a certain period of time, a stable clock signal is sent from the driver circuit 3 to the transmission line. Normally, a transmission clock is generated 1p through a transmission line! Another data processing device receiving the 1M2 generation lock may send out a clock sending command. Next, if the clock sending command is not re-sent by the internal control of the own data processing device within a certain period of time during which the sending clock generation circuit 2 is generating the sending clock based on the clock sending command, the data processing device cannot process the data. As a state, generation of the transmission clock is stopped after a certain period of time.

As a result, the driver circuit 3 is connected to the transmission clock generation circuit 2.
When the generation of the sending clock is stopped, the sending of the clock to the transmission line is immediately stopped, and the clock signal on the transmission line is disconnected. Next, the other data processing device that has detected the disconnection of the clock via the transmission path determines that the own data processing device that caused the disconnection of the clock signal is in a data processing disabled state. In order to determine the degree of the disabled state, a clock sending command is sent to the sending clock generating circuit 2 of the clock sending data processing device. In other data processing devices mentioned above, when a clock signal is detected within a certain period of time after the command, the clock sending source data processing device recognizes that the internal control of the Ichihara supply state has been stopped, and If the clock signal is not detected within the specified time, it is determined that the Ichihara disconnection has occurred in the clock sending source data processing device.In addition, the data sending circuit 2 of the clock sending source data processing device that caused the disconnection of the clock signal is connected to the transmission line. When a clock transmission command is input from another data processing device connected via the transmission line, the data processing device immediately starts transmitting a clock signal, unless there is an interruption in the supply of Ichihara to itself or a failure υ. In this way, the other data processing device M connected via the transmission line performs exactly the same operation as when a clock transmission command is input from the clock signal. The contents of the disabled state can be known by detecting the clock by executing the clock sending command after the clock is cut off.

FIG. 2 is a block diagram showing an embodiment of the clock sending circuit according to the present invention shown in FIG. 1.

Hereinafter, referring to FIG. 72 with reference to FIG. 1, the clock generation circuit 1 in FIG. 1 is a clock generation circuit that generates a pace clock signal on the signal line a. The transmission clock generation circuit 2 shown in FIG. 1 is composed of an AND circuit 11 and a monostable multivibrator 12. The monostable multivibrator 12 receives a clock transmission command signal (on signal &!b) inputted by internal control of its own data processing device.
It has a re-trigger function that is triggered by the rising edge of the signal line f and the rising edge of the clock transmission command signal (on the signal line f) input via the transmission line by internal control of another data processing device that receives the clock signal via the transmission line signal. It is something that The AND circuit 11 receives as input the pace clock signal (@kotosen a) supplied from the clock generation circuit 1 and the output signal (signal ?fBC) of the monostable multivibrator 12. The driver circuit 3 is an AND circuit 11 in FIG.
Input 1 as the output clock (on signal line d)
2. This is a driver circuit that outputs a signal (on signal line e) as a clock signal onto the transmission path.

In FIG. 3, A and B are signal waveforms on signal lines a and b, respectively, C is a signal waveform at the time of a single trigger, and DF is a signal waveform on signal lines df, respectively.

Assuming that the monostable multivibrator 12 can be retriggered within the time T1, the output time of true I of the signal C (waveform C in Figure 3) at the time of a single trigger without retriggering is T2. Suppose that

Next, the clock sending operation of the clock sending circuit will be explained in detail with reference to FIGS. 2 and 3.

A base clock signal with a period To (see FIG. 3(A)) is input from the clock generation circuit 1 to the 1-AND circuit 11. The clock sending command is not received by the internal control of the data processing device equipped with this clock sending circuit on the signal line b (see Figure 3 (B)), and the clock sending command is not received by the control of another data processing device that receives the clock via the transmission path. When the clock sending command is not received on the signal line f (see Fig. 3 (F)), the output signal C of the first stable multivibrator 12 (see Fig. 3 (C)
) is "false", so the output signal sent from the AND circuit 11 to the signal line d (see Figure 3 CD)) is "false", and this signal is input as the sending clock. Output signal from the dry nozzle circuit 13 to the transmission line (Fig. 3)
(see E) also becomes "false", and the clock signal on the transmission path is disconnected.

Next, the clock transmission command A Akane No. of port 11 (Fig. 3 (B)
When the monostable multivibrator 12 receives the pulse of the output signal (see FIG. 3(C)), the signal on the signal line rises to true 1, and the output signal (see FIG.
Output for 1.

When this signal (see FIG. 3C) is input as "true", the AND circuit 1) outputs a transmission clock signal having a signal waveform to the driver circuit 13.

The driver circuit 3 drives the input line e to the transmission line,
TO outputs the same period clock signal. Monostable-r k
While the Fh power signal (see No. 319 (C)) of the f-by-break 12 is 1 true, the output on the signal line e is in a clock driven state.

Output signal of monostable multivibrator 12 (Fig. 3 (C)
)) continues to be "true" if the trigger is re-input, that is, the signal on line 48 is "true", and if the signal is re-input within the time T1.

Now, the time T3<T1, that is, the time T3 required to be retriggered
At time T3, which is shorter than time 1, as a clock transmission command from the own data processing device,
When the pulse is re-inputted, monostable multivibrator 1
No. 2 is triggered, and the output signal (see FIG. 3(C)) continues to remain at Etora for a time T2 after the re-triggering. A data processing device equipped with a sending clock generation circuit maintains this state and performs data processing when data processing is possible.

However, if the internal control of the data processing device stops and the pulse of "1 true" is not input to the monostable multinode (ibrator 12) as a clock transmission command on the signal line d within the time T1, the monostable multinode (ibrator 12) 12 assumes that the data processing device (not shown) associated with the present invention is unable to process the data, and generates the signal waveform (FIG. 3(C)) after the time T2 by the final input from the top of the signal line. As a result, the AND circuit 11 stops driving the sending clock signal (see FIG. 3(D)), so the driver circuit 13 similarly outputs the clock driving signal (see FIG. 3(D)). (See Figure 3 (C)) The meeting is stopped. With this action,
The clock signal on the transmission line is disconnected.

When the clock signal on the transmission line is suddenly disconnected, other data processing devices connected via the transmission line 7 detect the clock disconnection of the clock sending source data processing device. Therefore, before determining whether data processing is not possible, a clock sending command is sent to the data processing device from which the clock is sent via the signal line f and the transmission line. When the clock signal is cut off due to a stop in its own internal control, if the pulse on the signal if is "pallid" in the data processing device that is the source of the clock, this signal is input to its own monostable multivibrator 12. , on the signal line f, the output signal (see FIG. 3 (C)) becomes true 1 and is output to the AND circuit 11 when the @ symbol rises to true -1.Hereinafter, the signal on the signal line f In an operation similar to that of rising to "true", the driver circuit 13 immediately outputs a clock signal to the signal line e. In other data processing devices that receive this clock signal via the transmission line, when the clock is detected after the command is issued, the data processing device that sends the clock is in a state where data processing is not possible due to internal control stoppage in the state where the clock signal is being supplied. recognize that it exists. Furthermore, if no clock is detected after a certain period of time has elapsed, it is determined that the power of the clock sending source data processing device has been cut off.

(Effects of the Invention) As explained above, the present invention inputs a continuously generated clock signal, inputs a command signal from its own data processing device, or inputs a clock signal transferred via a transmission line. By transmitting a clock signal for a certain period of time after inputting a command signal from another data processing device, an abnormal state of one data processing device can be transmitted to another data processing device connected via a transmission line. This has the advantage that the information is transmitted quickly and accurately, and the operating status can be displayed accurately.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a clock sending circuit according to the present invention. FIG. 2 is a pronk circuit diagram showing a detailed example of the main parts of the clock sending circuit of FIG. 1. FIG. 3 is a time chart showing the operation of the clock output path in FIG. 1.100Φ・Clock generation circuit 2・・Fist・・φ Sending clock generation circuit 3.13・・Driver circuit 11・・・AND circuit 12・・φψ・Monostable multivibrake Patent applicant
NEC Corporation Representative Patent Attorney Hisashi Inoro

Claims (1)

[Claims] A clock signal is transferred between the own data processing device and another data processing device that is not connected to the own data processing device via a transmission path, and the data is transferred using the clock signal. In the clock sending circuit of the configured data processing device, a clock generating means for continuously generating the clock signal μ, and the clock signal from the clock generating means are input, and a command signal from the own data processing device is inputted. or transmitting the clock signal only for a certain period of time after inputting a command signal from the other data processing device that is receiving the transferred clock signal via the transmission path. 1. A clock transmission circuit comprising clock generation driving means.