JPS60191298A - Fundamental wave cycle extraction circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a fundamental frequency period extraction circuit capable of extracting a fundamental frequency (pitch) in real time from a signal having a large number of harmonic components.

[Technical Background of the Invention] - If the fundamental frequency (pitch) can be extracted in real time from a complex waveform like a musical tone, that is, a waveform that contains a large number of high frequency components, it will be possible to detect the melody of music etc. Then, it becomes possible to generate musical tones and chords with tones that serve as accompaniment.

A fundamental wave period extraction circuit for such use is disclosed, for example, in Japanese Patent Laid-Open No. 55398/1983, and its circuit diagram is shown in FIG. This circuit detects the positive peak voltage level of the input signal waveform A, holds this level with a time constant circuit consisting of a capacitor 1 and a resistor 2, and uses this held voltage as the threshold voltage for the next step. A positive peak extraction circuit 3 detects the coming positive peak voltage as a peak wave when it exceeds this level and holds this voltage in the same way again, and a negative peak voltage is detected in the same way. A flip-flop f5f is set by the output signal B+ of the positive peak voltage extraction circuit 3, and the negative peak voltage extraction circuit 4 is provided to hold the negative peak voltage extraction circuit 4.
By resetting the output signal B- of the flip-flop 5, a substantial fundamental periodic signal C is obtained from the flip-flop 5. Note that FIG. 2 is a timing chart of the circuit shown in FIG. 1.

Here, the period of the fundamental wave periodic signal C obtained by the flip-flop 5 can be determined by counting the reference clock signal Dt obtained from a crystal oscillation circuit or the like. That is, the pitch frequency kfp, the frequency of the reference clock signal fD, the number of pitches to be counted tNp
When the number of reference clock signals is ND, the pitch frequency fp is given by the following equation.

For example, as shown in Figure 2, the number of reference clock signals counted in a period of two cycles (Np = 2) from the falling edge of the pitch signal (fundamental wave periodic signal) C is 18 (
No = 18), if the frequency fD of the reference clock signal is set to 32768 Hz, then f
p is 3640Hz. In order to increase the calculated pitch frequency by R1,+ degrees, the number of NPs is usually determined so that the number of NDOs is approximately several thousand.

[Problems with background technology]

In the circuit shown in FIG. 1, the pitch frequency jp is determined by counting the number of pitches NP and the number ND of reference clock signals. Therefore, as shown in FIG. 3, if a normal pitch signal c1 malfunctions due to noise or other causes and becomes like C2, for example, the Np''160 reference clock signal count period T1 for pitch signal C1 is T2 for pitch signal c2.
=15/16・T1, so it becomes shorter by 1/16・T1. This means that the calculated pitch frequency will be 16/15 times the correct frequency. As described above, in the circuit of FIG. 1, since the pitch signal C is correct and the pitch is adjusted from now on, it is not always possible to obtain an accurate pinch, and the reliability is low.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to provide a highly reliable fundamental wave period extraction circuit that can always accurately obtain the fundamental wave period contained in an input signal. It's about doing.

[Summary of the invention]

The fundamental wave period extraction circuit according to the present invention includes a pitch period detection circuit and a pitch correction circuit, and counts reference clock signals in the pitch period detection circuit, thereby detecting at least one fundamental wave period of an input signal including an arbitrary fundamental wave period. To obtain a count value corresponding to the wave period, the pitch correction circuit counts the reference clock signal, and the value reaches the count value of the ζ pitch period detection circuit by taking into account the counting error of the reference clock signal in the pitch period detection circuit. I am trying to allow the output of the input signal only when

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing the configuration of the fundamental wave period extraction circuit of the present invention. As shown in the figure, this circuit is composed of a pitch period detection circuit 10 and a pitch correction circuit 20.

The pitch period detection circuit 10 is supplied with an input signal including an arbitrary fundamental wave period, for example, a pitch signal C obtained by a circuit as shown in FIG. 1 and a reference clock signal. This pitch period detection circuit 10 has an internal counter, and by counting the reference clock signal Dt with this counter, a count value E corresponding to at least one fundamental period of the pitch signal C is obtained. The count value E obtained by the pitch period detection circuit 10 is calculated by the pitch correction circuit 2.
0. The pitch correction circuit 20 is supplied with the pitch signal C and the reference clock signal. This pitch correction circuit 20 also has a counter therein, and this counter counts the reference clock signal, and this count value F is calculated by taking into account the count error of the reference clock signal in the counter in the pitch period detection circuit 10. Pitch signal C is output only when count value E is reached.

FIG. 5 is a circuit diagram showing a specific configuration of the pitch period detection circuit 10 in the embodiment circuit of FIG. 4. In FIG. 5, a pitch period detection start signal S is supplied as an input signal to a D-type flip-flop 1. The Q output signal of this flip-flop 11 is supplied to another D-type flip-flop 12 as an input signal. A pitch signal C is supplied as a clock signal to both flip-flops 11 and 12 via an inverter 13. The Q output signal of the flip-flop 12 is supplied to an AND gate 14. This AND gate 14 is supplied with a reference clock signal, and the output signal of the AND gate 14 is (n+1
) is supplied as a count input signal to a binary counter 15 having a bit configuration. Further, the binary counter 15 is supplied with an output signal from the flip-flop 11 as a reset signal. The binary counter 15 (n
+1) bit count outputs Q0 to Qn are supplied to a coincidence determination circuit 16. This coincidence judgment circuit 16 receives the count output Q supplied from the binary counter 15. ~Qn
It has a storage section that stores three times of count values Q0 to Qn, and outputs the count values Q0 to Qn only when all three times of count values Q0 to Qn substantially match. In this coincidence determination circuit 16, the storage operation of the count outputs Q0 to Qn is controlled by the Q output signal of the flip-flop 12.

FIG. 6 is a timing chart of the pitch period detection circuit 10 shown in FIG. In the circuit shown in FIG. 5, when the pitch signal C is inverted from the 1" level to the "0" level after the pitch signal detection start signal S is raised to the "1" level, the Q output of the flip-flop 11 is synchronized with this. signal 1
7 is inverted from the 61" level to the "0" level. Since this signal 17 is supplied to the binary counter 15 as a reset signal, the binary counter 15 is released from the reset state and becomes ready for counting. At this time, The Q output signal 18 of the flip-flop 12 is kept at the "'1" level, and the AND gate 14 is kept open. The output signal 19 of the output 14 is shown as Q in FIG. , Q-work, . . . are counted sequentially as shown. While the binary counter 15 is counting the signal 19, the pitch signal C is "from 07 lebel"
When it returns to the '1' level and is further inverted to the '0' level, the flip-flop 12 synchronizes with this and the output signal 18 is first inverted from the e+I II level to the '0' level.This signal 18 becomes '0'. '' level, the D gate 14 is closed and the signal 19 is set to the ``0'' level, so that the counter 15 stops counting.Meanwhile, in synchronization with the signal 18, the coincidence judgment circuit 16 stores the count output Q.
6 is a non-infinite counter 1 corresponding to 1 pitch of signal C.
A count value of 5 will be stored. Similarly, the infinite counter 15 counts the reference clock signal for one pitch period of the signal C, and this count value is stored in the coincidence determination circuit 16. And the match determination circuit 16
When the count values for three times are stored, the match judgment circuit 1
6 compares the count values of these three times for coincidence, and only when the three times are almost the same, the count value is directly Q.

- Output Qn.

Note that if they do not match, the next three count values are compared for matching. Here, if the count value corresponding to one pitch in the binary counter 15 is, for example, about 40 in decimal notation, the count value when a malfunction occurs in the pitch signal C will be about half of that value, about 20. Therefore, if there is no large difference between the three count values, one of them is output.

The count value outputted from the coincidence determination circuit 16 in this manner is approximately proportional to one pitch of the pitch signal C, and this count value is supplied as the above-mentioned E to the pitch correction circuit 12.

FIG. 7 shows the pitch correction circuit 2 in the embodiment circuit shown in FIG. 4.
FIG. 2 is a circuit diagram showing a specific configuration of 0.

In FIG. 7, the count value Q from the match determination circuit 16
0 to Qn are supplied to the comparison circuit 21.

On the other hand, a binary counter 22 having an (n+1) bit configuration for counting the reference clock signal is also provided in the pitch correction circuit 20, and the count values Qo' to Qn' of this binary counter 220 are compared with the above. circuit 21
supplied to This comparison circuit 21 has two count values Q
Compare 0~Qn and QO'~Qn' and find the count value Q0~
The count error included in Qn, for example, the error due to the instability of the reference clock signal, and the error based on the opening/closing timing of the AND gate 14 (in this embodiment, this error is ±1) are calculated as the count values Q0 to Qn. 2 taken into account
When the value of Qo' to Qn' is in the range from 8 to 30, the output signal, ? s@'1'' level. This signal 23 is supplied to an AND gate 24. The pitch signal C is supplied to this AND dart 24, and the output signal 25 of this AND gate 24 is The signal is output to the circuit as a corrected pitch signal and is also supplied to the differentiating circuit 27 via the inverter 26.

This differentiating circuit 27 is composed of a capacitor, a resistor, and a diode, and differentiates the rising edge 9 of the inverter 26 to obtain "1".
The differential pulse 28 obtained here is supplied to the binary counter 22 as a reset signal.

FIG. 8 is a timing chart of the pitch correction circuit 2o shown in FIG. Note that this timing chart shows the case where the binary counters 15 and 22 each have 5 bits, and the count values are Q0' to Q4'. Assume now that the count value E (QO-Q4) output from the pitch period detection circuit 10 is 29 in decimal notation.

In FIG. 7, when the output signal 23 of the comparison circuit 21 is at the 11# level, the pitch signal C is inverted from the "'1" level to the "0" level.

When the signal C is inverted and becomes the "0" level, the output signal 25 of the melon gate 24 also falls to the "0" level.Subsequently, the output signal of the inverter 26 rises to the "1" level9, and this rising A differential pulse 28 is output from the differential circuit 27 in synchronization with 9 (see T in FIG. 8).
By inputting J pulse 8, binary counter 2
2 is reset, and all of its count values Qo' to Qa' are set to the "O" level. After this reset, the binary counter 22 receives the reference clock signals I)'t-i8, Q0/ to Q, / While the binary counter 22 is counting the reference clock signal Dt, the pitch signal C changes from the ``0'' level to the ``l'' level.
``The level returns.Then, the count value of the binary counter 15 is 28, which is one less than 29 given by Q0 to Q4.''
When it reaches, the output signal 23 of the comparison circuit 21 is set to the '1' level (T in FIG. 8).

At this time, the pitch signal C is at the "l" level, so the '1' level state of the pitch signal C remains unchanged at A.
The signal is output from the ND gate 24 as a signal 25. Then, when the pitch signal C falls to the "θ" level while the output signal 23 of the comparator circuit 2 is at the "1" level, A
The output signal 25 of the ND gate 24 also falls to the "0" level. In synchronization with the fall of this signal 25, the differentiating circuit 2
Since the differential pulse 28 is output from T3 in FIG.
), after which the binary counter 22 is reset again. In this way, if the fall of the pitch signal C occurs after 9 is the count value of the binary counter 22 but before 30, it is assumed that the timing of the fall of the pitch signal C at 9 is correct. is output from the AND gate 24 as it is. Also, the binary counter 22 is reset, and its count value Q, /~Qn
When all ' are set to the 0" level, the output signal 23 of the comparator circuit 21 is also set to the '0" level. The binary counter 22 then resumes counting the reference clock signal.

Assume that while the binary counter 22 is counting the signal, the pitch signal C inverts from the "1" level to the @0 level before the count value Q0'~Q,/ reaches 28. (lit, in Fig. 8). Note that, as a matter of course, at timing T4, which is before T, the pitch signal C is inverted to the 1'' level. This is due to the pitch signal C malfunctioning due to noise or the like.

At the timing T5, the count value of the binary counter 22 has not reached 28. For this reason, the comparison circuit 21
The output signal 23 of is left at the "o" level, and since the AND dirt 24 is closed, the change in pitch signal C at this time is not transmitted to the output signal 25 of ANDf-) 24. . That is, the binary counter 22
Even if the pitch signal C changes before the count value reaches 28, this change is not allowed to be output to the multi signal 25 by the AND dirt 24.

After this, the binary counter 220 count value becomes 2.
When the pitch signal C changes at the regular timing T6 of 9, this signal change is transmitted to the signal 25. In this way, only regular changes in the pitch signal C are transmitted to the signal 25, so that the signal 25 can be an accurate pitch signal free from malfunctions. In consideration of the count error in the binary counter 15, this pitch signal is allowed to vary by ±1 around the correct count value of 29.

FIG. 9 is a circuit diagram showing a specific configuration of the comparator circuit 21 in the circuit of FIG. 7. This circuit uses the count value Q o ”
``'Q4 and Q0/~Q*'t'' A subtracter 31 that subtracts each bit, and five subtracters to which subtraction outputs 80 to S4 of each bit of this subtracter 31 and a carry signal CARR are supplied. exclusive OR dart 32 and these f-to 3
a 5-bit half adder 33 to which the output signal of 2 is supplied as data and the carry signal CARR of the subtracter 31 is supplied as a carry signal;
The lower bit S of the output of 3. The NOR dart 34 is supplied with the outputs of S□ to S4 except for . In this circuit, count values Q0 to Q4 and Qo' to Q,
NOR dart 34 only when the absolute value of the difference between / is 1
The output signal of is set to 1'' level.

FIG. 10 is a circuit diagram showing another specific configuration of the pitch correction circuit 20. For example, if the pitch signal C is a vibraphone,
In the case of a sound with vibrato or portamento, such as a violin, the count values Q0 to Qn from the coincidence judgment circuit 16 are input to the comparison circuit 21 via the dart circuit 41, as shown in FIG. At the same time, the count values Q0' to Q and A of the binary counter 22 are held in a register 42, and the held value QO of this register 42 is
”~Q // is input to the comparison circuit 21 via the dart circuit 43.

In such a configuration, if the pitch signal C does not include vibrato or portamento, the dart circuit 41 is opened by the control signal 9, and the count values Q0 to Qn from the coincidence determination circuit 16 are input to the comparison circuit 21.

On the other hand, when pitch signal C is subjected to vibrato or portamento, the number ND of reference clock signals per pitch of signal C is, for example, 28°28, 28, 29
, 29 , 29 , 30 , 30 .

31, . . . Therefore, in this case, first the dart circuit 41 is opened and the count values Q0 to Qn from the match determination circuit 16 are input to the comparison circuit 21, and then the count value QO is counted by the binary counter 22 and held in the register 42. "~QI is input to the comparator circuit 21 via the dart circuit 43. In this way, accurate pitches can be extracted even for sounds whose pitches change sequentially.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, a case has been described in which the pitch period detection circuit 11 is configured as shown in FIG. 5, but this uses the original waveform as shown in A in FIG. After gold-plating conversion, fast Fourier scissors converter (FF
The frequency between peaks may be determined by counting the signal, or the waveform of A may be
After /D conversion, the peak frequency may be determined by counting the frequency of the signal using an autocorrelator.

Furthermore, the configuration of the pitch correction circuit 12 is also shown in FIGS.
It is not limited to what is shown in the figure, and various modifications are possible.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to remove the malfunction part of the fundamental wave period included in the input signal, so the fundamental wave layer AA can always be accurately obtained, and the fundamental wave period with high reliability can be obtained. An extraction circuit can be provided.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of the conventional circuit, Fig. 2 is a timing chart of the circuit shown in Fig. 1, Fig. 3 is a timing chart of the circuit shown in Fig. 1, and Fig. 4 is a block diagram of the fundamental wave period extraction circuit of the present invention. , FIG. 5 is a circuit diagram showing a specific configuration of a part of the circuit of FIG. 4, FIG. 6 is a timing chart of the circuit of FIG. 5, and FIG. 7 is a specific configuration of other parts of the circuit of FIG. 4. 8 is a timing chart of the circuit in FIG. 7, FIG. 9 is a circuit diagram showing a part of the circuit in FIG. 7 in more detail, and FIG.
This figure is a circuit diagram of a modification of the circuit of FIG. 7. 10...Pitch period detection circuit, 11.12...D-type flip 70 horn, 15...Prior counter, 16
... Match determination circuit, 20 ... Pitch correction circuit, 21
... Comparison circuit, 22 ... Noguinary counter, 27
... Differential circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 20 Nn=IQ Figure 3, Punishment book ■ system ``lI'LITL Concave dish tomo sokuhono;--
−−１□− Figure 4 0

Claims (1)

[Claims] An input signal including an arbitrary fundamental period and a reference clock signal are provided, and by counting the reference clock signals, a first signal corresponding to at least one fundamental period of the input signal is determined.
a first means for obtaining a count value of , and the input signal, a reference clock signal and a first count value are supplied, the reference clock signal is counted, and the value corresponds to the counting error of the reference clock signal in the first means. A fundamental wave period extraction circuit comprising: second means for permitting output of an input signal only when the first counted value is reached.