JPS60189890U - electronic time clock - Google Patents

electronic time clock

Info

Publication number
JPS60189890U
JPS60189890U JP7825184U JP7825184U JPS60189890U JP S60189890 U JPS60189890 U JP S60189890U JP 7825184 U JP7825184 U JP 7825184U JP 7825184 U JP7825184 U JP 7825184U JP S60189890 U JPS60189890 U JP S60189890U
Authority
JP
Japan
Prior art keywords
circuit
hour
time clock
code
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7825184U
Other languages
Japanese (ja)
Inventor
和彦 白鳥
Original Assignee
株式会社精工舎
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社精工舎 filed Critical 株式会社精工舎
Priority to JP7825184U priority Critical patent/JPS60189890U/en
Publication of JPS60189890U publication Critical patent/JPS60189890U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示した論理回路図、第2図
はウエストミンスターチャイムの5分ごとに演奏される
小節を示した説明図である。 ROM1〜ROM5・・・・・・記憶回路、DE・・・
・・・デコーダ、AC・・・・・・アドレスカウンタ、
CT・・・・・・カウンタ、A・・・・・・合成回路。
FIG. 1 is a logic circuit diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the measures played every five minutes of the Westminster chime. ROM1~ROM5...Memory circuit, DE...
...decoder, AC ...address counter,
CT...Counter, A...Synthesis circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の小節からなるメロディの所望の小節を正一時およ
び正時から1粉ごとに適宜選択して演奏する電子報時時
計において、上記メロディを各小節ごとに分割してPC
M変調したデータを記憶する記憶回路と、正時および正
時から1粉ごとにその時刻を表すコード出力を生じる出
力発生回路と、この出力発生回路からのコード出力によ
って上記−各記憶回路のいずれかを選択する選択回路と
、この選択回路で選択された記憶回路のデータを読み出
す制御回路と、読み出されたデータに基づいて楽音を合
成する合成回路とからなる電子報時時計。
In an electronic time clock that appropriately selects and plays desired measures of a melody consisting of a plurality of measures, one after the hour and one after the hour, the melody is divided into each measure and then played on a PC.
A memory circuit that stores M-modulated data, an output generation circuit that generates a code output representing the time on the hour and every hour starting from the hour, and a code output from this output generation circuit that outputs a code from each of the above-mentioned memory circuits. An electronic timepiece comprising a selection circuit that selects a memory circuit, a control circuit that reads data from a memory circuit selected by the selection circuit, and a synthesis circuit that synthesizes musical tones based on the read data.
JP7825184U 1984-05-28 1984-05-28 electronic time clock Pending JPS60189890U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7825184U JPS60189890U (en) 1984-05-28 1984-05-28 electronic time clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7825184U JPS60189890U (en) 1984-05-28 1984-05-28 electronic time clock

Publications (1)

Publication Number Publication Date
JPS60189890U true JPS60189890U (en) 1985-12-16

Family

ID=30622061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7825184U Pending JPS60189890U (en) 1984-05-28 1984-05-28 electronic time clock

Country Status (1)

Country Link
JP (1) JPS60189890U (en)

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