JPS6343514Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a musical tone generator for use in small electronic devices such as small electronic calculators and electronic watches.

[Prior art and its problems]

In recent years, small electronic calculators have been developed that associate each key with a musical scale such as "Do, Re, Mi..." and report the scale musical note corresponding to the operation key to ensure key input.
2. Description of the Related Art Small electronic devices having various musical tone generation functions, such as electronic clocks, which automatically report a predetermined melody tone at a preset time to make the user perceive the time, have been developed.

On the other hand, when a key is pressed, a sound source circuit of an electronic instrument that generates a sound source signal with a frequency corresponding to that key for the first time may be used, for example, from a memory circuit that stores frequency information of a plurality of sound source signals corresponding to the pressed key. When the frequency information is read out and stored in the temporary storage device, and a clock pulse is sent to a frequency divider connected in series in multiple stages, and the contents of this frequency divider match the frequency information stored in the temporary storage device over all bits. A so-called variable frequency division type sound source circuit is known that outputs a predetermined pulse signal to obtain a sound source signal of a frequency corresponding to a pressed key.

For example, when each musical tone is generated in a small electronic calculator using a temporary storage device, a frequency divider, a matching circuit, etc. in the manner described above, the frequency of the basic clock that drives the small electronic calculator is Since the frequency is low (about 10-100KHz), the frequency of the musical tone actually produced may be significantly different from the true musical tone frequency due to the frequency division of the basic clock mentioned above to create the musical tone signal. painful,
It also had some drawbacks, such as being unfavorable in terms of pitch education.

[Purpose of invention]

The present invention has been made in view of the above points, and it is an object of the present invention to provide a musical tone generating device that can accurately report each musical tone even if the basic clock frequency of the electronic device is sufficiently low. .

[Key points of the idea]

In order to achieve the above object, the present invention inputs and stores musical tone frequency information including correction data in a temporary storage circuit, and detects coincidence between musical tone frequency information excluding the correction data and the contents of a counter that is sequentially counted by clock pulses. and when a match signal is output, the counter is reset immediately or after a predetermined time delay according to the correction data, and
The other of the two-level voltages is selectively supplied to the sounding body.

〔Example〕

Hereinafter, an embodiment in which the musical tone generator of the present invention is applied to a small electronic calculator will be described in detail with reference to the drawings.

Figure 1 shows the overall configuration of a small electronic calculator.
Reference numeral 1 in the figure is a key input section, on which a numeric keypad, function keys, etc. are provided. Above key input section 1
The key operation signal is applied to the CPU (central processing unit) 2, and predetermined arithmetic processing is performed. i.e.
The CPU 2 has a control section 3 consisting of a ROM (read-only memory), etc., and according to a control signal CONT output from the control section 3, an arithmetic processing circuit 4 consisting of a RAM (random access memory), an adder circuit, etc. Then, arithmetic processing corresponding to the key operation is executed and transferred to a display device (not shown) for display.
Also, each note is 1 byte (8 bits) in CPU2.
It has a musical tone storage section 5 that stores musical tone frequency information (described later) of the configuration, and serially transmits musical tone frequency information corresponding to an address designation signal AD given from the control section 3 to a musical tone generation circuit 6 via an arithmetic processing circuit 4. Send. Furthermore, the CPU 2 is provided with a timing signal generating section 7 which supplies various timing signals in addition to the basic clocks φ ₁ and φ ₂ to the control section 3, arithmetic processing circuit 4, musical tone storage section 5, and musical tone generating circuit 6.

Thus, the musical tone frequency information given through the arithmetic processing circuit 4 is input in a serial state to the buffer register 8 (8-bit capacity) in the musical tone generating circuit 6, and the read clock φk output from the control section 3 The data is stored while being shifted sequentially.

For convenience of explanation, each bit of the buffer register 8 is assigned "1", "2", "4", and "4" from the right as shown in the diagram.
Weighting is done by "8", "16", "32", "64", and "128".

The contents of the buffer register 8 are output in parallel in synchronization with the basic clock φ ₂ , and the data with weighting "1" (correction data) is sent to the AND circuit 9.
10 first input terminals, respectively, and
It is applied to the first input terminal of the AND circuit 11 via the inverter 12, and weighted "2", "4", "8",
Data "16", "32", "64", and "128" are respectively applied to one input terminal of exclusive NOR circuits 13-19.

The other input terminals of the exclusive NOR circuits 13 to 19 are supplied with the contents of a counter 20 (7-bit capacity) that is sequentially counted up by the basic clock _φ1 (as shown for convenience, from the right, "1",
Weights are given as "2", "4", "8", "16", "32", and "64". ) are output and given in parallel in synchronization with the basic clock _φ2 . That is, while this counter 20 normally counts up from "0000000" to "1111111" by inputting the basic clock _φ1 , it is forcibly reset by the "1" output of the OR circuit 21 (described later) and all bit contents are counted up. becomes "0", so it can be used as a variable frequency divider that repeatedly counts from "0" to a predetermined value.

The outputs of the exclusive NOR circuits 13 to 19 are applied to each input terminal of the AND circuit 22, and the outputs thereof are applied to the second input terminals of the AND circuits 10 and 11, respectively, and are also delayed by one bit time by the delay circuit 23. and is applied to the second input terminal of the AND circuit 9.

Further, the output of a flip-flop circuit 24 (described later) is applied to the third input terminals of the AND circuits 9 and 10 via an inverter 25 or directly.
The output thereof is supplied to an OR circuit 21 together with the output of the AND circuit 11. And OR circuit 2
The output of 1 is applied to the AND circuits 26 and 27, and is also applied to the counter 20 as a reset signal as described above.

The AND circuit 26 is supplied with the basic clock φ ₁ in addition to the output of the OR circuit 21.
The output is given to the clock input terminal CK as a read signal of the flip-flop circuit 24, and the signal which is outputted from the output terminal 0 in synchronization with the basic clock φ ₂ and applied to the input terminal I via the inverter 25 is read. It's crowded. This flip-flop circuit 24
The output is directly applied to the AND circuits 10 and 27, inverted by the inverter 25, and applied to the input terminal I of the flip-flop circuit 24 and the AND circuit 9, respectively, and also to the AND circuit 28.

Furthermore, when the computer is set to the musical sound generation mode, the input terminals of the AND circuits 27 and 28 are supplied with a control signal _O1 from the control section 3, and are opened.
As a result, the output of the AND circuit 27 is supplied to the control section 3 to control the sounding time, and the AND circuit 28
The output is supplied to a sounding body 29 such as a piezoelectric buzzer to generate a sound.

Next, the operation of this embodiment will be explained. Figure 2 shows
True musical frequency of each scale, basic clock φ ₁ , φ ₂
The musical tone frequency information (setting value [n-2]) stored in the musical tone storage section 5 when the frequency of is set to 32768 Hz, for example, the Low bell voltage and High level applied to the sounding body 29 based on the musical tone frequency information. _The bit time of the voltage and the bit time [n] of one waveform (that is, the sum of the bit times of the low level voltage and the high level voltage ₎ are respectively shown. The following is a detailed explanation of the case in which musical tones are generated.

That is, as shown in FIG. 2, for example, musical tone F ₄
, just divide the basic clock (frequency 32768Hz) by a division ratio of 1/94 (note that when actually playing a musical tone,
The musical tone frequency pronounced as _F4 is 348.5...Hz. ). Therefore, musical tones are generated in association with key operation signals.
When generating _F4 , the control section 3 sends the musical tone storage section 5 a set value of "92" (the difference "2" from the above value "94" is the difference for the counter 20 to start counting from "0"). ) and sends the third address to the buffer register 8 via the arithmetic processing circuit 4.
Enter "01011100" as shown in Figure A and store it.

According to the basic clocks φ ₁ and φ ₂ shown in FIG. 4 a and b, the counter 20 sequentially performs a count-up operation from "0" (0000000) to "45" (0101101) as shown in FIG. 4 c. However, all the bits do not match the data stored in the 7 bits of weighting "2" to "128" of the buffer register 8 (i.e., "0101110"), and therefore, As shown, a "0" signal (Low level) is output from the output terminal 0 of the flip-flop circuit 24 and is supplied to the sounding element 29 via the AND circuit 28.

Then, the contents of counter 20 are "46"
(“0101110”), the AND circuit 22 generates 7
A "1" signal indicating a bit match is output and supplied to AND circuits 9, 10, and 11 (note that it is supplied to AND circuit 9 after being delayed by 1 bit via delay circuit 23). At this time, only the AND circuit 11,
It is opened by applying the content (correction data) "0" of the weighting "1" of the buffer register 8 via the inverter 12. Therefore, the output of the AND circuit 22 is transmitted via the AND circuit 11 to the OR circuit 21. (see Figure 4g). Then, the output of the OR circuit 21 opens the AND circuit 26,
Clock input terminal CK of flip-flop circuit 24
A basic clock φ ₁ is applied to the circuit as shown in FIG. 4h, and the output of the flip-flop circuit 24 is changed to “1” (High level) in synchronization with the next basic clock φ ₂ (see FIG. 4j).

Furthermore, the output of the OR circuit 21 is sent to the counter 20.
is given as a reset signal to the
Set it to "0" as shown in Figure c. Note that the output of the OR circuit 21 is also given to the AND circuit 27, but since the output of the flip-flop circuit 24 is "0", it maintains the "0" state as shown in FIG. 4i.

However, after the counter 20 is reset,
The count-up operation from "0" to "45" is performed again in the same manner as above. Then, when the content becomes "46" again, a "1" signal is output from the AND circuit 22 and applied to the AND circuits 9, 10, and 11, but this time as well, the "1" signal is output in the same way as above. It is supplied to the OR circuit 21 via the AND circuit 11.

The "1" output of the OR circuit 21 is given to the AND circuit 26, which supplies the basic clock _φ1 to the clock input terminal CK of the flip-flop circuit 24 as shown in FIG. It is inverted to "0" (Low level) as shown in j. Further, the output of the OR circuit 21 is given to the counter 20 as a reset signal, and the content of the counter 20 is set to "0" as shown in FIG. 4c.
Furthermore, the output of the OR circuit 21 is given to the AND circuit 27, which changes the output to "1" for one bit as shown in FIG.
(Reference) waveform creation has been completed.

The musical tone generating circuit 6 repeats the above operation a predetermined number of times (the number of operations is determined by the AND circuit 27 as described above).
It is controlled by counting the "1" outputs of. ), the sounding body 29 sounds the musical tone _F4 for a predetermined period of time.

Next, a case in which musical tone E ₄ is to be sounded will be explained.
In other words, as shown in Figure 2, it is understood that the basic clock (frequency 32768 Hz) can be divided by a division ratio of 1/99 (the musical tone frequency actually sounded as musical tone E ₄ is 330.9... Hz), but
For this purpose, it is necessary to make the time of the low level voltage and the time of the high level voltage supplied to the sounding element 29 different, for example, 50 bit time and 49 bit time, as shown in FIG.

Hereinafter, a detailed explanation will be given focusing on the above points.
In other words, as in the case of musical tone F ₄ , the control section 3
When the musical tone E ₄ is addressed to the musical tone storage section 5, the setting value "97" is inputted to the buffer register 8 via the arithmetic processing circuit 4 and is stored as "01100001" as shown in FIG. 3B. be done.

Then, the counter 20 reads the contents of the weights "2" to "128" of this buffer register 8 as "0110000".
Count up until it equals (48).
When the content of the counter 20 reaches the value "48", the AND circuit 22 outputs a "1" signal as shown in FIG. circuit 2
3 and is delayed by 1 bit. At this time, the third input terminal of the AND circuit 10 is connected to the output "0" (Low level) of the flip-flop circuit 24.
(see FIG. 5j) is given, and the data (correction data) "1" for the weighting "1" of the buffer memory 8 is inverted and given to the first input terminal of the AND circuit 11 via the inverter 12. Each is closed. On the other hand, the data (correction data) "1" for the weighting "1" of the buffer memory 8 is directly supplied to the first input terminal of the AND circuit 9, and the output "0" of the flip-flop circuit 24 is directly supplied to the third input terminal of the AND circuit 9. Therefore, the output of the AND circuit 22 is delayed by 1 bit and outputted from the AND circuit 9 (see FIG. 5e). “1” is given to the AND circuit 26, which converts the basic clock _φ1 to the flip-flop circuit 26.
4 (see Figure 5h). As a result, the output of the flip-flop circuit 24 changes from the "0" state (low level) that lasted for 50 bit times to the "1" state (high level) as shown in FIG.
level).

Further, the counter 20 is supplied with a reset signal from the OR circuit 21, and its content is forcibly changed from "49" to "0". Thereafter, the counter 20 sequentially counts up again, and when the content reaches "48", a "1" signal is output from the AND circuit 22 and applied to the AND circuits 9, 10, and 11, as shown in FIG. 5d. Ru. This time, since the output of the flip-flop circuit 24 is "1", only the AND circuit 10 is opened, and the output of the AND circuit 22 is passed through the AND circuit 10 to the OR circuit 21 as shown in FIG. given to.

Therefore, the basic clock _φ1 is supplied to the clock input terminal CK of the flip-flop circuit 24 via the AND circuit 26, and the clock input terminal CK of the flip-flop circuit 24 is
“1” output (High level) that continues for a bit time
is inverted as shown in FIG. 5j, and the waveform creation for one cycle (see FIG. 5k) is completed.

The other circuit operations for musical tone E ₄ are as follows:
This is the same as the case of musical tone _F4 , and other musical tones are generated in the same manner as described above, so the explanation thereof will be omitted.

As explained above, the musical tone generation circuit 6 of this embodiment is not only capable of generating musical tones when the frequency division ratio for the basic clocks φ ₁ and φ ₂ (frequency 32768 Hz) is 1/even number, but also capable of generating musical tone when the frequency division ratio is 1/even number. 1, the output of the flip-flop circuit 24 is in the "0" state (Low This is possible by extending the time in the "1" state (High level) by one bit time compared to the time in the "1" state (High level). Therefore, the basic clock φ ₁ ,
Even though φ ₂ is low, it is possible to bring the sound generation frequency very close to the true musical tone frequency, making it possible to make the error inaudible.

In the above embodiment, the time of the low level voltage applied to the sounding element 29 can be extended by one bit time as required compared to the time of the high level voltage. By directly applying the voltage and applying the output inverted by an inverter to the AND circuit 10, it is possible to extend the time of the high level voltage by one bit time compared to the time of the low level voltage.

Further, the circuit configuration of the musical tone generation circuit is not limited to the above embodiment, and the point is that the sound generating body 29 is caused to have a binary level voltage at different times depending on the correction data of the musical tone frequency information sent. It is sufficient if each of them is alternately supplied so that one cycle of the musical tone as a whole is an integral multiple of the period of the basic clock (in other words, the musical tone frequency is a value that is an integral fraction of the fundamental frequency).

Further, although the above embodiment has been described in connection with the case where the musical tone generating device of the present invention is applied to a small electronic calculator to generate musical tones in response to key input operations, it is possible to continuously store predetermined musical tone frequency information in musical tone memory in advance. It is also possible to generate a predetermined melody sound from the sounding body 29 by storing it in the unit 5 or microprogramming it in the ROM in the control unit 3, and the present invention can be applied to other small electronic devices such as electronic watches. It is also possible to apply musical tone generators such as
Of course, various modifications and applications can be made without departing from the gist of the present invention.

[Effect of idea]

As explained in detail above, the musical tone generating device of the present invention changes the frequency division ratio of the frequency divider according to the supplied musical tone frequency information, and applies each of the binary level voltages to the sounding body at different times within one cycle. By making it possible to supply and creating a musical tone for one cycle as a whole,
Even when the frequency of the basic clock that drives electronic equipment is low, it is possible to generate musical tones at a frequency very close to the true musical frequency. Therefore, the sound can be easily and accurately generated, which is also convenient for teaching pitch sense. It has certain advantages.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, with FIG. 1 showing the circuit configuration of a small electronic calculator, and FIG.
Figures 3A and 3B show the frequency, bit time, and setting values of the musical tones to be sounded, respectively, and the musical tone frequency information that is input to the buffer register 8 and stored when generating the musical tones F ₄ and E ₄ is shown. The figures shown in FIGS. 4 and 5 are timing charts when musical tones F ₄ and E ₄ are generated. 3... Control section, 5... Musical tone storage section, 6... Musical tone generation circuit, 7... Timing signal generation section, 8...
Buffer register, 9 to 11...AND circuit, 1
3 to 19...exclusive NOR circuit, 20...counter, 22...AND circuit, 23...delay circuit, 2
4...Flip-flop circuit, 25...Inverter, 29...Sounding body.

Claims (1)

[Scope of utility model registration request] a clock pulse generating means for generating a clock pulse having a predetermined frequency; a temporary storage circuit for inputting and storing frequency division information for the frequency of the clock pulse set based on the 1/2 period of the musical tone frequency corresponding to each scale; Stores correction information specifying whether or not to correct the period obtained by the 1/2 period frequency division information according to the difference between the frequency obtained by dividing the clock pulse and the actual musical tone frequency. a correction information storage circuit; a counter that sequentially counts when the clock pulse is applied; and a detection circuit that detects coincidence between the contents of the counter and frequency division information stored in the temporary storage circuit and outputs a coincidence signal. , a delay circuit that delays the coincidence signal output from the detection circuit by one clock pulse, and inverts the output every time the coincidence signal output from the detection circuit or the coincidence signal delayed by the delay circuit is applied. If there is no correction information, all matching signals are applied directly to the inversion circuit, and if there is correction information, the signal is applied directly or via the delay circuit depending on the output state of the inversion circuit. a logic circuit for applying a match signal to the inverting circuit; a reset circuit for resetting the counter each time a match signal or a match signal delayed by the delay circuit is applied to the inverting circuit; A musical tone generating device characterized by comprising a sounding body that is driven accordingly.