JPS60189549A - System for controlling main storage device in data processing system - Google Patents

Abstract

PURPOSE:To prevent the assignment of page frames from being collected on the same main storage device unit and to improve the parallel processing of main storage devices by providing a page frame control means and two temporary storage means. CONSTITUTION:When a process requests the assignment of a page frame in a main storage device controlling method using a data processing system having plural processors and main storage devices, the contents of a register 9 are stored in a storage part corresponding to a page frame finally assigned out of at least one page frame assigned on the basis of a register 12 and a pointer 10. The contents stored in the storage part corresponding to the finally assigned page frame are stored in the final storage parts of a register 9 and a page frame control table 8. Consequently, the assignment of page frames can be prevented from being collected on the same main storage device unit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a management method (prior art) for managing page frame allocation of a main storage device in a data processing system. Conventionally, in a data processing system having multiple processors and a main memory device, the main memory device that is commonly accessed by the multiple processes has a multi-bank configuration (the main memory device is divided into multiple parts (banks) that can be accessed independently). > VC divided configuration) is adopted.If such a configuration is adopted, the main storage device as a whole will not be accessed redundantly due to the plurality of gross storage devices, and the utilization efficiency can be improved. Generally, in data processing systems, the maximum main memory capacity that can be accessed by the processor is not implemented in a single main memory device, but is implemented by dividing it into multiple main memory units. This is to make it possible to create various product models by combining various storage units and processors, and to construct the optimal system configuration that matches the processing power expected of the data processing system.Main storage unit It is also an independent main memory device with a multi-bank configuration, and different main memory units are accessed independently by a plurality of processes.

Conventionally, in the main memory management method of this glazed data processing system, the allocation of page frames to each processor was
In this case, the processing is performed for the required number of page frames in ascending order of the main storage device address, that is, the page frame number. Therefore, accesses from the processor are concentrated in a specific main memory unit, and the frequency with which the processor accesses the same bank within this specific main memory unit increases, resulting in interleaving in the main memory unit with a multi-bank configuration. This has the disadvantage that the effect of the mechanism is not utilized and the processing performance of the data processing system is reduced.

(Object of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a main storage management system in which page frame allocation is not concentrated in a specific main storage unit.

(Structure of the Invention) The system of the present invention includes a plurality of processing devices that execute a plurality of processes and a plurality of main storage devices each having a plurality of banks that can be accessed independently from each process of the plurality of processing devices. In a main storage management method in a data processing system including a main storage device consisting of a main storage device consisting of a plurality of page frames, a page frame is provided in a one-to-one correspondence with each page frame of the main memory device that is logically divided into a plurality of page frames. The management information storage section is provided with a page frame management means storing a first pointer for specifying the next storage section in each storage section, and a page frame management means corresponding to the plurality of page frames that are not allocated to the plurality of processes. A second storage unit that specifies the first storage unit among the plurality of storage units.
and at least one second temporary storage means that is allocated to the process when the process requests allocation of a page frame; When requesting page frame allocation, the contents of the first temporary storage means are transferred to the second temporary storage means.
and the storage section corresponding to the last page frame allocated among the at least one page frame allocated based on the first pointer according to this request, and Before storage is performed, the answer stored in the memory section corresponding to the last assigned page frame is stored in the first temporary storage means and at the end of the page frame management means. 0 (
Examples) Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an embodiment of a data processing system to which the method of the present invention is applied includes main memory units 1a and 1b having a multi-bank configuration constituting the main memory, and a plurality of main memory units 1a and 1b that can execute a plurality of processes. It consists of an arithmetic processing device 3, a plurality of channel control devices 4, and a system control device 2 connected to each of these devices and units. Furthermore, it can be independently accessed by several channel controllers 4, and the paging mechanism allows multiple processing units! [3 and the two main memory units from the channel controllers 4] la and 1b can be accessed with consecutive addresses.

FIG. 2(a) is a diagram showing the internal configuration of two main memory units 1a and lb that constitute the main memory.Each main memory unit 1a and 1b has 8 banks, each with 32 banks. It has a configuration that is logically divided into page frames (K=1024).

Such a main memory is accessed by a main memory address (word) as shown in FIG.

In Figure 3, the address word consists of 26 bits from bit 0 to bit 25, where bit 0 = -bit 25 indicates the address in the main memory, bit 0 indicates the number of the main memory unit, and bits 1 to 25 indicate the main memory unit number. 25 indicates an address within the main memory unit, bits 1 to 15 indicate a page frame number, bits 16 to 25 indicate an address within the page frame, and bits 22 to 24 indicate a bank number. By using address words with such a structure, it is possible to access the main storage device simultaneously from multiple arithmetic processing units 3 and multiple channel control units 4 independently and simultaneously if the bank numbers are different even if the page frame number is the same. However, if the main storage unit number is different, it can be accessed in the same way. again,
Referring to FIG. 2(a), there is a page frame management table 8 having page frame management areas (entries) 5 provided in one-to-one correspondence for all page frames included in main storage units (la and 1b). It is stored in a predetermined portion of the main memory. In this embodiment, a pointer 6 to the next entry is set in each entry 5. Further, it is assumed that all pointer values in the pointer are expressed by page frame numbers.

Initialization of the page frame management table 8 will be explained with reference to FIG. 2(b). The pointer value 1oVC in the register 9 provided in the processing device 3 is set to the page frame number O, and the page frame number (-1 to 64) is set as the pointer value of the chain pointer 6 of the entry 5 corresponding to the page frame number 0.
) is set, and the page frame number 1 is set as the pointer value of the chain pointer 6 of the entry 5 corresponding to the page frame number (-1 to 64). The page frame number (-2 to 64) to 32K are set as the pointer value of the chain pointer 6 of each entry 5 corresponding to the page frame number (3).
Page frame numbers (-1 to 32) to 2 are set as the pointer values of the chain pointers 6 of each entry 5 corresponding to 2 +1) to (64 to -2), and the page frame number 3
The page frame number 0 is set as the pointer value of the chain pointer 6 of each entry 5 corresponding to 2K. In this way, for the main storage unit 1aic, the page frame number is set in ascending order of the page frame number, and for the main storage unit 1b, the page frame number is set as the pointer value of the chain pointer 6. Entries corresponding to page frames included in different main storage units are connected in a chain in descending numbers. Arithmetic processing unit 3 and daughter channel control unit [
When a process on 114 issues a request to allocate a page frame in the main memory, the processing device 3
The allocation program stored in advance in a or 1b is executed. Based on this program, the processing device 3 traces the requested page from the entry indicated by the pointer in the register 9.

FIG. 2C is a diagram showing an example in which a request for allocating four page frames is issued from a certain task to the initialized page frame management table 8, and the allocation is performed. Processing device 3 sets pointer value 10 in register 9 to processing device 3.
It is set in the register 12 provided in the page frame, and also in the entry 16 corresponding to the last allocated page frame.

The register 9 is set with the page frame number corresponding to the first entry (IJ) of the page frame management table 11 that has been reduced by this allocation, and the same page frame number is also set in the last entry 18 of this management table 11. is set. With this pressure, page frame numbers 0, 1, . (
Four page frames (-2) and (-1) are assigned to 64. Subsequent allocations to other processes are similarly done by setting the pointer value in register 9 to the register allocated to the other process, and setting the register to the entry corresponding to the last allocated page frame. This is done by setting the page frame number corresponding to the first entry in the last entry 18 of 9.

Next, to return the already allocated page frame from the process, set the contents of the register corresponding to the process to the entry 18 of the management table, and return the page frame that was last allocated to this process. This is done by setting the pointer value of register 9 to the corresponding entry.

Even after the return, the chain pointer in the entry that forms the page frame management table can be accessed by the owner.
Accesses are not concentrated on a specific main storage unit.

In this embodiment, only one pointer is set for each frame, but multiple pointers may be set. For example, set the pointer so that the entries corresponding to the page frames are connected in a chain for the main storage unit )la in descending order of the page frame number, and for the main memory unit )lb in the ascending order of the page frame number. can do.

Further, in this embodiment, a page frame number is used as the pointer value, but other address information or the like may be used.

(Effects of the Invention) Since the frequency of access conflicts from a plurality of processors to the data processing system can be reduced, there is an effect that the parallel processing performance for the main memory of the data processing system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a data processing system to which the method of the present invention is applied, FIGS. 2(a) to (c) are diagrams for explaining the present invention in detail, and FIG. It is a figure showing the address candy to be used. In the figure, 1... Main storage unit, 2.
...System control device, 3 ... Arithmetic processing device, 4 ... Channel control device, 5 ...
・Entry, 6...Chain pointer, 8...
...Page frame management table, 9.12...
register.

Claims (1)

[Claims] Data processing that includes a plurality of processing units that execute a plurality of processes and a main memory unit that includes a plurality of main memory units each having a plurality of banks that can be independently accessed by each process of the plurality of processing units. In the main storage management method in the system, a page frame management information storage section is provided in one-to-one correspondence with each page frame of the main storage device that is logically divided into a plurality of page frames. A page frame management means that stores a first pointer that specifies a storage section, and a first storage section among the plurality of storage sections corresponding to the plurality of page frames that are not allocated to the plurality of processes. at least one second temporary storage means that is allocated to the process when the process requests allocation of a page frame; requests allocation of a page frame, the contents of the first temporary storage means are transferred to the second temporary storage means and at least one page allocated based on the first pointer is requested by the user. The page frame is stored in the storage unit corresponding to the page frame allocated last among the frames, and before this storage is performed, the page frame is stored in the storage unit corresponding to the page frame allocated last. A main storage device management method in a data processing system, characterized in that the content stored in the first temporary storage means and the last storage section of the page frame management means are stored.