JPS6018944A - Lead frame for semiconductor integrated circuit device - Google Patents
Lead frame for semiconductor integrated circuit deviceInfo
- Publication number
- JPS6018944A JPS6018944A JP58126734A JP12673483A JPS6018944A JP S6018944 A JPS6018944 A JP S6018944A JP 58126734 A JP58126734 A JP 58126734A JP 12673483 A JP12673483 A JP 12673483A JP S6018944 A JPS6018944 A JP S6018944A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- leads
- sections
- stitch
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/4917—Crossed wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、本来は完全に分離される事が望ましい二つの
配線におい゛Ｃ共通インピーダンス部分を低減すること
の出来る半導体集積回路装置のり−ドフレームに関する
。[Detailed description of the invention] [Technical field to which the invention pertains] The present invention provides a semiconductor integrated circuit device board that can reduce a common impedance portion between two wiring lines that are originally desirable to be completely separated. Regarding frames.
半導体集積回路装置（以下ＩＣと称す）のベレットにお
ける金属薄膜による配線において、特定の端子の配線を
二つに分離する必要のある事カニしばしばあり、特にグ
ランド配線にその例力玉多い。In the wiring of metal thin films in the pellets of semiconductor integrated circuit devices (hereinafter referred to as IC), it is often necessary to separate the wiring of a particular terminal into two, and this is especially common in ground wiring.
例えば電力増幅用ＩＣの信号系のグランドと出力系のグ
ランドとでは、これらが共通であると、出力系のグラン
ドを流れる大きな電流力玉、布線インピーダンスにより
入力信号に応じた電圧となり信号系のグランドを振る事
により入力となつ°で帰還し、歪率を悪化する。For example, if the signal system ground and the output system ground of a power amplification IC are common, a large current flows through the output system ground, and wiring impedance causes a voltage corresponding to the input signal to be generated in the signal system. By shaking the ground, it returns at an angle equal to the input, worsening the distortion rate.
父、別の例としては、ステレオ用等で二つの増幅器を有
するものでは、各々のグランドを共通すると、出力信号
が互いに入力に帰還し相互干渉を生じ、いわゆるクロス
トークを悪化させる。As another example, if a stereo amplifier or the like has two amplifiers, and they all share a common ground, the output signals will be fed back to the input, causing mutual interference and worsening so-called crosstalk.
従来、一般にこれらの対策としては各々分離した配線と
し°Ｃいる。Conventionally, as a countermeasure for these problems, separate wiring has been generally used.
第１図は従来のリードフレームを用いたＩＣの一例の要
部平面図である。FIG. 1 is a plan view of essential parts of an example of an IC using a conventional lead frame.
図においてアイランド１１２にベレット１１３が搭載さ
れており、１０１〜１１１はリードである。ベレット１
１３上で分離の゛必要な配線１１４と配線１１５とは共
通ボンディングパット１１６から共通となりリード１０
６の金族細線１１８によってリード１０６と結線されて
いる。In the figure, a pellet 113 is mounted on an island 112, and 101 to 111 are leads. Beret 1
The wiring 114 and the wiring 115 that need to be separated on the lead 13 are connected to a common bonding pad 116 and are connected to the lead 10.
It is connected to the lead 106 by a metal group thin wire 118 of No. 6.
従って分離の必要な配線１１４と配＃ｊ１１１５とは共
通ポンディングパッド１１６以降は共通インピーダンス
となってしまい歪率悪化、配線の引きまわしによるベレ
ット面積の増加、クロストーク悪化の問題を生ずる。Therefore, the wiring 114 and wiring #j 1115, which need to be separated, have a common impedance after the common bonding pad 116, resulting in problems such as deterioration of distortion rate, increase in bullet area due to routing of wiring, and deterioration of crosstalk.
この問題の対策としてポンディングパッドを二つ分離し
て設は一つのリードに別々の金属細線により結線する方
法が考えられる。A possible solution to this problem is to separate two bonding pads and connect them to one lead using separate thin metal wires.
第２図は従来のリードフレームを用いたＩＣの他の例の
平面図である。このＩＣは第１図の円の部分に於てポン
ディングパッド１１７を分離して設けた例であり、各々
のパッドから別々に金属細線１１８によりリード１０６
に結線されている。FIG. 2 is a plan view of another example of an IC using a conventional lead frame. This IC is an example in which the bonding pads 117 are separately provided in the circle part of FIG.
is connected to.
これにより金属細線の分の共通インピーダンスは削除で
きるが、リード１０６は共通インピーダンスは削除でき
るが、リード１０６は共通インピーダンスであり、また
分離したポンディングパッド１１７はいずれもリード１
０６の近くに設ける必要があるため、配線を引きまわす
必要を生じ、パターン設計を繁雑にし、更にその引き１
わし配線の分だけベレット面積を余分に必要とするとい
う多くの欠点がある。As a result, the common impedance of the thin metal wire can be deleted, but the common impedance of the lead 106 can be deleted, but the lead 106 has a common impedance, and the separated bonding pads 117 are both
Since it needs to be installed near 06, it becomes necessary to route the wiring, making the pattern design complicated, and furthermore, the wiring 1
It has many drawbacks, including the need for extra bullet area for the wires.
当然のこととして、リードを１本州やし、その機能の端
子（前記例ではグランド端子）を２本とすれば完全に分
離できるが、その分だけ端子を多く必要とするので、多
機能化、小型化の妨げとなり、コストも上るという欠点
がある。Naturally, if you use one lead and two terminals for that function (the ground terminal in the example above), you can completely separate them, but that requires more terminals, so it is better to have multiple functions. This has the disadvantage of hindering miniaturization and increasing costs.
本発明の目的は以上の欠点を除去し、リードの本数を余
分に必要とすることなく、またベレットの配線の引きま
わしもすることもなく、リードの共通インピーダンス部
を極力少なくする事ができる半導体集積回路装置のリー
ドフレームを提供することにある。The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to provide a semiconductor that can reduce the common impedance portion of the leads as much as possible without requiring an extra number of leads or routing the wires of the bullet. An object of the present invention is to provide a lead frame for an integrated circuit device.
本発明の半導体集積回路装置のリードフレームはベレッ
トのポンディングパッドとボンディング結線するステッ
チ部が他のリードのステッチ部より低く位置するよう段
差が設けられ、前記ステッチ部は対向するベレットの一
辺に沿うようＬ字又はＴ字型構造をなし、かつステッチ
部側よりのスリットにより中途まで分割されているリー
ドを少なくと一つ含んで構成される。In the lead frame of the semiconductor integrated circuit device of the present invention, a step is provided so that the stitched portion of the bullet that connects the bonding pad with the bonding wire is located lower than the stitched portion of other leads, and the stitched portion is along one side of the opposing pellet. The lead has an L-shaped or T-shaped structure, and includes at least one lead that is divided halfway by a slit from the stitching side.
第３図は本発明の第１の実施例の平面図である。 FIG. 3 is a plan view of the first embodiment of the invention.
図において１０１〜１０５および２０６並びに１０７〜
１１１は何れもリードである。以上のリードのうち２０
６は本発明の要部であるリードで、このリードはベレッ
トのポンディングパッドとの結線領域であるステッチ部
が外部引出部に対しＴ字型に形成されており、前記ステ
ッチ部はステッチ部側よりのスリット１００により２０
６ｂ、２０６ｃの２つの部分に分割されている。In the figure, 101-105 and 206 and 107-
All 111 are leads. 20 of these leads
Reference numeral 6 denotes a lead which is a main part of the present invention, and this lead has a stitched part which is a connection area with the pounding pad of the bullet and is formed in a T-shape with respect to the external drawer part, and the stitched part is on the stitched part side. More slits 100 by 20
It is divided into two parts, 6b and 206c.
また、この２つに分割されたステッチ部は他のリード、
すなわち１０１〜１０５，１０７〜１１１の位置する面
より低くなるよう加工されている。In addition, the stitch part divided into two parts can be used for other leads,
That is, it is processed to be lower than the planes 101 to 105 and 107 to 111 are located.
第４図は第３図に示すリード２０６の斜視図である。FIG. 4 is a perspective view of the lead 206 shown in FIG. 3.
図より明らかなようにリード２０６は２０６ｄで上下に
区画されており、ステッチ部２０６ ｂ 、 ２０６
ｃは他のリードより低い位置に２０６８の部分は他のリ
ードと同一面に位置し２０６ｄ部分で段差を形成してい
る。またＴ型の横棒に相当するステッチ部は配線の便を
はかりベレットの取付部であるアイランドの一辺に沿う
よう配置されリードフレームを構成し“Ｃいる。As is clear from the figure, the lead 206 is divided into upper and lower parts 206d, and stitched parts 206b, 206
A portion 2068 is located on the same surface as the other leads, and a step is formed at a portion 206d. In addition, the stitched portion corresponding to the horizontal bar of the T-shape is arranged along one side of the island, which is the mounting portion of the bullet, for convenience of wiring, and forms a lead frame.
第５図は第３図に示した第１の実施例のリードフレーム
を用いた半導体集積回路装置の平面図である。図におい
て１０１〜１１１はリードであり、２０６は本発明の主
要部のリードである。また１１２はアイランドであり、
このアイランド上にはベレッ）１１３が固定されている
。FIG. 5 is a plan view of a semiconductor integrated circuit device using the lead frame of the first embodiment shown in FIG. In the figure, 101 to 111 are leads, and 206 is a lead that is the main part of the present invention. Also, 112 is an island,
A beret 113 is fixed on this island.
リード２０６はステッチ部を含むリードのベレット側部
２０６ｂ 、２０６Ｃ部は折り曲げ加工によって２０６
の外部リード側部２０６ａ並びに他のリードより低くす
っている。更にリード２０６のステッチ部側はスリット
１００により分離され、各々リード１０５，１０７をく
ぐりぬけ左右に延びているので、通常ペレットの左右に
離れ−Ｃしまう信号系のグランドと出力係のグランド、
もしくは左右のチャンネルのグランド等に代表される配
線１１４と配線１１５を第１図、杷２図のように引きま
わす必要がなくなり、ボンディング線１１７゜１１８に
より左右にのびたステッチ部に容易に結線できる。The lead 206 is formed by bending the bellet side parts 206b and 206C of the lead including the stitched part.
The outer lead side portion 206a of the lead is lower than the other leads. Furthermore, the stitched part side of the lead 206 is separated by the slit 100 and extends to the left and right through the leads 105 and 107, respectively, so that the signal system ground and the output ground, which are usually separated to the left and right of the pellet, are connected to each other.
Alternatively, it is no longer necessary to route the wiring 114 and wiring 115, which are represented by the grounds of the left and right channels, as shown in FIGS.
またリード２０６はパッケージの外部まで二つに分離さ
れているためリード部の共通インピーダンスが極力低減
されている。Further, since the lead 206 is separated into two parts to the outside of the package, the common impedance of the lead portion is reduced as much as possible.
このように本実施例によれは、リードの本数を余分にす
ることなく、マたペレットの配線のひきまわしをするこ
ともなく、リードの共通インピーダンスを低減すること
ができる。As described above, according to this embodiment, the common impedance of the leads can be reduced without increasing the number of leads and without having to route the wiring of the pellet.
更にリード２０６の金属細線１１８とリード１０４の金
属細線１２０のように互いに段差のあるところでは交差
した結線も可能となる。Further, in places where there is a step difference between the thin metal wires 118 of the leads 206 and the thin metal wires 120 of the leads 104, it is possible to connect the wires so that they intersect.
第６瞼は本発明の第２の実施例の平面図、第７図は第６
図に示すリード３０６の斜視図である。The sixth eyelid is a plan view of the second embodiment of the present invention, and FIG.
FIG. 3 is a perspective view of the lead 306 shown in the figure.
第６図におい”ｒ、１０３〜１０５，１０７゜１０８は
通常のリードであり、３０６力二本発明の要部であるリ
ードである。リード３０６は全体としてＴ字型構造をな
し、横棒に相当するステッチ部は３０６１：、、３０６
Ｃの２部分よりなりスリット１００により分割されでい
る。In Fig. 6, "r", 103-105, 107° 108 is a normal lead, and 306 is a lead that is the main part of the present invention. The lead 306 has a T-shaped structure as a whole, and has a horizontal bar. The corresponding stitch part is 3061:,,306
It is divided into two parts by a slit 100.
−また、第７図に示すこうに、リード３０６の３０６ｂ
、３０６ｃ部分は他のリードより低い位置となるよう
他のリードと同一平面にある３０６８部の間に３０６ｄ
に（目当する段差が設けられている。また本実施例では
段着部以降のリード部は幅が狭く形成されている。すな
わちスリットによる分割した構造のリードで第３図のり
一ド２０６のようにリード幅を他のリードと同じ面”ま
で広くすると隣のリードとの間隔が狭くなり問題となる
。特にリード間隔が小さい場合は対策をとる必要を生ず
る。-Also, as shown in FIG.
, 306d between the 3068 parts which are on the same plane as other leads so that the 306c part is at a lower position than the other leads.
In this embodiment, the lead portion after the stepped portion is formed to have a narrow width.In other words, the lead has a structure divided by slits, and the lead portion 206 in FIG. If the lead width is widened to the same plane as the other leads, the distance between adjacent leads becomes narrower, causing a problem. Especially when the lead distance is small, countermeasures must be taken.
ところが第７図でｄ、新り−まげ加工て似くされたリー
ドの幅広部と隣のリードとの間隔をＷｌとし他のリード
と同一面のリード部と隣のリードとの間隔をＷ２とする
と低い位置のみ幅広のため上部はＷ２で、低部はＷｌで
あるが実質的には段差によりリード間隔が保たれるので
リード間隔の狭いリードフレームにも本発明を容易に実
施できる。However, in Fig. 7, d, the distance between the wide part of the new lead and the adjacent lead is Wl, and the distance between the lead part on the same surface as other leads and the adjacent lead is W2. Then, since only the lower part is wide, the upper part is W2 and the lower part is W1, but since the lead spacing is substantially maintained by the step, the present invention can be easily applied to a lead frame with a narrow lead spacing.
第８図は本発明の第３の実施例を用いた半導体集積回路
装置の平面図である。FIG. 8 is a plan view of a semiconductor integrated circuit device using a third embodiment of the present invention.
図において１０１〜１ｏ５，１０７〜１１ｏは同一平面
にあるリード４０６及び４１１は本発明の要部であるリ
ードを示す。また１１２はアイランド、１１３はペレッ
トである。In the figure, 101 to 1o5 and 107 to 11o are on the same plane.Leads 406 and 411 are the main parts of the present invention. Further, 112 is an island, and 113 is a pellet.
また本発明の要部であるリード４０６はＴ字の左側にの
けず必要がないのでステッチ部４０６ｂ 。Also, since the lead 406, which is the main part of the present invention, is not needed because it is placed on the left side of the T-shape, the stitched part 406b is used.
４０６ｃはリードの外側部４０６ａとＬ字形に構成し、
ステッチ側よりスリット１ｏｏにより２分割されている
。このような構造においても４０６ｂ 、４０６ｃに対
応するペレットのポンディングパッドが１３０゜１３１
の位置にあるので容易に本発明の効果を得ることができ
る。406c is configured in an L-shape with the outer part 406a of the lead,
It is divided into two by slit 1oo from the stitch side. Even in this structure, the pellet pounding pads corresponding to 406b and 406c are 130°131
, the effects of the present invention can be easily obtained.
またリード４１１はアイランド１１２の端に位置してい
るがＬ字型のリードで４１１０と１３３のパッドを、４
１１ｂと１３２のパッドを金属細線１２１および１２０
で容易に結線することができ、またスリット１００によ
シリードが分割されているので共通インピーダンスを大
幅に低減することができる。Also, the lead 411 is located at the end of the island 112, and is an L-shaped lead that connects pads 4110 and 133 to 4
Pads 11b and 132 are connected to thin metal wires 121 and 120.
Since the series leads are divided by the slit 100, the common impedance can be significantly reduced.
第９図は本発明の第４の実施例の平面図である。FIG. 9 is a plan view of a fourth embodiment of the invention.
第９図の実施例においても、リード５０６は５０６ ａ
＋ ５０６ ｂ ＋ ５０６ ｃの各部よりな９５０
６ｄ部と５０６ｂ 、 ５０６ｃ部はＴ字型をなすと共
にスリット部１００により分割されている。また５０６
ｂ 。Also in the embodiment of FIG. 9, the lead 506 is 506 a
950 from each part of + 506 b + 506 c
The 6d portion, 506b, and 506c form a T-shape and are divided by a slit portion 100. Also 506
b.
５０６Ｃ部は５０６ｄ部より低く位置されている。この
リードフレームでは５０６ｂ 、５０６ｃ部と通常の隣
接するリード１０４，１０５，１０７，１０８とは上下
関係で重なっていない。しかし５０６ｂ 。The 506C section is located lower than the 506d section. In this lead frame, portions 506b and 506c do not overlap the normal adjacent leads 104, 105, 107, and 108 in a vertical relationship. But 506b.
５０６Ｃ部は５０６ｄ部と段差が設けられて、低い位置
にあるのでボンディング細線による結線に問題が生ずる
ことがなく本発明の効果が得られる。Since the portion 506C has a step difference from the portion 506d and is located at a lower position, the effects of the present invention can be obtained without causing any problems in connection with the thin bonding wire.
以上詳細に説明したように、本発明によれば、リードの
本数を余分に必要とすることなく、またベレットの配線
を引きまわすこともなく、リードの共通インピーダンス
部を極力少なくする事ができ、従って、歪率の悪化、ペ
レット面積の増大。As explained in detail above, according to the present invention, the common impedance portion of the leads can be minimized without requiring an extra number of leads or routing the wires of the bullet. Therefore, the strain rate deteriorates and the pellet area increases.
クロストークの悪化等の問題を除去できる半導体集積回
路装置のリードフレームが得られる。A lead frame for a semiconductor integrated circuit device that can eliminate problems such as deterioration of crosstalk can be obtained.
第１図は従来のリードフレームを用いたＩＣの一例の平
面図、第２図は従来のリードフレームを用いたＩＣの他
の例の平面図、第３図は本発明の第１の実施例の平面図
、第４図は第３図に示すリード２０６の斜視図、第５図
は本発明の第１の実施例のリードフレームを用いたＩＣ
の平面図、第６図は本発明の第２の実施例の平面図、第
７図は第６図に示すリード３０６の斜視図、第８図は本
発明の第３の実施例を用いたＩＣの平面図、第９図は本
発明の第４の実施例の平面図で゛ある。
１００パ・°°スリット、１０１〜１１１・・・・・・
リード、１１２パ°・・・アイランド、１１３・・・・
・・ペレット、１１４．１１５・・・・・・配線、１１
６・・・・・・共通ポンディングパッド、１１７・・・
・・・分離したポンディングパッド、１１８，１１９，
１２０，１２１・・・・・・金属細線、２０６．３０６
．４０６．５０６・・・・・・本発明によるリード、２
０６ａ 、３０６ａ ＋４０６ａ 。
５０６ａ・・・・・・本発明によるリードの外側部、２
０６ｂ。
２０６ｃ、３０６ｂ、３０６ｃ、４０６ｂ、４０６ｃ、
５０６ｂ 。
５０６Ｃ・・・本発明によるリードのステッチ部、２０
６ｄ、３０６ｄ・・・・・本発明のリードの段差部。
第１図Fig. 1 is a plan view of an example of an IC using a conventional lead frame, Fig. 2 is a plan view of another example of an IC using a conventional lead frame, and Fig. 3 is a plan view of an example of an IC using a conventional lead frame. 4 is a perspective view of the lead 206 shown in FIG. 3, and FIG. 5 is an IC using the lead frame of the first embodiment of the present invention.
6 is a plan view of the second embodiment of the present invention, FIG. 7 is a perspective view of the lead 306 shown in FIG. 6, and FIG. 8 is a plan view of the third embodiment of the present invention. FIG. 9, a plan view of the IC, is a plan view of a fourth embodiment of the present invention. 100 pa/°° slit, 101~111...
Lead, 112 pa°...Island, 113...
...Pellet, 114.115...Wiring, 11
6...Common pounding pad, 117...
... Separated pounding pad, 118, 119,
120,121...Thin metal wire, 206.306
．． 406.506...Lead according to the present invention, 2
06a, 306a +406a. 506a... Outer part of lead according to the present invention, 2
06b. 206c, 306b, 306c, 406b, 406c,
506b. 506C... Stitched portion of lead according to the present invention, 20
6d, 306d...Stepped portions of the lead of the present invention. Figure 1
Claims (1)
他のリードのステッチ部より低く位置するよう段差が設
けられ、前記ステッチ部は対向するベレットの一辺に沿
うようＬ字又はＴ字型構造をなし、かつステッチ部側よ
りのスリットにより中途まで分割されているリードを少
なくと一つ含むことを特徴とする半導体集積回路装置の
リードフレーム。A step is provided so that the stitched portion connecting to the pounding pad of the bullet is located lower than the stitched portion of other leads, and the stitched portion has an L-shaped or T-shaped structure along one side of the opposing bullet, and A lead frame for a semiconductor integrated circuit device, comprising at least one lead that is divided halfway by a slit from the stitching side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58126734A JPS6018944A (en) | 1983-07-12 | 1983-07-12 | Lead frame for semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58126734A JPS6018944A (en) | 1983-07-12 | 1983-07-12 | Lead frame for semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6018944A true JPS6018944A (en) | 1985-01-31 |
Family
ID=14942563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58126734A Pending JPS6018944A (en) | 1983-07-12 | 1983-07-12 | Lead frame for semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6018944A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62134255U (en) * | 1986-02-17 | 1987-08-24 | ||
| US4979016A (en) * | 1988-05-16 | 1990-12-18 | Dallas Semiconductor Corporation | Split lead package |
| US5065224A (en) * | 1986-06-30 | 1991-11-12 | Fairchild Semiconductor Corporation | Low noise integrated circuit and leadframe |
| US5173621A (en) * | 1986-06-30 | 1992-12-22 | Fairchild Semiconductor Corporation | Transceiver with isolated power rails for ground bounce reduction |
| EP1746650A2 (en) | 2005-07-22 | 2007-01-24 | Marvell World Trade Ltd | Packaging for high speed integrated circuits |
| US7638870B2 (en) | 2005-07-22 | 2009-12-29 | Marvell International Ltd. | Packaging for high speed integrated circuits |
-
1983
- 1983-07-12 JP JP58126734A patent/JPS6018944A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62134255U (en) * | 1986-02-17 | 1987-08-24 | ||
| US5065224A (en) * | 1986-06-30 | 1991-11-12 | Fairchild Semiconductor Corporation | Low noise integrated circuit and leadframe |
| US5173621A (en) * | 1986-06-30 | 1992-12-22 | Fairchild Semiconductor Corporation | Transceiver with isolated power rails for ground bounce reduction |
| US4979016A (en) * | 1988-05-16 | 1990-12-18 | Dallas Semiconductor Corporation | Split lead package |
| EP1746650A2 (en) | 2005-07-22 | 2007-01-24 | Marvell World Trade Ltd | Packaging for high speed integrated circuits |
| EP1746650A3 (en) * | 2005-07-22 | 2008-09-10 | Marvell World Trade Ltd | Packaging for high speed integrated circuits |
| US7638870B2 (en) | 2005-07-22 | 2009-12-29 | Marvell International Ltd. | Packaging for high speed integrated circuits |
| US7884451B2 (en) | 2005-07-22 | 2011-02-08 | Marvell World Trade Ltd. | Packaging for high speed integrated circuits |
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