JPS6018933A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6018933A JPS6018933A JP58126705A JP12670583A JPS6018933A JP S6018933 A JPS6018933 A JP S6018933A JP 58126705 A JP58126705 A JP 58126705A JP 12670583 A JP12670583 A JP 12670583A JP S6018933 A JPS6018933 A JP S6018933A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- film
- fusing
- cutting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に関し、%に冗長ビットを有する半
導体メモリ装置の10グラマプル素子を含む半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a 10-gram element of a semiconductor memory device having 10% redundant bits.
近年、半導体メモリ装置は急速VCC大量量化進展して
きた。しズハし、チップ当りの記憶容量が増加するに伴
い製造歩留ケ実用的水準以上(保つことが次第【困難に
なりつつあり、冗長ビットを設は歩留同上を計る冗長構
成技術が採用さhつつある。冗長構成技術に使用される
プログラマブル索子には大きく分けてヒユーズを用いる
ものとレーザにより配線全溶断するものとがある。In recent years, semiconductor memory devices have rapidly increased in mass VCC. However, as the memory capacity per chip increases, it is becoming increasingly difficult to maintain manufacturing yields above a practical level, and redundant configuration technology is being adopted to increase yield by setting redundant bits. Programmable cables used in redundant configuration technology are broadly divided into those that use fuses and those that completely fuse the wiring using a laser.
従来使用される前記冗長s敗技術に使用されるプログラ
マブル素子について図面を用いて説明する0
第1図は従来の7−ロゲラマブル素子−例の平tm図で
ある。A programmable element used in the conventional redundancy loss technique will be described with reference to the drawings. FIG. 1 is a flat-tm diagram of an example of a conventional seven-log programmable element.
半導体基lfiにプログラム素子を形成し、その上を第
1の絶縁膜で覆う。この上に多結晶シリコンでプログラ
ム素子の活性領域rCコンタクト部3で啜続する溶断用
配線lを設ける0溶断用配線の上に第2の絶縁膜を設け
、窓あけし、コンタクト部3で咲続するアルミニウム配
線2を設ける。4は拡散領域である。A program element is formed on the semiconductor substrate lfi, and the program element is covered with a first insulating film. On top of this, a fusing wiring l made of polycrystalline silicon is provided that continues at the active region rC of the program element. A continuous aluminum wiring 2 is provided. 4 is a diffusion region.
溶断用配線lの溶断はレーザ元にニジ多結晶シリコンを
加熱して溶断する。しかし、レーザ九がトランジスタの
ゲートrC用いらt7る多結晶シリコン、拡散領域等に
照射されるとこれらのものは損傷を受け、リーク等の原
因となるため、溶断用配線lと拡散領域4等の間屹l″
r:第1図に示すようなマージンt1が必要であった。The wire 1 for fusing is cut by heating rainbow polycrystalline silicon using a laser source. However, if the laser beam is irradiated onto the transistor gate rC, polycrystalline silicon, diffusion region, etc., these things will be damaged and cause leakage, etc. The space between
r: A margin t1 as shown in FIG. 1 was required.
このマージンt1ぼレーザ光を照射する時の位置合せ精
度によって決まる。This margin t1 is determined by the positioning accuracy when irradiating the laser beam.
上記理由に、!ニジレーザ九で溶断することを予定した
プログラマブル索子を含む半導体チップは面積が大さく
なる欠点があった。また、面積を小さくするためVCレ
ーザ照射の位置合せ精度?高めると装置が高価となり、
スループットが落ちる欠点があった。For the above reasons! Semiconductor chips containing programmable cables that were intended to be fused with the Niji Laser 9 had the disadvantage of being large in area. Also, what is the alignment accuracy of VC laser irradiation to reduce the area? The higher the value, the more expensive the equipment becomes.
The drawback was that throughput decreased.
本発明は上記欠点全除去し、マージンを小さくすること
ができ、半導体メモリ装置のプログラマブル索子の面積
を小ざ<シ、従って半導体チップ面積を小さくした半導
体装置全提供するものである0
本発明の半導体装置は、′+群外体基板丸形5yきねた
プログラム素子と、前記半纏外基板上10設けられた第
1の絶縁膜上に多結晶半導体で形成され前記プログラム
素子の活性領域(陸続する溶断用配線と、該溶断用配線
?覆う第2の絶縁膜と、該第2の絶縁膜上に前記溶断用
配線の溶断部を少なくとも囲む金属膜とを含んで構成さ
れる。The present invention eliminates all of the above-mentioned drawbacks, reduces the margin, reduces the area of the programmable cable of the semiconductor memory device, and therefore provides a semiconductor device with a reduced semiconductor chip area. The semiconductor device includes a program element having a circular shape 5y on a round outer substrate, and an active region of the program element ( It is configured to include a land-connected fusing wiring, a second insulating film covering the fusing wiring, and a metal film surrounding at least the fusing portion of the fusing wiring on the second insulating film.
仄【、本発明の実施例について図面を用いて説明する。[Embodiments of the present invention will be described with reference to the drawings.
第2図は本発明の一笑7II!191の平面図である。Figure 2 shows the present invention's Issho 7II! 191 is a plan view of FIG.
半導体基板にプログラム素子音形成し、その上に第1の
絶縁膜を形成する。プログラム素子の活性領域i’v吸
続陸続溶断用配線lを多結晶ノリコンで形成し、その上
に第2の絶縁膜を設ける。窓あけしてアルミニウム配線
2とコンタクト部3で陸続する。この実施例では第2の
絶縁j漠の上に溶断用配線lの溶断部を少なくとも囲む
ように金属膜5を設ける。金属膜5にアルミニウム?用
いると、アルミニウム配線3と同時に形成でさるという
利点がある0溶断8を囲むのであるから、溶1”fr
=ttの上IIcは金属膜5全形成しない。即ち窓6
fj:6けておく。A program element sound is formed on a semiconductor substrate, and a first insulating film is formed thereon. The active region i'v of the program element is formed of a polycrystalline glue l for intermittent fusing, and a second insulating film is provided thereon. A window is opened and the aluminum wiring 2 and the contact part 3 are connected to each other. In this embodiment, a metal film 5 is provided on the second insulating layer so as to at least surround the fusing portion of the fusing wiring l. Aluminum in metal film 5? When used, it surrounds the melt 8 which has the advantage of being formed at the same time as the aluminum wiring 3.
= On IIc of tt, the metal film 5 is not entirely formed. i.e. window 6
fj: Leave 6 digits.
レーザ光で多結晶シリコンの溶断用配線ii熱照射ると
さ、レーザ光は溶断用配線lのみならずその周辺も照射
するが、金属膜5を照射したレーザ光に金属膜5で反射
され、金属膜5の下部(設けられた拡散領域あるいはゲ
ート電極等に用いらhる多結晶シリコンに影響をお工ば
ざない。これに多結晶シリコンはレーザ光を極めて吸収
しやすいため溶断しやすく金属膜はレーザ光の大部分を
反射させるため、多結晶シリコン全十分溶断させるエネ
ルギーでレーザ光を照射させても金属膜5に損傷ケ与え
ることはないためである。従って、多結晶シリコンの溶
断用配線lと拡散領域4とのマージン12u非常に小さ
くすることができる。またレーザ光の位置合せ精度が高
い高価な装置も不要とな・ジ、スループットも上げるこ
とができる。When the polycrystalline silicon fusing wiring ii is thermally irradiated with a laser beam, the laser beam irradiates not only the fusing wiring 1 but also its surroundings, but the laser beam that irradiates the metal film 5 is reflected by the metal film 5, Do not affect the polycrystalline silicon used for the lower part of the metal film 5 (the diffusion region provided or the gate electrode, etc.). Polycrystalline silicon absorbs laser light extremely easily, so it is easy to melt and melt the metal. This is because the film reflects most of the laser light, so even if the laser light is irradiated with enough energy to melt all of the polycrystalline silicon, the metal film 5 will not be damaged. The margin 12u between the wiring 1 and the diffusion region 4 can be made very small.Also, there is no need for an expensive device with high alignment accuracy of the laser beam, and the throughput can also be increased.
以上詳細に説明したように、本発明によれば、−半導体
メモリ装置のプログラマブル素子を含み、該プログラマ
ブル索子の面積を小さくすることがでさ、従って半導体
チップの面積を小さくした半導体装置が得られるのでそ
の効果は大さい。As explained in detail above, according to the present invention, - it is possible to reduce the area of the programmable element of the semiconductor memory device, and thus to obtain a semiconductor device with a reduced area of the semiconductor chip; The effect is great.
第1図は従来のプログラマブル索子の一例の平面図、第
2図は本発明の一実施例の平面図である。
l・・・溶断用配線、2・・・アルミニウム配線、3・
・・コンタクト部、4・・・拡散領域、訃・・金属膜、
6・・・窓。FIG. 1 is a plan view of an example of a conventional programmable cord, and FIG. 2 is a plan view of an embodiment of the present invention. l... Wiring for fusing, 2... Aluminum wiring, 3.
...Contact part, 4...Diffusion region, End...Metal film,
6...window.
Claims (1)
基板上に設けられた第1の絶縁膜上流多結晶半導体で形
成された前記プログラム素子の活性領域cB続する溶断
用配線と、該溶断用配線を覆う第2の絶縁J漠と、該第
2の絶縁膜上に前記溶断用配線の溶断WPSk少なくと
も囲む金属膜とを含むこと全特徴とする半導体装置nA round semiconductor substrate, a grogram element, a fusing wiring connected to an active region cB of the program element formed of a polycrystalline semiconductor upstream of a first insulating film provided on the semiconductor substrate, and the fusing wiring. and a metal film surrounding at least the fusing wire of the fusing wiring on the second insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58126705A JPS6018933A (en) | 1983-07-12 | 1983-07-12 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58126705A JPS6018933A (en) | 1983-07-12 | 1983-07-12 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6018933A true JPS6018933A (en) | 1985-01-31 |
Family
ID=14941810
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58126705A Pending JPS6018933A (en) | 1983-07-12 | 1983-07-12 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6018933A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4826785A (en) * | 1987-01-27 | 1989-05-02 | Inmos Corporation | Metallic fuse with optically absorptive layer |
US6516719B2 (en) | 1996-08-22 | 2003-02-11 | Monarch Marking Systems, Inc. | Hand-held labeler |
-
1983
- 1983-07-12 JP JP58126705A patent/JPS6018933A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4826785A (en) * | 1987-01-27 | 1989-05-02 | Inmos Corporation | Metallic fuse with optically absorptive layer |
US6516719B2 (en) | 1996-08-22 | 2003-02-11 | Monarch Marking Systems, Inc. | Hand-held labeler |
US6619204B2 (en) | 1996-08-22 | 2003-09-16 | Paxar Americas, Inc. | Hand-held labeler |
US6766842B1 (en) | 1996-08-22 | 2004-07-27 | Paxar Americas, Inc. | Hand-held labeler |
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