JPS60187997A - Read-only memory - Google Patents

Abstract

PURPOSE:To enhance the operation speed and reduce the power consumption by providing FETs, whose gates, drains, and sources are connected to a precharge line, sources of FETs constituting a ROM, and the second power supply terminal respectively, in the transverse stacked ROM. CONSTITUTION:N type FETs 6 whose gates, drains, and sources are connected to a precharge line PG, drains of N type FETs 3 constituting a dynamic ROM, and the first power source earth respectively are turned off in the first half of the precharge period when P type FETs 4 are turned on to precharge output signal lines 00-03. Consequently, a current from a power source VDD to the earth is not flowed in this period, and decoder outputs D0-D3 are not inhibited. As the result, the operation speed is improved and the power consumption is reduced in the transverse stacked dynamic ROM.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a horizontally stacked ROMcD structure.

(Prior Art) Recently, integrated circuit devices are rapidly becoming more highly integrated. Programming method 1' (currently changing) is aimed at reducing the number of elements from a circuit that conventionally consisted of only random logic.

For this reason, in order to store the zlog gram, v RU M r
It is also required that c is also L times faster and the f-memory capacity is larger. Therefore, due to these requirements, a horizontally stacked ROM, which has a structure in which transistors are stacked horizontally, is not used. This is because the horizontally stacked A transistors are connected in parallel, so the speed is fast, whereas the speed is slow because the A transistors are connected in parallel.This becomes noticeable when the ROM increases to 6% stiffness.

Conventionally, this type of cross-over R (an example of JM is shown in Figure 1). 2 bits of AI, its decoded signal rJ
DO to D3 are 4 bits, and this is input to R (JM, and the final output is 4 bits). A precharge signal gPG is input to 0 or UM, which has a structure in which M(Jf9 transistor is formed), and 1 recharge of R(JM is performed.The timing diagram shown in Fig. 2) 01 recharge signal yGa has a period T?, and is connected to each output line at +T1 before the period T. /b7 P-channel transistor 4 for recharging is turned on, and the output signal OO~(7 is recharged to J3. (l#1'(Naru.

) and during the second half T2 F output signal 00~u a rc
Specific power appears. Input data a 0 that changes synchronously with this period Trc Therefore, the decoded signal DO~D3% 0 ('I! No. Do-Dar) that changes synchronously with this period Trc
[Only the intended signal is 'l#'9 and all other a@
0". Therefore, if there is a transistor on the intended signal line in 80M, the transistor turns on and T
Change the output line which is precharged to @l# during the period I to 10" during the period T2. Conversely, if the output line rl without a transistor [m1 remains precharged,
m and na/bo this way, this R (JMrI″″0
If "1" is desired, transistor A is provided, and if "1" is desired, transistor A is not provided.

However, with this configuration, the P-channel transistor 4 for 1 recharge attached to each output line is turned on during the period Tl, but during this period the σtecode output M DO~
Since the target signal in D3 is 1'l#, R
(In JMQ, this signal line [6 channel transistors turn on by 3%, and a current flows between VDD and ground. Generally, the on-resistance of the transistor is about a few tens to several hundred η). Therefore, the current a flowing at the moment of TI is several tens [μA] per output, and if the output is 100, the output will be several (mA) (yzr), IEL (J
The larger the MO size is, the more pronounced the 0 characteristic rc becomes. This P-channel transistor for precharging 4
The rff load response is large and one recharge is not required during the period of Tl, and the flow is actually made noticeably larger as the flow is made more difficult. The power supply wiring must be carefully designed to withstand this N current, and due to the resistance of the power supply wiring, the line voltage actually applied to each transistor 3°4 may be lowered, causing malfunctions. Also, the biggest drawback is consumption [which leads to an increase in mud]. An example of a conventional impeller that has been improved in this respect is shown in FIG. 3, and its timing diagram is shown in FIG. In this example, the and-
Road 5? For a period of 1"l, the decode output Do-D3 is '
l"lc is prohibited. 0 In addition, during the period of Tt, between rlrvDD and ground, there is no flow of current. ?-1” to 10”1
It takes 6 hours to change from 0# to At", which reduces the operating speed of R(JM. Therefore, this signal line vi
- It means that it will be prohibited for a period of time. This speed-up [on the other hand, it is not suitable for the recent high-speed R (JM 90 is not suitable).

(Aim of the invention) Aim of the invention a above-mentioned drawbacks? and the operation speed is fast.
In order to reduce current consumption, bR (JM?) is intended to be provided and constructed. The recharge signal line, the first and second power supply terminals, and the source 11r and the 11th
ZJ' [gate to source terminal all 1 recharge signal H, drain to output line and)
．． +field effect transistor, source' to second power supply terminal, gate Fr7 recharge signal line to drain iRL
Source rC of the field effect transistor that constitutes the IM cell
It is composed of a plurality of m2 field effect transistors connected in a row.

(Example) Next, the present invention will be explained in more detail with reference to the entire diagram of blood vessels.An example of the present invention? Is that timing chart in Figure 5?
OR shown in Figure 6 (JM contents a) Same as the conventional example,
H channel horizontal loading type, N channel type MO8F
A transistor 3 is formed at a predetermined portion between the source signal line and the output line.

The major feature in Fig. 5 is that the source of the 1.0M cell (consisting of rrN-channel MO8 transistor 3) is not directly connected to the ground, but is connected to the -gate t-1 recharge signal line PG by the source keground I'. channel type M (connected to ground through six J8 transistors. In addition to this transistor group, L
Also during Tl period of 91 recharge, r between VDD and ground
cll, no current flows 9 and te code signal D
θ ~ 1) There is no prohibition during 3aTt, and there is no delay in conveying te, -me. 6o Also, why don't you add it here? 6N channel pM (J8 transistor 6σ Since the charge held in the stray capacitance is simply discharged, a large transistor A is not required. Therefore, the increase in chip area due to the addition of this transistor is not so large because it is possible to create an RCL by bundling several source signal lines 2 together. In particular, the speed does not decrease at the same time as the wasteful consumption [flow a disappears.This method has the effect of increasing the speed while reducing the consumption flow.

[Brief explanation of the drawing]

Figure 1 a shows an example of the conventional υR (3M configuration), W, 2
Figure a is the timing chart. FIG. 3a is a diagram showing another conventional ROM0M configuration example, and FIG. 4a is its timing chart. Figure 5a is a diagram of an embodiment of R (JM) of the present invention, and Figure 6a is its timing chart.
...N-channel type M (J8 transistor) in huM cell, 4...P-channel type M (JS) transistor, 5...AND circuit, 6...N-channel type M (J8 transistor)
8 transistors, AO, Al...input signal, DO, D
I, D2゜D3... Tecoded output signal, (JO
, (Jl, (J2゜03...output signal, PG...precharge signal line twist 1 figure Δθ Al ρθ θ/ 02 θ3 false 3 figure 1 ″41 ゛Aρ Al θρ θl ri2 ρ3

Claims (1)

[Claims] ROM cell wm5!1. Dynamic type R in which field effect transistors are stacked horizontally (in JMRC, the charge signal line, the 2nd V power supply terminal, and the 1st Q power supply terminal of the source circuit) are connected to the power supply terminal of the gate circuit 1. Recharge m-qic drain? output line, )t(a plurality of first field effect transistors connected to the drain of the field effect transistor constituting the JM cell 1r, and the source 1f)
r, to the second power supply terminal, to the gate, to the recharge gIg line, to the drain? above)L(JN cell?rmg
D4) A plurality of second (1) field effect transistors that failed to serve as the source of the field effect transistor? Including? Special memory for bladder removal.