JPS60187972A - Digital signal detecting circuit - Google Patents

Abstract

PURPOSE:To detect surely digital signals to reduce the error rate of reproduced signals by setting an input signal to a prescribed level when preceding and succeeding contents of an input signal between plural reference levels have specific patterns. CONSTITUTION:An RF signal from a terminal 41 is compared with reference levels in comparing circuits 42 and 43, and respective comparison outputs are shifted in a register 47 through an EOR circuit 46 by clocks from a terminal 50, and simultaneously, the output of the circuit 43 is shifted in a register 48. Contents of FFs 471-473 constituting the register 47 correspond to those of FFs 481-483 constituting the register 48 with respect to time. If the RF signal is between reference levels and level discrimination is unsettled, the pattern is discriminated on a basis of contents of FFs 485, 484, 482, and 481, and contents of the FF483 are outputted as they are in case of characteristic (a), but contents of the FF483 are outputted after inversion in case of characteristic (b). As the result, signals without errors are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal detection circuit suitable for use in recording and reproducing digital signals.

BACKGROUND TECHNOLOGY AND PROBLEMS Generally speaking, when a digital signal is recorded on a recording medium and recorded in 11 sips, it is difficult to avoid errors in one particular bit at a particular location in a particular pattern. This is a major factor in degrading the error rate.

FIG. 1 schematically shows a conventional reproduction system, in which a signal reproduced from a recording medium such as a magnetic tape (not shown) by a magnetic head 11 is sent to a reciprocating amplifier (2) and an equalizer (3). is supplied to the reproducing circuit (4) via the equalizer (3) output (RF multiplied signal), and the digital signal "II" ( or “I”).

A determination of "L" (or "θ") is made, and after the required 4R processing, the signal is output to the output terminal (6).

For example, if we consider a recording pattern that includes a large amount of direct current components, such as shown in Figure 2A, when digital data of such a pattern is recorded on a magnetic tape, it will appear as shown in Figure 2B. The signal has boronization characteristics. Soshi-ζ
When the signal is reproduced from the magnetic tape on which the digital signal is recorded in this manner through the head (1) and supplied to the reproduction amplifier (2), the output side has a signal as shown in Figure 2 C. A good signal can be obtained. This signal is then supplied to the equalizer (3) and is equalized into a waveform as shown in the second figure, resulting in an RF multiplied signal. Then, this RF multiplied signal is compared with a predetermined reference level, for example, O level, in the reproduction circuit (4) and extracted by the clock pulses supplied from the clock reproduction circuit (5) from time t1 to t6. )
Error data different from the recording pattern in Figure 2A, as shown in Figure 2E, is output on the output side of the If the DC component cannot be sufficiently regenerated due to an intervention, etc., as shown in the second diagram, the level gradually decreases as time passes, and for example, at time t5, the level may exceed the original 0 level (reference level). This is because the level should be lower than this θ level, so the reproducing circuit (4) makes an error in the determination and treats "H" as "L'" and outputs it.

Furthermore, in the case of a recording pattern with a high frequency, the output is small, so the waveform is rounded and the same error as described above occurs. That is, for example, when a high frequency recording pattern as shown in FIG. 3A is changed, such digital data is recorded on the magnetic tape with magnetization characteristics as shown in FIG. 3B. Then, play this to Nol' (It).
2) as shown in Figure 3C, and further equalizer (
3), an RF multiplied signal with a distorted waveform as shown in the third diagram will be obtained. When judged by such an RF double signal reproducing circuit (4), since this signal does not cross the O level, the time t3, which should originally be judged as “I,” is changed to “I]”.
As a result, erroneous data different from the recording pattern of FIG. 3A is output to the output side of the reproduction IR (41).

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a digital signal detection circuit that can reliably detect and reproduce digital information.

Summary of the Invention The present invention has a plurality of reference levels, a comparison means for comparing these reference levels and a human input signal, a storage means for storing the output of the comparison means, and the above-mentioned information based on the contents of the storage means. and discriminating means for determining the pattern of the human input signal, and is configured to set the human input signal between the reference levels to a predetermined level when the content before and after the input signal between the reference levels listed in -1- is a specific pattern. ing.

With the 1u configuration, the present invention enables reliable detection of digital signals and reproduction of digital signals with a low error rate.

Hereinafter, one embodiment of the present invention will be described in detail based on FIGS. 4 to 10.

FIG. 4 shows a diagram of the basic principle of this invention. In the same figure, (21) is an input terminal to which an RF signal passed through the equalizer described above is supplied;
) is supplied to one input terminal of a plurality of (+1)l comparison circuits (22) and (23) serving as ratio axis means. The other input terminals of the comparison circuits (22) and (23) are supplied with signals serving as reference levels of the terminals (24) and (25), respectively. These standard levels are set to different values depending on the residence. Note that this reference level is determined so that the current voltage is the midpoint, one is a little higher than this, and the other is a little lower than this.

On the output side of the comparator circuits (22) and (23), there is a shift register (2) consisting of a plurality of flip-flop circuits (26+) to (26n) as described above.
6) and flip-flop circuits (271) to (27n
) A shift register (27) consisting of For example, if I'' is below the reference level, a signal of 1. Shifted by .

In addition, the output of the flip-flop circuit (26+) ''□ (2fin) of the shift register (26) is supplied to the distribution circuit 118 (2!1>), and the output of the flip-flop circuit R& ( 27+),
(272) and (27n-+).

The output of (27n) is fed to another circuit (29) of 111.

In the discrimination circuit (29), the shift register (26) and (
From the contents of 27), R supplied from input terminal (21)
The F-fold signal pattern is determined, and the output signal thereof is supplied (It) to the switch circuit (30) as a control signal.

Further, to each switch circuit (30), for example, the output of the flip-flop circuit II (273) near the middle of the shift register (27) is supplied as data information to the switch circuit (30). In the case of an n-stage shift register, it is preferable to take out this data information from the n/2 stage.

Further, this data information may be taken out from near the middle of the shift register (26).

The discriminating circuit (29) determines the content before and after approximately the middle of the shift register (27) side, for example, flip-flow knob rotation II.
Solitub flop circuits (27n (2
7n-1), (272), and (27t) have a specific pattern such as H” or “I” as shown in FIG. 2 or 3.
, ′ is a pattern that is difficult to distinguish and prone to errors,
The output signal controls the switch circuit (30) so that the contents of the ``ζ flimp flow circuit IM (273)''
It is determined whether to set the signal to "H" or "L", and output a digital signal with an error-free pattern to the output terminal (31) side.

That is, in the pattern shown in FIG. 2 or 3, the base Y1
An error occurred because the bit that should have been "■1" became "17" when the level was off, but in such a case, if the reference level was slightly changed by 1. Become. Therefore, in this invention, instead of shifting the reference level by 1-, the RF (“H”, “L” of the
The purpose of this method is to make a judgment based on the data contents before and after the judgment, and extract the signal itself that is determined to be at a certain level after the judgment as a digital signal.

FIG. 5 shows the first embodiment of the present invention, in which there are two reference levels.

(41) is an input terminal to which the RF multiplied signal is supplied through the initial stage, and the RF multiplied signal comparison circuit (42) and Hi (43
) is supplied to one input terminal of the terminal, and the other input terminal is compared with a reference level supplied from terminals (44) and (45), respectively. In this case, for example, a signal of a positive reference level is supplied from a terminal (44) and a signal of a negative reference level is supplied from a terminal (45), centered around the midpoint (0 level) of the power supply 'Ichikawa'.

The respective outputs of the 11 comparison products (42) and (43) are sent to, for example, flip-flop circuits (471) to (173) via an exclusive OR (hereinafter referred to as EOR) circuit (46).
) is supplied to the input side of a shift register (47). Further, the output of the comparator circuit (43) is supplied to the input terminal of a shift register (48) consisting of, for example, solid flop circuits (481) to (48s). Then ζ is the output of the shift register (47), that is, the flip-flop circuit (
The output of 473) is supplied to the separate circuit (49) and the flip-flop circuits (48+), (4B2) and (484) of the shift register (48).
485) are supplied to the discrimination circuit (49).

Note that a clock pulse for shifting is supplied from a clock terminal (50) to each flip-flop circuit of the shift registers (47) and (48).

Also, there is an E ORl! between the shift register (48) solipf [1 knob circuit (483) and (484)]. -! l M
g (5]) is provided, the output of the flip-flop 1 circuit (483) is supplied (Iu) to the - force input terminal of this EOR1 path (51), and the other input terminal is supplied with t'11. Separately, the output of 1//f <49) is supplied, and the EOR circuit (
The output of 51) is supplied to the flip-flop 1 circuit (484). Then, the output terminal (52) is taken out from the output side of the flip-flop circuit II (485) on the output side of the shift register (4th day).

Next, the operation of this circuit will be explained with reference to FIGS. 6 and 7. In addition, in each H, ζI, o is 0 lehel, I, 1
1I and 2 are each ratio φ121F! The reference level at I I-δ (42) and (43), the arrow represents the application time of the Ell 4J extraction pulse.

Is it now RI from the input terminal A (old)? When Hakugo (j) is supplied, it is compared with each reference level in comparison circuits (42) and (43), and both comparison circuits (42) and (43) are Output is EOR
1 path (46) in a sequential shift register (47), and at the same time the output of the comparator circuit (43) is sequentially shifted in a shift register (48). Therefore, the flip-flop circuit (4'71) of the shift register (47)
) to (473) correspond in time to the contents of flip-flop circuit W11 (48t to (483)) of the shift register (48), respectively.

Also, the output of the EOR1 path (46) becomes "I(" only when the outputs of the comparison circuits (42) and (43) are different, that is, when the RF multiplied signal level is between the reference levels L1 and I2. , otherwise it is L''.

-, the output of the flip-flop circuit (473) is "1".
1", at this time the output of the corresponding flip-flop circuit (483) should also be "H", but there is a large possibility that the determination is ambiguous. Therefore, The discrimination circuit (49) determines the contents of the data before and after the output of the flip-flop circuit (483), that is, the flip-flop circuit (48) of the shift register (4th).
s ) , (4B4 ) and (482) , (4B+
), it is determined that the output of the solve flop circuit (483) should be corrected.

For example, flip-flops vj4(48.,), (4
84).

The outputs of (4B2) and (48t) are “'H”
, “11”.

If "L" and "I2" do not form a typical pattern with curve d in Figure 6, then "111 Separate 1/A (49) will generate a debt of L" on its output side? 1; Shi, this is C.
Solitub flop times I/8 (483) output "H"
” with the ICOR circuit (5I) (next 1)
41 (supply) to each solid flop circuit (411q).

In addition, at this time, Sorisopufu l:l,,pu times 11! δ
(The output of 4fh + is l, regardless of whether it is "I4" or "°L".

In addition, flip-flop 1" tube circuit (4B+; ), (4
84).

The outputs of (482) and (481) are “l-” and “1
, Pa.

If the curves in Figure 6 for "H" and H" do not form a pattern that looks like a gap, the discrimination 11 old/1% (49) generates a "■B" signal on its output side, Due to dirt, the output "II" of the flip-flop 1/8 (483)
It is inverted by the OR circuit (51) and supplied to the next-stage Frisopflop circuit (484).In addition, at this time, the output of the Soritsuflop circuit (48+) is "H".
” or “L”.

In addition, flip-flop circuits (48s), (484
) (482), <48s> output is “H” #
HII.

In the case of "H", "H" exhibiting a pattern as shown by curve a in FIG.
It generates the signal I(゛), thereby converting the output “■(” of the flip-flop circuit (483) into the EOR circuit (51
) and supplies it to the ζ flip-flop circuit (484).

In addition, flip-flop circuits (48s), (484
).

(482), (48t > output is “L”, “L”
.

When the curves of "L" and "L" exhibit a pattern as shown in FIG. The output “H” of the pull circuit (483) is connected to the EOR circuit (5
1) Flip-flop #l8 without any inversion
(484).

Then, the output of the flip-flop circuit (473) is “H”.
”, a flip-flop circuit (48s).

Each output of (484), (482), and (48t) is -[, and in case of other combinations outside the series, all 16
For the remaining 12 ways out of itll, the discrimination circuit (49) generates 01 of 17" on its output side, and the judgment circuit (49) generates the 01 number of 17" on the output side, and the output of
The rEOR circuit (51) supplies the ``H'' to the see-through flop circuit (484) without inverting it in any way.

Also, the output of the solid flop circuit (47:I) is “L”
In other words, when the R and F signals from the input terminal (41) are not between the comparison peaks (4z) and (43), the 1-Nohel discrimination is reliable (1-noher discrimination is In this case, the discrimination circuit (49) is composed of the tree flop circuits (48+), (482), (4B4).
).

Regardless of the output of (486), "' 1.
” signal is generated and the flip-flop circuit (483)
The output of is inverted with EOR times 11K (5) and the flip-flop is exactly as it is. I II! J!
Let (J( be supplied) to (48-+).

The following Table 1 is a logical value table for the discrimination circuit (49) that summarizes the above. In this Table 1, the * mark is "11".

It represents don't care, which can be either "L".

Table 1 In this embodiment, if the RF multiplied signal from the input terminal (41) is between the reference levels of the comparison circuits (42) and (43) and there is any ambiguity in the level determination, , the data before and after the data existing between the reference levels, that is, the flip-flop circuit (48G), (48
4), (482), and (48z), and when the pattern is as shown in the characteristic a in FIG. 6 and the characteristic in FIG. 7, the flip-flop circuit (
The contents of 483) are output as they are, and when the pattern is such that the characteristics shown in FIG. 6 and the characteristics a of FIG. Therefore, an error-free digital signal is taken out on the output terminal (52) side.

FIG. 8 shows a second embodiment of the present invention, in which there are three reference levels.

In the figure, (61) is an input terminal to which the RF multiplied signal passed through the initial stage is supplied.
1) RF (No. Fj is a comparison circuit (62).

The signal is supplied to one of the input terminals (63) and (64), and compared to the reference level supplied to the other input terminal from the terminals (65), (66) and the ground side, respectively.

In this case, for example, a signal at a positive reference level is supplied from the terminal (65) and a signal at a negative reference level is supplied from the terminal (66) with the ground potential as the midpoint.

The respective outputs of the comparator circuits (62) and (63) are connected to, for example, Frisopf 1. Shift register consisting of top circuit (6B+) and (682)
68). Also, a comparison circuit (64)
For example, the output of the solve flop circuit (691 to (69
4) is supplied to the input side of a shift register (69) consisting of: Then, the output of the shift register (68) and the output of the flip-flop circuit (682) are the output of the discrimination circuit (7).
0) and a flip-flop circuit (69z) of the shift register (69).

The outputs of (692), (693), and (694) are supplied to a discrimination circuit (70). Note that the shift register (
A clock pulse for shifting is supplied from a clock terminal (71) to each of the flip-flop circuits 68) and (69).

Also, the flip-flop circuit of the shift register (69) (
A switch circuit (72) is provided between (692) and (693), the output of the flip-flop circuit (692) is supplied to the contact a side of this switch circuit (72), and the remaining contacts A and C are connected to each other. Connected to constant voltage terminal +Vcc and ground side. And this switch circuit (72
), the movable terminals of which are located before and after the flip-flop circuit (692) according to the output of the discrimination circuit (70) (694).

'ζ is switched according to the contents of (693) and (69t). Then, an output terminal (73) is taken out from the output side of the shift I register (69), that is, the output side of the flip-flop circuit (694).

Next, the operation of this circuit is as described above with reference to FIGS. 6 and 7.
@ l, I will explain. In addition, in the same figure, C1.

is the reference level of the comparison circuit (64), 1. It is assumed that r and L2 are the reference levels applied to the comparison circuits (62) and (63), and the arrow represents the time point at which the extraction pulse is applied.

Now, when the RF multiplied signal is supplied from the input terminal (61),
It is compared with each reference level in comparison circuits (62) to (64), and by the clock pulse from the clock terminal (71),
Riki Ryokawa of the comparison circuits (62) and (63) is the EOR circuit (
67) and is sequentially shifted into a shift register (68), and at the same time, the output of the comparison circuit (64) is sequentially shifted into a shift register (69). Therefore, the solve flop circuit (681) of the shift register (6th), (
The contents of 682) temporally correspond to the contents of the solve flop circuits (69s) to (692) of the shift (- register (69)).

The output of the EOR circuit (67) is 11 when the outputs of the comparison circuits (62) and (63) are different, that is, when the RF multiplied signal level is between the reference level Ls and I-2. ”, and otherwise it is “L”.

Now, if we consider the case where the output of the flip-flop circuit W1+ (6B2) becomes "11", at this time, the flip-flop circuit corresponding to this becomes the top circuit 1! JG (Ei
92), the base Y (Level (0) of the comparator circuit (64)
It is unclear whether it is above (level) or below. Therefore, in the discrimination time 11Pt (70), the contents of the data before and after the output of the flip-flop 1 [sting (692)]
``In other words, based on the contents of the flip-flop circuits (694), (693), and (69+) of the shift register (69), the output of the flip-flop circuit (692) is output as is, or is fixed to a substantially constant level. Determine whether to output °ζ.

For example, flip-flop circuit (694), (6!1
3) The output of (69□) is “H”, 'IT',
When the sixth and first lines of "I7" form a pattern as shown by curve a, the discrimination circuit (70) uses its output to control the switch circuit (72) to switch to the contact side, and the next stage The flip-flop circuit (693) is supplied with a +Vcc current, that is, an 'H' signal.Furthermore, the flip-flop circuit (694), Nigq), ((i
If the output of τ)1) forms a pattern as shown by the curved line in FIG.
70) controls the switch circuit (72) by its output to switch to the contact C side, and the next stage soli knob solo knob I#
(693) so as to supply a signal of No. 4 (I"L") at ground potential.

Then, the output of the solid flop circuit p (6112) is I]', and the solid flop circuit (Ei!]→).

When each output of (603) and (69t) is a combination other than the child chain, that is, the remaining 6 out of 8 total
As for C, the discrimination circuit (70) controls the switch circuit (72) by its output and connects it to the contact a side, and the 111 power of the flip-flop circuit (692) is directly connected to the flip-flop circuit (693). ) Supply L.

Also, the output of 1 m (682) flip-flops is “■
, ”, that is, when the RF multiplied signal from the input terminal (61) is not between the reference levels of the RF multiplied signal comparison circuits (62) and (63), the level can be reliably determined. The circuit (7 (+>) controls the switch circuit (72) by its output regardless of the outputs of the solid flop circuits (691), (693) +' (694), and connects it to the ζ contact a side. , flip-flop circuit (
692) output as it is\solubflotub circuit (69
3).

The following Table 2 shows the 4
In this table of logical values, the ζ* mark in Table 2 is "11".

” Don't care, which can be either I or ゛.
Also, S represents the output of the solid block circuit (692).

Table 2 Thus, in this embodiment, the reference level of the comparator circuit ([i4) is between the reference levels of the RF multiplied signal comparison circuits (62) and (63) from the input terminal A ([il)]. 1
- If it is unclear which side of the
62) and (Ei3), the data before and after the data existing between the standard levels of
4) Determine the pattern from the contents of , (6Xh) and (6!1+), and if the pattern is as shown in characteristic a in Fig. 6, forcefully increase the signal level to +Vcc voltage When the signal level is fixed to the corresponding "H" signal and the pattern shown in Figure 6 is shown, the signal level is forcibly fixed to the ground voltage (I5" signal corresponding to 1'l). otherwise, the frit-flop circuit (
692) is output as is, an error-free digital signal is output to the output terminal (73).

FIG. 9 shows a third embodiment of the present invention, in which the embodiment of FIG. 5 described above has a pattern as shown in FIG. While only considering patterns that are likely to occur,
In this embodiment, the pattern shown in FIG. 7 is not limited to the pattern shown in FIG.
This is a case in which patterns that are likely to cause errors are also taken into consideration.

In FIG. 9, parts corresponding to those in FIG. 8 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In this embodiment, the shift register (6B') is composed of flip-flop circuits (681) to (683), and the shift register (69') is composed of a solid flip-flop circuit (69').
+ ) to (69s), and a shift register (68
output of the flip-flop circuit (683) of the shift I register (69') and the flip-flop circuit (6!) of the shift I register (69').
L), (892), (69,+), (69G
) are supplied to the discrimination circuit (70'). In addition, the shift register (69')
:1 switch between circuits (693) and (694)! 8 (72), and the switching of this switch circuit (72) is controlled by the output of the discrimination circuit (70').

The other configurations are the same as in FIG.

Then, the output of the C1 Frisopf turtle circuit (683) is "I("), and the flip-flop circuit (69s).

(694) The outputs of I(692) and (6!h) form a pattern as shown by curve a in Figure 6 of "H", "H", "'I,", "■,", respectively. case, or “L”
.

There are curves in Figure 6 for "L", H", and "1("; if a pattern like l<4 is formed, don't c:
If n r e and '→, then] - just consider the same method of determination as in the case of FIG. 8 described above.

On the other hand, the output of the solid flop circuit (683) is “H”
Solitub flop I” sting (6!li), (6
ri4).

The outputs of (692) and (69t) are
”.

When accepting a small pattern of curve aC in FIG. 7 of "H", "+1", ")I", the discrimination circuit (70') controls the switch circuit (72) by its output. The contact is switched to the C side, and a signal of "L", which is the ground potential, is supplied to the next stage flip-flop circuit (694).

Also, Solitub flop circuit (69s), (694
) (692) and (89+) are respectively ``L''
1゛L'', ``L'', ``L'' If the curve shows a pattern as already shown in Fig. 7, the discrimination circuit (70') controls the switch circuit (72) with its output to close the contact. The switch is switched to the positive side, and a signal of "■ ("), which is a +Vcc potential, is supplied to the next stage flip-flop circuit (694).

Then, the output of the flip-flop circuit 111+ (683) is “I]”, and the output of the flip-flop circuit II (695)
.

Each output of (694), (692), and (691) is 1
For other combinations not listed in series, the remaining 12 out of 16 combinations are determined by a discrimination circuit (70'
) controls the switch circuit (72) by its output and connects it to the contact a side, so that the output of the flip-flop circuit (693) is directly supplied to the flip-flop circuit (694).

Also, the output of the flip-flop circuit (683) is 't,''
In other words, when the RF multiplied signal from the input terminal (61) is not between the respective reference levels of the comparison circuits (62) and (63), level discrimination can be performed reliably. ? t (7(1') is a solid flop circuit (69+), (692), (69q)
.

Regardless of each output of (695), the output controls the switch circuit v8 (72)' (connected to the contact a side, and the output of the flip-flop circuit (693) is directly applied to the five flip-flop circuits Wtr (6!). 11) Make sure that 4IL is paid.

The following Table 3 is a logical value table for the discrimination circuit (70') that summarizes the above. In this Table 3, the * mark is "'+1".

Either “L” is acceptable.
r e and S represents the output of the solid flop llll3 (693) obtained at the output side of the switch circuit (72).

As shown in Table 3, in this embodiment, although the RF multiplied signal from the input terminal (61) is between the reference levels of the comparison circuits (62) and (63), the reference level of the comparison circuit (64) is "F
If it is unclear on which side the comparator circuit (62
) and the data before and after the data existing between the reference levels of (63), that is, the 79777171 circuit (69s),
The pattern is determined from the contents of (694), (692), and (69t), and if the pattern is as shown in characteristic a in Figure 6 and characteristic a in Figure 7, the signal level is forcibly set to the level equivalent to +Vcc potential. When the signal level is fixed to ``H'' and the signal is output, and when the pattern shown in FIG.

Since the output is fixed to the signal of , and in other cases, the contents of the solid flop circuit (693) are output as is, an error-free digital signal is taken out to the output terminal (73) side. It will be done.

Is Figure 10 a specific episode 1 of Figure 8? An example of δ configuration is 5
In FIG. 10, parts corresponding to those in FIG. 8 are designated by the same reference numerals and explained as "C".

In the figure, an RF multiplied signal is supplied from an input terminal (61) to one input terminal of the comparator circuits (62), (63) and (64), and a terminal (65) is supplied to the other input terminal.
, (66) and a reference level supplied from the ground side. In this case, the ground potential is set at the midpoint, and for example, a signal at a stop reference level is supplied from the terminal (65), and a signal at a negative reference level is supplied from the terminal (66).

The outputs of the comparator circuits (62) and (63) are outputted through IEOR circuits (81) and (82), respectively, which serve as uplinks.
(J) is supplied to the inner input end of the E ORu path (67), and the output of this IE ORu path (67) is the input side of a shift register (68) consisting of, for example, D-type flip-flop circuits (681) to (683). Also, comparison time I
The output of I (64) is sent to the EOR circuit (83) as a buffer.
) and time adjustment (with EOR circuit (67) system) E O
It is supplied via the R1IiJ path (84) to the input end of a shift register (69) consisting of, for example, D-type flip-flop circuits (69s) to (694). Then, the output of the shift register (68), that is, the flip-flop circuit (68)
The output of B2) is the switch circuit (72) of the discrimination circuit (70).
) as a switching control signal, as well as the inverted output of the flip-flop circuit (691) of the shift register (69), the flip-flop circuits (693) and (694).
) are passed through the AND circuit (85), and the outputs of the solid flop circuit (6!h) and the inverted outputs of the flip-flop circuits (693) and (''94) are passed through the AND circuit (86). and is supplied to the switch circuit (72) as a switching control signal.

Further, a clock pulse for shifting is supplied from a clock terminal (71) to each flip-flop circuit of the shift registers (68) and (69).

The first switch (72) is a solid block circuit (69).
2) and (6!13), and a switch circuit (7!
The contact 2) is connected to a constant voltage terminal Vcc,
The contact C is grounded, and the remaining contacts al to a6 are connected to the output side of the flip-flop circuit (692). Also, the mouth J of the switch circuit (72)! The ++ terminal is connected to the input end of the flip-flop circuit (693). Then°ζ
The lIJ active terminal terminal change of the switch circuit (72) is
It is controlled by a logical combination of the output of Frisopf ``1 Tsubu'' 1 Old 181 (682) and the respective outputs of AND circuits (85) and (86) as described later.

Now, when the RF multiplied signal (1) is supplied from the input terminal (61), it is compared with the valley reference in the comparator circuits (62) to (64), and the clock pulse from the clock terminal (71) causes the comparator circuit 11 to (62) and (63) are sequentially shifted in the shift register (6B) via the EOR circuit (67), and at the same time, the output of the comparison circuit (64) is sequentially shifted in the shift I register (69). Therefore, the shift register (68) free knob flop circuit (6B
+ ), (682) contents are shift register (69
)'s Flip-Flo Knob times'dt (69t) ~ (6
92), which correspond in time to the contents of 92).

In addition, the output of the EOR1 path (67) is "I" only when the outputs of the comparison circuits (62) and (63) are different, that is, when the RF multiplied signal level is between the reference levels L1, l, and 2. Otherwise, it is L''.

The discrimination circuit (70) checks the contents of the flip-flop circuit (682) of the shift register (68) and the shift register (
69) flip-flop circuit (691).

While looking at the outputs of the AND circuits (85) and (86) corresponding to the contents of (693) and (694), for example, follow the logical value table shown in Table 4 below, (72) is controlled. In addition, in this Table 4, S
For example, it represents the output of the flip-flop circuit (692) obtained on the output side of the switch circuit (72).

Table 4 From Table 4, in the discriminator circuit (70), the output of the flip-flop circuit (682) is "H", and the outputs of the loop circuits (85) and (86) are "I bit" and "]," respectively. When,
In other words, in the case of a pattern that does not follow the curve a in Fig. 6, switch circuit 11fi <72) is switched to the contact side, and a signal of "11°" corresponding to the -1-Vcc potential is applied to the flip-flop. Also, when the output of the flip-flop circuit (682) is "I(") and the outputs of the AND circuits (85) and (86) are "L" and "H", respectively, That is, in the case of a pattern as shown by the curve in FIG. 6, the switch circuit (72) is switched to the contact C side, and an "L" signal corresponding to the ground potential is sent to the flip-flop circuit (693).

Also, discrimination episode vI! In the case of the remaining combinations other than those mentioned above, I (70) connects the switch 1u path (72) to the contacts a1 to a6 according to each logical combination, and connects the output of the flip-flop circuit (692) to the next stage. It is supplied to the flip-flop circuit (69i).

In this way, a completely error-free digital signal is taken out at the output terminal (73).

Although the switch circuit (72) uses a multiplexer in FIG. 10, it is not limited to this, and may be configured by a logic circuit corresponding to the logic value table of Table 4.

Effects of the Invention As described above, according to the present invention, a plurality of human signals (161
The human power signal between the reference levels is compared to the reference level and memorized, and the human power signal between the reference levels is set to a predetermined level. Since I set it to
Even when the transmission conditions are poor, such as when ζ errors are likely to occur, digital 4N',i can be reliably detected, and the error rate (within a low error rate)1' becomes +1J (il).

[Brief explanation of drawings]

Fig. 1 is a schematic block diagram of an example of conventional IIf raw silk, Figs. 2 and 3 are waveform diagrams used to explain the operation of Fig. 1, and Fig. 4 is a diagram illustrating the basic principle of this invention. IJ for explanation
Figure 5 shows an embodiment of the present invention; ] <-4 block 1:1 diagram, Figures 6 and 7 are blank lines for explaining the invention 8 and 9 are block diagrams showing other embodiments of the present invention, respectively, and FIG. 10 is a block diagram of the first embodiment of FIG. 8. FIG. 3 is a connection diagram showing an example of the g configuration. (22) , (23) , (42) , (,13) ,
(62). (63) and (64) are comparison circuits, (2Ei) and (2
7). (,17), (4B), (6B), (643) are shift 1-registers, (29), (49), (70)
is a control circuit, (30). (72) is a switch circuit, and (5]) and (67) are exclusive OR (EOR) circuits. Same Hidemori Matsukuma...'...□゛' Figure 1 Figure 2 Figure 3 Figure 4 Figure 6 +++1+ HHHH LL LL Figure 7+++++++ HHHH LL LL

Claims (1)

[Claims] Comparing means having a plurality of base 11 color levels, comparing the reference level and the human input signal, storing means for storing the output of the comparing means, and determining the pattern of the input signal from the contents of the storing means. 1. A digital signal detection circuit comprising: a determining means, wherein when the contents before and after the input signal between the reference levels have a specific pattern, the input signal between the reference levels is set to a predetermined level.