JPS6018773A - Measurement of pulse width - Google Patents

Abstract

PURPOSE:To eliminate errors possible in the results of measurement by determining a pulse width depending on a shift of a clock phase shifting circuit with the control of computation/control/memory circuit. CONSTITUTION:A bit synchronization circuit 4 counts a bit error rate with an error counting circuit 7 depending on a clock phase shifted and a computation/ control/memory circuit 8 computes and memorizes the results to control a clock phase shifting circuit 9 until the shifting of the clock phase is ended equivalent to one bit of data. This operation is repeated and the control is stopped when the shifting of the clock phase is ended equivalent to one bit of data. Meanwhile, the shift in the clock phase of the circuit 9 is determined as measured value with the pulse width of a digital waveform. This enables the measurement of the width of a phase jitter even in the pulse width of a signal pattern other than repeated signals thereby eliminating errors in the results of the measurement.

Description

DETAILED DESCRIPTION OF THE INVENTION +a+ Technical Field of the Invention The present invention relates to a pulse width measuring circuit for a digital signal transmission system.

Background of fbl technology In recent years, with the need for advanced technology development, digital signal transmission methods have been in the spotlight, and in the future, digital signals will be used as the core of advanced information communication systems using PCM transmission, digital optical communication, and various information processing systems. Technology is evolving with advances in large scale semiconductor integrated circuit technology.

However, performance evaluation of the pulse width of digital waveforms, which is the basis of various processing systems that utilize digital technology, affects the precision, accuracy, reliability, etc. of the transmission system, and Conventionally, the pulse width of a digital waveform after transmission in a system, etc., has generally been evaluated by measuring the bit error rate (BER) after transmission.

(C1 Prior Art and Problems Conventionally, this type of pulse width measurement of digital waveforms is basically classified into two types. This is a waveform diagram based on the principle of measuring the crossing time. FIG. 2 is a waveform diagram based on the principle of sampling the digital waveform to be measured and measuring based on the sampling time difference.

In the digital waveform diagram to be measured in FIG.
1, t2, the pulse width = t2 - tl, and the measurement result of the pulse width of the digital waveform can be obtained by the time at which the prescribed dark value voltages cross.

In the diagram of the digital waveform to be measured in FIG. 2, the dark value voltage is set to vth as above, and the digital waveform to be measured is sampled with the sampling pulse of the clock generator.
If the sampling pulse pinch time is Ts and the number of pulses at the dark value voltage vth held by the sample tent at the dark value voltage of the digital waveform to be measured is 6 and 19, then the pulse width is -(196) x T3, and the specified dark value Multiplying the number of pulses between voltages by the pinch time provides a measurement of the pulse width of the digital waveform.

In addition, the measurement method for measuring the pulse width of this digital waveform applies the measurement principle described above (11 Manual measurement method using an oscilloscope.

(2) Method of measuring with an automatic tester.

(3) Method using a waveform analyzer.

etc. However, after fl) is transmitted through the transmission system, the digital waveform signal contains phase jitter due to the short-term unstable state of the phase of the digital waveform, the so-called jitter phenomenon, so the edges of the waveform are not clear. It disappears. Therefore,
When measuring with an oscilloscope, etc., the subjectivity of the person taking the measurement comes into play.
Accurate measurements cannot be made (and measurement errors are likely to occur. Also, it is virtually impossible to measure all pulse widths of a long data pattern using this method. Method (2)
The main measurement target is continuous repeating signals, and it is not suitable for measuring irregular signals such as signal patterns in transmission systems. This is because the pulse width varies depending on the signal pattern, so it is meaningless to measure any one pulse width. The method (3) also targets measurement of continuous repetitive signals.

Therefore, it is not suitable for the same reason as (2). However, there is also a method of increasing the number of measurements and averaging them.

As described above, conventional methods for measuring the pulse width of digital waveforms are unable to measure the phase jitter phenomenon of digital waveforms and irregular signals, and errors tend to occur in the measurement results. A considerable error occurs in the measurement result of the pulse width of the digital waveform after transmission in the transmission system, and the conventional method of measuring the bit error rate after transmission is indirect, and As a measurement method for evaluating the performance of

(dl OBJECT OF THE INVENTION The present invention aims to solve this conventional drawback.

tel Structure of the Invention The above object is to provide a clock generation circuit that becomes a basic clock signal source of a measurement system and generate various signal patterns synchronized with the basic clock of the clock generation circuit on the input side of a transmission system that transmits digital signals. A data pattern generation circuit is provided on the output side of the transmission system, and a bit synchronization circuit is provided on the output side of the transmission system for bit synchronizing the signal of the data pattern generation circuit and the signal after passing through the transmission system. A frame synchronization circuit for obtaining frame synchronization of the signal that has been synchronized, and a signal from the data pattern generation circuit whose frame synchronization has been achieved by the frame synchronization circuit, and a signal after passing through the transmission system are compared to detect error history 1. an error detection circuit that calculates a bit error rate by counting errors detected by the error detection circuit;
A clock phase shift circuit that shifts the clock phase by a time corresponding to 1/n hint of the data pattern from a state where the bits are synchronized, and an arithmetic/control/memory circuit that controls the clock phase shift circuit are provided. , a clock signal from the clock generation circuit is input to the data pattern generation circuit, a signal pattern generated by the data pattern generation circuit is input to the transmission system, and the transmission signal after passing through the transmission system is synchronized with the bits. The signal pattern is input to a circuit to achieve bit synchronization, the frame synchronization circuit performs frame synchronization, the error detection circuit compares the signal pattern with the signal pattern of the data pattern generation circuit to detect an error, and the detected error is counted as the error count. The P1-error rate calculated by the circuit is stored, and the arithmetic/control/storage circuit controls the clock phase shift circuit to shift the clock phase until the clock phase shift for 1 bit of data is completed. This is achieved by the present invention, which is configured to be input to the bit synchronization circuit.

In other words, a signal pattern is input from the input side of the transmission line of the transmission system to be measured, the output signal pattern after passing through the transmission line of the transmission system is bit synchronized and frame synchronized, and the signal input to the transmission line of the transmission system is Detect bit errors by comparing them with the pattern signal, input the calculated result of this bit error to a clock phase shift circuit, input the clock phase shifted by the clock phase shift circuit to a bit synchronization circuit, and calculate this bit error rate. By controlling the clock phase shift circuit so that the clock phase shift amount is less than a specified value, the measurement result of the pulse width of the digital waveform is calculated by the clock phase shift amount, and the bit error rate is measured and the bit error rate is calculated. This is a digital waveform pulse width measurement method that incorporates a feedback circuit function that inputs the result to the arithmetic, control, and storage circuit, controls the clock phase shift circuit based on the input calculation result, and shifts the clock phase of the bit synchronization circuit. be.

With the circuit configuration of the present invention, by measuring the pulse width of a digital waveform that satisfies a specified focus error rate, the pulse width of a signal pattern that is not a repetitive signal, as well as the width of phase jitter, can also be determined to meet a specified bit error rate. The permissible phase range of the sampling clock to obtain the data can also be clearly measured. Furthermore, the definition of the pulse width of a pulse containing jitter can be clarified. Therefore, even if the phase jitter phenomenon or irregular signals of the digital waveform after transmission through the transmission system occur, errors will not occur in the measurement results, and the present invention provides an accurate and reproducible measurement method for evaluating the performance of digital waveforms. It is something.

(f) Example of the Invention An example of the present invention will be described below. FIG. 3 shows a circuit configuration block diagram of a pulse width measuring circuit according to the present invention. 1 is a clock generation circuit, 2 is a data pattern generation circuit, 3 is a circuit under test or transmission path (hereinafter collectively referred to as the circuit under test), 4 is a bit synchronization circuit, 5 is a frame synchronization circuit, 6
7 is an error detection circuit, 7 is an error counting circuit, 8 is an arithmetic/control/storage circuit, and 9 is a clock phase shift circuit.

In this circuit configuration, a basic clock is generated from a clock generation circuit 1, which is the basic clock signal source of the measurement system, and various digital waveform signal patterns that can be selected by the circuit under test synchronized with this basic clock are generated. A signal pattern is input from the data pattern generation circuit 2 to the circuit under test 3 to be measured. The signal waveform input to the circuit under test 3 is in the form of a digital waveform whose phase waveform is shifted or contains phase fluctuations due to circuit characteristics specific to the circuit network of the circuit under test 3, and is output after the circuit under test imm. It is output to the output side of the circuit under test 3 as a signal pattern. In order to achieve bit synchronization, this output signal pattern is input to the bit synchronization circuit 4 for bit synchronization, and the output signal pattern with the focus synchronization is input to the frame synchronization circuit 5 for frame synchronization. Period 1i! &5, the frame-synchronized output signal pattern is output to the error detection circuit 6, and the pattern generation circuit 2 obtains frame synchronization with the reference signal pattern that does not pass through the circuit under test 3, and the error detection circuit 6 receives the same signal pattern. Output. These two signal patterns are compared by the error detection circuit 6 to detect an error focus, and the detected error bits are counted by the error counting circuit 7, and the counting results are calculated, controlled, and described in 1. a
The signal is sent to the circuit 8, and the calculation/control/memory circuit 8 calculates and records whether the error rate is greater than or equal to one error rate, and controls the clock phase shift 1 circuit 9. The clock phase shift circuit 9 receives a clock signal from the clock generation circuit 1,
The time for 1 bit of the signal pattern is 1/n [1/n
The clock signal shifted by a time period of [bits] is sequentially output to the bit synchronization circuit 4 under the control of the clock phase shift circuit 9. The bit synchronization circuit 4 changes the bit synchronization of the output signal pattern using the shifted clock phase and inputs it again to the frame synchronization circuit 5, and the bit error rate is counted by the error counting circuit 7 along the continuous path, and is calculated. - The control/storage circuit 8 performs calculation and storage, and the calculation/control/storage circuit 8 controls the clock phase shift circuit 9 until the clock phase shift of one pin of data is completed. The above path is repeated, and control is stopped when the clock phase shift for one bit of data is completed. During this time, the clock phase shift amount of the clock phase shift circuit 9 within the range where the bit error rate is less than the prescribed bit error rate is taken as a measurement value of the pulse width of the digital waveform. Note that if you shift the clock phase, there may be areas where bit synchronization or frame synchronization cannot be achieved.
These are determined by the arithmetic/control/storage circuit 8 to be higher than a specified bit error rate.

1 FIG. 4 shows a circuit configuration block diagram of another embodiment according to the present invention. In this figure, the same objects are indicated by the same symbols as in FIG. 3. 10 is an external data pattern generation circuit that generates a signal pattern similar to the data pattern generation circuit 2; the generated signal pattern is input to the frame synchronization circuit 5;
Frame synchronization is performed by a frame synchronization circuit 5. Reference numeral 11 denotes a clock regeneration circuit which receives the transmitted signal pattern from the circuit under test 3, regenerates clock pulses, and supplies the regenerated clock pulses to the clock phase shift circuit 9. This external data pattern generation circuit 10 and clock recovery circuit 1
1 is different from that in FIG. 3, and the measurement path is the same as that described above, so a description thereof will be omitted. Figure 3 shows a circuit when the circuit under test 3 is a relatively small device and the signal generation sending side and bit error rate counting calculation shift etc. receiving side are installed in the same place and the measurement is performed. This circuit is used when the circuit under test 3 is a long cable, or when the sending and receiving ends of a transmission line are far apart, and the signal generation sending side and the receiving side of bit error rate counting, calculation, shifting, etc. are separated for measurement. You can choose according to the actual situation.

fg+ As described in detail of the invention, as a method for measuring the pulse width of a digital waveform signal after being transmitted through a transmission system, a signal generation source is provided using a clock generation circuit and a data pattern generation circuit, and a focus synchronization circuit and a frame synchronization circuit are used. Calculation, control, and
By shifting the clock phase of the clock phase shift circuit under the control of the memory circuit and adjusting the pulse width by the amount of clock phase shift, it is possible to accurately measure the pulse width of a signal pattern that is not a repetitive signal, as well as the width of phase jitter. This method has the effect of obtaining measured values with good reproducibility and accurately evaluating the performance of digital waveforms without causing errors in the measurement results.

[Brief explanation of drawings]

1 and 2 are waveform diagrams illustrating the principle of pulse width measurement, and FIGS. 3 and 4 are block diagrams of the circuit configuration of a pulse width measurement circuit according to the present invention. In the drawings, ■ is a clock generation circuit, 2 is a data pattern generation circuit, 3 is a circuit under test (or transmission line), 4 is a bit synchronization circuit, 5 is a frame synchronization circuit, 6 is an error detection circuit, and 7 is an error. 8 is a calculation/control/storage circuit; 9 is a clock phase shift circuit; 10 is an external data pattern generation circuit; and 11 is a clock regeneration circuit. 5 f 1 Figure 1 E 2 Rate 2 Figure

Claims (1)

[Claims] A clock generation circuit serving as a basic clock signal source for the measurement system and a data pattern generation circuit generating various signal patterns synchronized with the basic clock of the clock generation circuit are provided on the input side of a transmission system that transmits digital signals, a signal from the data pattern generation circuit on the output side of the transmission system;
a bit synchronization circuit for synchronizing the bits of the signal after passing through the transmission system; a frame synchronization circuit for synchronizing the bit synchronization of the signal from the bit synchronization circuit; an error detection circuit that detects error bits by comparing the obtained signal from the data pattern generation circuit with the signal passed through the transmission system; and an error detection circuit that counts the errors detected by the error detection circuit and calculates a bit error rate. a clock phase shift circuit that shifts the clock phase by the time of 1/n bit of 1 bit of the data pattern from the bit synchronized state; and an arithmetic/control circuit that controls the clock phase shift circuit. A storage circuit is provided, a clock signal from the clock generation circuit is input to the data pattern generation circuit, a signal pattern generated by the data pattern generation circuit is input to the transmission system, and the transmission signal after passing through the transmission system is is input into the bit synchronization circuit to achieve focus synchronization, the frame synchronization circuit performs frame synchronization, and the error detection circuit compares the signal pattern with the signal pattern of the data pattern generation circuit to detect an error. The focus error rate calculated by the error counting circuit is stored, and the arithmetic/control/storage circuit controls the clock phase shift circuit to shift the clock phase until the clock phase shift for one bit of data is completed. A method for measuring a pulse width, characterized in that the pulse width is inputted to the hint synchronization circuit.