JPS60187153A - Data receiving circuit - Google Patents

Abstract

PURPOSE:To detect an error of received data and to write data in memory even after data is ceased by generating a pseudo clock the same as the received data in bit period after the data is ceased. CONSTITUTION:An output Q' of an FF14 goes up to a level H during data reception and a clock synchronizing with a bit period outputted from a one-shot multiplier 12 is generated through an OR gate 133. When the data is ceased, on the other hand, a signal CS' goes up to the level H and a terminal Q of the FF14 is held at the level H. Therefore, the pseudo clock CLK of a clock generating source is generated from a clock selecting circuit 13 through an AND gate 132 and an OR gate 133.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a reception clock generation circuit used in a data receiver 4=i circuit of a so-called local area network that transmits data between devices scattered in a relatively narrow area. Regarding.

[Technical background of the invention and its problems]

There are path types, star types, ring types, etc. of network topolozos, but the path type in which multiple machines i = are plunged on one transmission line at a required distance is CSMA (CarrierSense Mul
Collisi Access)/CD (Collisi
on Detect)
ernet) is widely known. This Ethernet determines which device among the many devices branched to one transmission line will take the initiative in transmission, by detecting the disappearance of data transmitted on the transmission line, and then detecting the disappearance of data transmitted on the transmission line. When data is transmitted at different timings and there is a conflict, the data is transmitted using random number means given f, and the device that transmitted the data first takes control of the transmission line. Therefore, Ethernet is the fi11. As is clear from the description, it is an asynchronous communication method, and its transmission format is "0" from the viewpoint of transmitting a clock component before transmitting data.
, NRZ (
Encoding/transmitting encoded patterns without adopting a non-return-to-zero format
A P-pattern type is used. If this code is greater than 3, -C is used, such as Manchester code or pi-phase code.

Therefore, the data receiving circuit side decoding method when using the above Manchester code-1 (1) method using a one-shot timer,
There are two methods, such as using a digital PLL that performs sampling using a higher-order clock of a forward lock.By the way, in Ethernet using carrier sense, by adopting Manchester code, the method shown in Fig. 1 is used. As shown, the reception clock RXC is generated by FJJ by receiving the Etsuo ES of the Manchester code RXD, but since Manchester 8e@RXD disappears at the end of transmission, the reception clock RXC cannot be regenerated.Generally, the reception clock RXC is necessary to shift data to shift register 1 for error detection inside the data receiving circuit and to generate a memory write request signal to shift register 2 or DMA (direct memory access) controller 3, as shown in Figure 2. It is something.

For example, the error detection means includes an error detection shift register 1 and a comparator 4, and includes a Manchester code RXD
The NRZ data obtained by decoding by the decoder 5 is shifted and stored in the error detection shift register 1 using the reception clock RXC also obtained by decoding, and is output from the shift register 1 at the end of reception. The parallel data is supplied to the comparator 4 and compared with the data stored in the first fth column.

I) The MA controller 3 receives the memo IJ, I created by the reception clock RXC from the shift register 2.
When receiving the J input request signal, a command is given to the register 6 for temporary storage and the CPU 7, and
Processing is performed so that the data is stored in the memory 8.

When performing this IIL-] process, the reception clock 1t
Even after the disappearance of the Manchester code RXI), Xc becomes constant at the stage tVI/r.

By the way, among the decoding methods (1) to (3) above, (3)
)'s j′ inotal J) The method using LL uses a high-speed clock
Phase tatami rock 1 with bow + txo, so
Reception clock RXC even after Manchester code RXD disappears
can be supplied to the shift register 1 and DMA controller 1-RA 3. However, in the 7' code method of Because we are getting
Manchester't:) After the disappearance of RXD, the reception clock RXC cannot be generated. In addition, ■Digital P
Even in the decoding method using LL (III), in order to follow the transmission lock of 10 MHz,
0x clock 100 Mi (z) is used, but it can be used as a circuit element with normal MOS/IC or TLL.
, the 1st R rule was not completed in time, and therefore the comparative consumption 11
ECL with big shine (emlter couple
However, there are disadvantages such as the use of d logic), which makes it difficult to obtain X, and circuit design-1-1- is often difficult and costly.

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a reception clock generation circuit that can generate a reception clock by simple means and use it for data processing even after reception data disappears.

[Summary of the invention]

The present invention includes a clock generation source that generates a pseudo clock with a frequency equal to the bit period of received data, and a disconnection circuit that determines the presence or absence of a carrier from a carrier sense signal generated corresponding to the received data. , a clock 714 selection circuit that selectively generates a clock obtained from the receiver and a pseudo clock from the clock 46 generation source based on the judgment of the judgment circuit, and This is a reception clock generation circuit that generates a clock with the same frequency as the 'j-' and '4n clocks even after extinction.

[Embodiment 1 is shown in FIG.
This will be explained with reference to FIG. Fig. 3 is a 41'q configuration diagram of the reception black/flip generation circuit, Fig. 4 is a configuration diagram of the error detector shown in Fig. 3, and Fig. 5 is a configuration diagram of the one-shot multivibrator shown in Fig. 3. . In FIG. 3, received data RXD is encoded, for example, in a Manchester code, and is received by a decoder (not shown) and is supplied to an edge detector circuit 1. This edge detector circuit 77 tt,t,.

For example, as shown in Fig. 3, the exclusive image theory Jlli circuit 1) 1
and delay element 112 detect the rising and falling edges of the received data RX+) and generate signals synchronized with the rising and falling edges of the received data RX+. Reference numeral 12 denotes a one-shot multivibrator, which is constructed, for example, as shown in FIG. That is, this one-shot multivibrator 12 connects the mutual terminals of the little gull pull multivibrator 122 to the AND gate 12.
Since a high level signal is input to 1, when a pulse is input from edge detector 11 and 1, a clock with a time width proportional to the external time constant circuit 123 is output from the Q terminal, and 13. 100 is a signal that becomes low level when receiving the carrier sense signal generated corresponding to the receiving data RXDK, and this is a signal that becomes low level when the carrier sense signal generated corresponding to RXDK is received. Shape flip
It is supplied to the D terminals of the flop and pu 14.

A pseudo clock CLK is applied to the C terminal of this D-type flip-flop 14 from a clock generation source (not shown). This pseudo clock CLKC2 reception gate R
The frequency equal to the bit period of XD is 1, 1, 1,
The borrowing C is changed in synchronization with the break in the line. 6++ Notation type flip flow 7 no 014 is carrier 'a sense mercy C8 low bell time tori uke' (
High level from Q terminal when i<no data (No. 74,
The device C8 has a high level 111J, which means the low level 41'C from the lL'iKQ terminal of the receiver 117.
``Outputs j (has geometric function.

The 7-1 sill selection circuit 13 described in I''III is connected to the first and second ant 1 digits J 31 , J 32 .
The input end of the first 7' end 7.91 is the output end of the multivibrator 12 and the 4th end of the 1) type Frino, Frog 14. connected to the terminal. On the other hand, the two input terminals of the second AND gate 132 are connected to the Q terminal of the flip-flop 14 and the output terminal of the clock generation source.

Next, the operation i'i1 of the data receiving circuit as described above will be explained with reference to FIG. Data RX encoded from the transmission UAN
When D is input, the edge detector circuit 1 of the filter receiver circuit detects the rising edge 9 and the falling edge of the receiver RXI) and detects the rising edge 1-. : IJ'i
, - and synchronized with the falling edge, and 11@elongation -i'/
12+j4ia) Proportional to time・Grus width・e Lusta made hli,! -1 subsequent Oneshi "!'/)・Martino:-Iburetano 2 is supplied.Here, when the one-shot・-Fullb・ζibrator 12 receives the Nick detector circuit 11 or the C-T flat pulse, its・Using the external time constant circuit 12 as a starting point, the external time constant circuit 12 generates a clock with a time width proportional to 1'4i.

In addition, in the Manchester code, the level always changes in the middle of the bit, falling when the bit data is '0' and rising when the pin data is '1', and the same bit data is continuous. The level also changes depending on the cut of the bit during the match.

Therefore, the edge detector circuit 1 detects the edge in the center of the bit and triggers the little gusset Φ multivibrator 122 of the one-shot multi-pie break 12.
On the other hand, in the multi-pie break 12, the time constant circuit 1
If the CR time constant of 23 is set between the 1-bit duration time and 1/2 of that time, the one-shot multi-vibrate 2 receives the received y'-event RX as shown in Figure 6.
A clock synchronized with the bit period of I) can be extracted. However, since the initial state at the start part of received data +tX1) is high level, 1. The middle edge of the first bit of 'l'NZ cannot be detected. Therefore, the first pattern for the received response data RXD is "1010・
・If you send out the preamplifier turn, you can recover the tunning voltage from the second and subsequent clocks. Even with Ethernet and other footer transmission systems, the preamplifier turn is sent at the beginning of the transmitted data. What to do is standardized.

On the other hand, the carrier sense signal is received, -1 data RXD
It is output with a delay of 20 seconds, and it is reversed on the transmitting side or the receiving side, so that the ``Iha'' as shown in Figure 6 is suddenly stopped. Vt- is low level when there is no carrier, and high level when there is no carrier.Vt- is low level when receiving data.
Then, when a pseudo clock CLK with a frequency equal to the bit period of the receiving printer RXD is applied from the clock generation source to the C terminal, the terminal becomes high level as shown in Figure 6. , which is applied to one input terminal of the first AND mark 131 of the clock selection 1j11 paths 1 and 7.Therefore, during data reception, the bit period output from the multipibrator 12 is A synchronized clock is generated through the first AND gate 131 and the ORDART 133.

On the other hand, when Gata disappears, the signal page becomes Hano Ireheru and D
It is supplied to the D terminal of the frizzo type Φ-flop 14. Therefore, Frizzo Frogt 4(r-j;,, /・
After inputting the Erail signal U, data bit period 11)l
When a clock signal equal to CLK is input, the Q terminal is set to no-level at this clock manual timing, and the second AND gate 132 is turned on.Therefore, from the clock selection circuit 13, the pseudo 7 CLK will be the second AND8 gate 132 and the ORGATE 1334 mountain).

7. The hatched parts A and A' shown in Figure 6 are
Wano Sea, 7-Multi Kui Break 12 Output 11. CLK +7) l: I month negative iτ11 minutes, which indicates that the phase is fi: 1 pHt-1. l! ? When data disappears, one/seven
Since the output of multi-9ibrator 12)) is interrupted, the black, ri I (XC is interrupted, and the rounding time is long.The phase shift at the beginning of the data is the pre-angular part that precedes 1'-even, so black 7 + tXC) Received data RXD due to phase shift of
sampling error is not a problem. The clock RXC generated at the end section is interrupted t'1.1'1.
) After the last bit has been taken in, the disadvantage and f: f,
.

do not have. In this way, even after his career disappeared, Uke 1, . It is possible to generate a reverse RXC.

In addition, in the second embodiment, black, ri) 111 output means -
2. Connect the edge detector circuit 1 and the multi-pie break 12 once a month, and disconnect the circuit.
Then, using the D-type flip-flop 14, open the edge selection circuit 13 and open the door.

132 and orakeet 133 were used, but a similar (
It may be realized using other circuits as long as they have functionality.

〔Effect of the invention〕

As described in detail above, according to the present invention, after the node disappears, it is detected and a pseudo clock having a frequency equal to the period of the received data is generated as 1) and 2). As a result, even after the data has disappeared, the pseudo clock can be used in the shift reno star, I) MA controller, etc. to detect errors in received data and to perform data writing processing to the memory. That's naive, the Dinotal PLL that was previously used to compensate for the inability to generate the Fj of the receive clock after data disappears is now unnecessary (7). It is possible to provide a reception clock generation circuit that can be realized easily and inexpensively for only $1゛η.

[Brief explanation of the drawing]

Figure 1 is a clear diagram of a hll for controlling the reception clock in a conventional circuit, and Figure 2 explains an example of how the reception clock is used! Figures 3 to 6 show an example of the clock generation circuit according to the present invention; Figure 3 is an overall configuration diagram; The figure is 31″/,
Configuration 1 as a specific example of an echnodetector circuit not shown in 1.
Figure 115 shows 1.1? as a specific example of the one-shot multi-pipe lake shown in No. 31. Figure 6 is a time chart showing the operation on a jj5:1 basis. 1 No. Esso deductor circuit, 12. One-shot multi-pipe rake, 13. Clock selection circuit, 14. D-type flip-flop.

Claims (3)

[Claims] (1) A clock extracting means for extracting a clock synchronized with the bit period from the bit patterned received data according to a predetermined rule, and a clock generating a pseudo clock having a frequency equal to the bit period of the received data. a determination circuit that receives a symbol generated corresponding to the received data and determines the presence or absence of the received data, and determines whether there is received data based on the determination signal of this determination circuit (if it is -, the above-mentioned 7. A reception clock generation circuit comprising: a clock selection circuit which selects a clock, selects the pseudo clock when it is determined that there is no reception clock, and generates the pseudo clock as a reception clock. (2) The R0T extraction means detects the rising edge and falling edge of the received data and outputs I? in synchronization with the rising edge and falling edge of the received data. Claim 1J, in which an edge detector circuit that outputs a signal and a circuit that receives an output signal of the edge detector circuit and generates a clock are integrated.
Receiver (+clock generation circuit) described in J4. (3) The judgment circuit uses a D-type fritsuno frog that receives a signal generated in response to received data at the D terminal and receives a pseudo clock from a clock generation source at the C (clock) terminal. A reception clock generation circuit according to claim 1.