JPS60187037A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit with which a potential measurement can be performed directly after it has been manufactured by a method wherein, in the integrated circuit on which a plurality of cell columns are provided pinching a wiring region, a test cell is formed in a logical cell column, and a pad to be used for potential measurement is provided in the top wiring layer. CONSTITUTION:When an NAND cell 17, an NOA cell 18, an inverter cell 19 and the like are provided pinching a wiring region, a test cell 20 is formed between the cells 17 and 18, for example. Said cell 20 is composed of the wiring part consisting of the first layer Al 11, the second layer Al 12 which is the top layer and will be turned to a pad, a contact hole 13 and the like, and the test cell is registered in the cell library of a computer together with a logical cell. Through these procedures the designer of the device determines that the test cell is to be connected to what part of the circuit together with the wiring relations of each logical cell, these data are inputted to a computer, and a shortest wiring process is performed.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to semiconductor integrated circuits.

[Prior art and its problems]

In recent years, in ICs, columns of logic cells have been
Semi-custom ICs are often used in which integrated circuits are manufactured by arranging a plurality of integrated circuits in parallel with each other, sandwiching a wall (51 area, 1 area), and applying multilayer wiring to these ICs. In such a semi-custom IC, logic cells are registered as a library, and the wiring layout, sometimes even the position within a column of logic cells, is designed by computer according to the user's specifications. In such a semi-custom IC, a large number of wiring tracks are provided in the wiring area,
This is used to connect the lead-out wirings from the cells.

By the way, in integrated circuits, it is desirable to test whether or not they are operating as planned. The most direct method is to measure the potential at a given circuit location.

In the days when layouts of ICs such as dedicated ICs were done by hand, after the layout, protruding parts were provided on the wiring to serve as pads, and potentials were later measured and tested. However, this technology seems to be forgotten due to improvements in design reliability due to design automation.

However, it can be said that there is a method 2 that cannot be overlooked when solving problems during manufacturing and checking for device malfunctions.

By the way, when trying to apply this test method to a semi-custom IC, there are many problems.

The biggest problem is that in the Yanoki Tor ξ region/area, wiring is provided at a high density due to its large-scale horizontal ratio, and if the wiring is crowded, a pad section can no longer be provided.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to provide an IC that can directly measure the potential after IC manufacturing.
It is to provide C.

[Summary of the invention]

The present invention is characterized in that a test cell is incorporated into the logic cell array mentioned above, which enables testing after IC manufacture by means of a pad using the uppermost layer wiring.

〔Effect of the invention〕

According to the present invention, by incorporating the test cells into the logic cell array, an integrated circuit can be obtained with sufficient pad size and without any restriction on the channel region.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

Figures 1 (a) to (C) and Figures 2 (al (bl), and Figures 3 (a) and (b) show test cells. Constant chain lines indicate cell areas. For example, in Figure 1 (a) is an example of one terminal, with a wiring part made of second layer Al112 and a second layer Al1
12 (top j-wiring). 13 is a contact ball. Similarly, (bl is an example of 2 terminals, (C1 is 1 where the test cell has a logic element)
This is an example.

14 is a diffusion layer formed in an 8i wafer, and 15 is a polysilicon layer. Hereinafter, the same membranes are indicated with the same hatching.

Figure 2 shows the shape of the pad, especially (b).
) is the second layer Al 112 from which the part 12' in the figure has been removed, and if the parts with different numbers are prepared, they can be easily identified on the step. Figure 4+11) (b) shows the second layer A7. Test cells are labeled with polysilicon layers.

Figures 4 to 6 are actual concrete examples, and 17 in the figure is a NAND
cell, 18 is a NOR cell, 19 is an inverter cell, 21
is a test cell of the type shown in FIG. 2(C). Diagrams inside these cells are omitted. Further, 20, 23, and 24 indicate test cells. In each figure, test cells are embedded within logic cell columns to form cell columns.

Multiple rows of these are formed on the wafer, sandwiching the channel regions on both sides.

In practice, test cells are registered in a computer's cell library along with logic cells. The designer then determines the connection relationship of each logic cell and to which part of the test cell circuit the logic cell should be connected. This data is then input into a computer to minimize the wiring and determine the placement of each cell.
Determine the wiring pattern. Of course, the size of each cell and its terminal position are registered in the cell library. As mentioned above, the wiring conditions are, for example, the first layer M wiring in the X direction,
The Y direction is formed by first layer M wiring using a predetermined number of wiring tracks.

After forming the uppermost wiring layer of the integrated circuit manufactured in this manner, it is possible to measure the potential in the operating state by contacting a probe to the pad portion. Furthermore, pads of sufficient size can be formed without interfering with wiring tracks. Also, within a step, several logic cells are used to form a circuit block, and these circuit blocks are combined to form an IC, so as the wiring is minimized, an empty area is created within the logic cell row. However, since test cells can be formed in this empty area, the degree of integration is not compromised.

When providing a large number of test cells as described above, it is easy to find the desired test cell by changing the shape of the test cells used or sequentially attaching identification symbols such as letters or numbers. Especially in computer design, cells can sometimes fly to unexpected locations, which is much easier to detect.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1, 2, and 3 are plan views of a test cell, and FIGS. 4, 5, and 6 are plan views for explaining an embodiment. In the figure, 11...first layer A! , 12...second layer A7. 20.21, 23, 24...Test cell. Attorney Kensuke Chika (and 1 other person) Figure 1 ridge) <b) (C) Figure 2 Figure 3 (/ (cln tb) Figure 4 Figure 5)

Claims (1)

[Claims] In a semiconductor integrated circuit formed by providing a plurality of logic cell rows with a wiring area in between and performing multilayer wiring, a test cell is provided in the logic cell row, and a potential is applied to the test cell using the uppermost wiring layer. A semiconductor integrated circuit characterized by being provided with a pad for measurement.