JPS60186896A - Scale converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Industrial application field This is a device that outputs a signal having a different pitch to the pitch of an input signal, and can be used as a special effect generator in the record, broadcasting, and movie industries, or as a device for generating different pitches. The present invention relates to a pitch conversion device that is used as a two-signal correction device and a device that converts the pitch of an accompaniment signal in a mixing device.

Structure of a conventional example and its problems FIG. 1 shows a conventional example. Signal S input to input terminal 1
t is 1 by the 1-bit analog-to-digital converter 2.
It is converted into a bit digital signal D1. The 1-bit analog-to-digital converter 2 can be put into practical use by using, for example, an ADM (adaptive delta modulator). and,
The clock fo is a fixed master clock generator 3. A zero digital signal D1, which is the output signal of the write clock generator 4, is input to a first digital memory 6 and a second digital memory 6. The first and second memories 6.6 can usually be implemented using random access memory (RAM). In order to operate the memory, the row address strobe (RAS)' and column address strobe (
CAS), write enable C'WE) t address (A
DDRESS) and other memory control signals f1. In other words, the principle of this conventional example is to read a digital signal written into the memory using a read clock having a frequency different from the write clock frequency, and the fixed master clock generator 3 and the memory The first memory is controlled by a first selector 11 that optimally selects fl, which is the output signal of the control fixed signal generator 7, and f2, which is the output signal of the controller 8, the variable master clock generator 9, and the memory control variable signal generator 10. 5 and the second memory 〇, and output the digital output signal D2.6 of the first and second memory 6.6. D3 becomes a serial digital signal D4 by the second selector 12, and the digital signal D4 is converted into an analog signal Sδ by the 1-bit digital-to-analog converter 13 and output to the output terminal 14.
The bit digital-to-analog converter 13 operates with a variable read clock fvK, which is the output signal of the variable master clock generator 9 and the read clock generator 15.

FIG. 2 shows the input signal S in the conventional example shown in FIG.
Output signal S when i is a 100Hz sine wave? 5 is shown. In sections A and C, sine waves are output, but in section B, a distorted waveform is output. The reason for this is that when the pitch changes, the digital data input in the memory is discarded or duplicated, so the input signal D4 of the 1-bit digital-to-analog converter 13 becomes a serial digital signal that does not exist in nature. It is for this purpose. In other words, a one-bit digital signal is discontinuous, but the signal converted to an analog signal has a continuous waveform although it generates distortion. This distortion does not pose a problem at all depending on the type of input signal, but it has the disadvantage that distortion is likely to occur particularly when the signal approximates a sine wave.

OBJECTS OF THE INVENTION The present invention aims to solve the above-mentioned problems and to provide a pitch conversion device that takes measures to reduce distortion according to the frequency band and improves naturalness of the generated distorted waveform. -ru.

Structure of the Invention The present invention comprises a first 1-bit analog-to-digital converter, a first 1-bit digital-to-analog converter, first and second digital memories, and a first 1-bit analog-to-digital converter. means for generating a fixed frequency clock for the converter;
means for generating a clock capable of varying the frequency of the eight analog converters; means for generating signals for controlling the first and second digital memories; and the output of the first 1-pit digital-to-analog converter. branching means for branching into a plurality of outputs; separation means for separating at least one output branched by the branching means according to a frequency band; and means for controlling amplitude, which receives the output of the separation means as an input. and at least one control means of the means for controlling the amplitude for a short time and the control means for cutting only the high frequency range for a short time, and at least one of the outputs of the branching means.
This configuration includes a time delay means for delaying two outputs, and an addition means for adding the outputs of the control means and the time delay means, thereby making it possible to obtain extremely natural sound quality.

DESCRIPTION OF THE EMBODIMENT FIG. 3 shows an embodiment of the present invention.
Of the 16 and 17 pro blocks divided into blocks, block 1
6 is the pitch conversion device shown in the conventional example, and block 1
7 is a circuit added to reduce distortion generated in the device.

Block 17 will be explained below.

Output signal S of 1-bit digital-to-analog converter 13
5 is a three-branching means 1B that connects a low-nox filter 1 (hereinafter abbreviated as LPF a) 19, a low-nox filter (hereinafter abbreviated as BPF) 20, and a 1-bit analog filter.
It is branched as an input signal to the digital converter 21.

The signal S6 input to the LPFa 19 is converted into an output signal S1 via a muting circuit 22 that reduces the amplitude only for a short time and a first amplitude control circuit 23.

The signal S8 input to the BPF 20 is converted into an output signal S2 via a high-cut muting circuit 24 that removes only high frequency components for a short period of time and a second amplitude control circuit 26.

A signal S input to a 1-pit analog-to-digital converter 21. ' is converted into a signal S3 via a third memory 26 and a 1-bit digital-to-analog converter 27. This output signal S3 is delayed in time with respect to the input signal S6. Further, the signal S3 is converted into a signal S4 via the LPFb 29 and the third amplitude control circuit 30. The 1-bit analog/digital converter 21 and the 1-bit digital/analog converter 27 receive the output signal f3 of the fixed master clock generator 3° write/read clock generator 31.
is input as a clock. The third memory 26 uses the output signal f4 of the fixed master clock generator 3 and the memory control fixed signal generator 32 as a RAS necessary for memory control.
, CAS and WE are input as address signals. Furthermore, the above-mentioned muting circuit 22, high-cut muting circuit 24, the first . second and third amplitude control circuits 23 , 25 ;

3o receives the output f6 of the fixed master clock generator 3, variable master clock generator 9, and muting/amplitude control signal generator 33.

1st. Each output signal S1. of the second and third amplitude control circuits 23.25°30. S2. S3 is added by an adder 34 and outputs an output signal S6 to an output terminal 36.

That is, by controlling the controller 8, the signal SL input to the input terminal 1 is converted into an output signal S5 whose pitch has been converted, and is output to the output terminal 36.

The operation of each circuit will be explained in detail below.In addition, each set value is calculated from the results of experiments.

In Figure 4, LPFa19, BPF20 and LPFb29
0LPFa19 and BPF20 showing the input/output frequency characteristics of
1j: Functions to separate the entire frequency band of the output signal S5 of the 1-bit digital-to-analog converter 13 into a low frequency range and a middle and high frequency range at the frequency F1.

This frequency F1 is set to a value of 50o to 2k)h. Note that the frequency F2 is set to be the same as the cutoff frequency of the LPF that reduces sampling noise, which is essential during digital-to-analog conversion, which is omitted in the embodiment shown in FIG.

LPFb29 works to reduce distortion in the low-mid range, and it is necessary to make its cutoff frequency F3 the same as or higher than Fl.
i is set.

Output signal f of muting/amplitude control signal generator 33
6 controls muting and amplitude control operations. The timing of this operation may be synchronized with the occurrence of regularly occurring distortion. Figure 6 shows the timing at which distortion occurs. When keying down, i.e. lowering the pitch,
This is a case where data written into the memory at the clock fO is read out at a clock fv smaller than fO, and the timing (t2-11) is determined by the clock fO and the memory length M1 as shown in equation (1).

tl-to=(fO)×M1・・・・・・・・・・・・
(1) On the other hand, when keying up, that is, when raising the pitch,
This is a case where data written to the memory with a clock fO is read out with a clock fv which is larger than fO, and the distortion is tl.
In addition to t2..., there is a timing T1. when all read counters become 0. This also occurs at T2..., and its timing (T2-tl) is determined by the clock fv and the memory length M1 as shown in (4).

T2-11=(fv) XMl-, , , , , , , ,
, (,4 Now, the muting circuit 22 functions to mute the level L1 of the output of the LPFa 19 over a short period of time Δt. The timing is shown in FIG.

In addition, Δt is 2 milliseconds to 50 milliseconds, and the level L1 is s
dB or more.

The high cut muting circuit 24 functions to perform high cut at the cutoff frequency F3 for a short period of time Δt2.

FIG. 7 shows the timing. In addition, Δt2 is 0.6 milliseconds - 5 milliseconds, and the cutoff frequency F3 is 1 to 3 kHz.
is set to .

The first amplitude control circuit 23 functions to reduce high frequency distortion generated by the muting circuit 22. FIG. 8 shows the timing of the amplitude control. tl at which distortion occurs
, t2, . . . , the amplitude is controlled for a time Δt3 as shown in FIG. Naturally, distortion occurs at T, , T2.
... are also controlled in the same way. In addition, Δt3 is 10 mm ~
It is set to 50 milliseconds.

The third amplitude control circuit 30 functions to reduce the tremolo feeling that occurs because the output signal S1 of the first amplitude control circuit 23 has large level fluctuations as shown in FIG. That is, Δt
3, the waveform shown in FIG. 9 is expressed as time Δ
A countermeasure was taken by adding t4. If the input signal is the same as that of the first amplitude control circuit 230, then time t1. Since distortion occurs at t2, . . ., a time delay circuit having a delay time Δt6, which is constituted by the third memory 26, is optimally set so that distortion does not occur during the period Δt4. In addition, Δt4 is Δt4 between 20 milliseconds and 60 milliseconds.
Δt6 is set to a value greater than t3, and Δt6 is set to a value greater than % of Δt4 from 10 milliseconds to 60 milliseconds.

The second amplitude control circuit 25 includes a high cut muting 2
It works to reduce the high frequency distortion that occurs in 4.

FIG. 10 shows the timing of the amplitude control. The 0 level is controlled as shown in FIG. 10 for a time Δt6 centering on tl, t2, . . ., where distortion occurs. 0 T1, where distortion naturally occurs. T2... is controlled in the same way. Furthermore, Δt6
is set to 2 ms-30 ms. This Δt5
It is better for It goes without saying that the naturalness can be increased.

As described above, this embodiment focuses on the fact that the distortion waveform generated in a pitch converter having a conventional 1-bit analog-to-digital converter differs depending on the frequency of the input signal, and generates distortion according to the frequency band. By taking measures to reduce noise, it is possible to obtain extremely natural sound quality, and as a result, it can be used in locations where the frequency band of the input signal is wide. In addition, the simple configuration makes it easy to integrate the circuit into an LSI.
Space saving and cost reduction can be realized.0 Effects of the Invention The present invention has an advantage in that an output signal having a pitch different from that of a human input signal can be easily constructed with naturalness. In addition, since the optimal distortion reduction measures are implemented according to the frequency band of the signal, extremely high natural sound quality can be obtained. Therefore, when the frequency band of the input signal is wide, ψ
For example, it is fully compatible with equipment in the Hi-Fi audio field and the mixing field. Furthermore, by converting the digital circuit into an LSi, it is possible to save space and reduce costs, which has tremendous effects.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional pitch converter, Fig. 2 is an output waveform diagram of the same, Fig. 3 is a block diagram of a pitch converter according to an embodiment of the present invention, and Fig. 4 is an input/output diagram of each filter. Frequency characteristics diagram, Figure 6 is a timing diagram showing the occurrence of distortion during key up and down, Figure 6 is an operation timing diagram of the muting circuit, Figure 7 is an operation timing diagram of the IJ high cut muting circuit, and Figure 8 is an operation timing diagram of the IJ high cut muting circuit. 1 to 10 are output signal waveform diagrams of the respective amplitude control circuits. 2.21...1-bit analog-to-digital converter, 3...Fixed master clock generator, 4
...Write clock generator, 5,6.26...
... 1st゜2nd. Third memory, 7...Memory control fixed signal generator, 8...Controller, 9...Variable mactor clock generator, 10
...Memory control variable signal generator, 13, 27
・・・・・・1 bit digital to analog converter, 1
8...3 branching means, 19...LPFa
, 20... BPF, 22... Venting circuit, 23, 25, 30... 1st. Second.
Third amplitude control circuit, 24... No-cut muting circuit, 34... Adder. Figure 4 Ward Breaking Castle Castle Ward Ward Ward φ H Regret Regret Iron

Claims (1)

[Claims] (1) A first 1-bit analog-to-digital converter, a first 1-bit digital-to-analog converter, and a first 1-bit analog to digital converter;
and a second digital memory; and means for generating a fixed frequency clock for the first 1-bit analog-to-digital converter; and a variable frequency clock for the first 1-bit digital-to-analog converter. means for generating a signal for controlling the first and second digital memories; branching means for branching the output of the first 1-bit digital-to-analog converter into a plurality of signals; separation means for separating at least one of the outputs according to a frequency band;
At least one control means out of a means for controlling the amplitude, a means for controlling the short-time amplitude, and a control means for cutting only the high-frequency range for a short time, which inputs the output of the separating means, and each output of the branching means. A pitch converting device comprising: a time delay means for delaying the output of at least one of the two; and a caloric calculation means for adding the outputs of the control means and the time delay means. (The time delay means comprises a 1-bit analog-to-digital converter, a 1-bit digital-to-analog converter, a digital memory, and means for generating a signal to control the memory.) Device.