JPS60186187A - White level stabilizing circuit - Google Patents

Abstract

PURPOSE:To omit a gain control circuit for picture control and simplify circuit constitution by using a gain control circuit which makes a white level adjustment even for picture control. CONSTITUTION:A picture control voltage obtained from a variable resistor 10 is converted by a voltage-current converting circuit 60 into a control current Ic, which is applied to multiplying circuits 62R, 62G, and 62B through a switch 61 and multiplied by gain control signals SWB, SWR, and SWB for white level adjustment. Gain control amplifiers 24R, 24G, and 24B are controlled with their multiplication outputs. Consequently, the signals SWR, SWG, and SWB are multiplied by the picture control current Ic while the switch 61 is on, so a white level adjustment is made while the ratio of SWR, SWG, and SWB is held, and picture control is also performed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a white level stabilization circuit used in an automatic white balance adjustment circuit in a television receiver.

BACKGROUND ART AND PROBLEMS THEREOF FIG. 1 shows a circuit system of a television receiver including a conventional automatic white balance A distortion circuit.

In the figure, a television signal received by an antenna 1 and selected by a tuner 2 is applied to an intermediate frequency circuit 6 and converted into an intermediate frequency signal of a predetermined frequency. is added to the video detection circuit 4 for video detection. The video signal Sv obtained from the video detection circuit 4 is applied to the synchronous separation circuit 5, and the Y/C
In addition to the separation circuit B, the Y signal (luminance signal) and C signal (
chroma signal). The Y signal is applied to a gain control amplifier 7, and the C signal is applied to a gain control amplifier 8 and to a burst gate circuit 9. The gain control amplifier 7.8 is used as a picture adjustment circuit, and the gain is controlled by the control voltage obtained from the variable resistor 10, thereby performing picture adjustment of the Y signal and the C signal. . The picture-adjusted Y signal is level-clamped by a flag circuit 11 and then applied to a matrix circuit 12. The C signal subjected to the vertical picture adjustment is subjected to color adjustment in a color adjustment circuit 16 using a control voltage obtained from a variable resistor 14, and then sent to a color demodulation circuit 15. Further, the color burst signal extracted from the C signal by the birth gate circuit 9 drives a subcarrier oscillator 16, and the subcarrier obtained from this oscillator 16 is sent to a control voltage obtained from a variable resistor 18 in a phase shift circuit 17. After being adjusted, it is applied to the color demodulation circuit 15. The R-Y and 13-Y color difference signals obtained from the color demodulation circuit 15 are sent to the matrix circuit 12.

On the other hand, horizontal and vertical synchronization signals obtained from the synchronization separation circuit 5 are applied to a horizontal deflection circuit 19 and a vertical deflection circuit 20. These horizontal and vertical deflection circuits 19 and 20 generate horizontal blanking pulses HP and vertical blanking pulses VP based on the synchronization signal and apply them to the timing pulse generation circuit 21 and matrix circuit 12, and also generate horizontal deflection signals H1- and A vertical deflection signal vF is generated and applied to the horizontal and vertical deflection coils (not shown) of the cathode ray tube 22.

The timing generation circuit 21 generates an upstream pulse 11P1V i
), a burst extraction pulse is generated and applied to the burst gate circuit 9, and a white timing pulse PW and a black timing pulse PB, which will be described later, are generated and output.

The matrix circuit 12 demodulates R, (), and B color signals based on the C signal, the color difference signal, and the horizontal and vertical blanking pulses I-IP, , VP. These RlGs,
B signal is reference level shift circuit 23R, 26G126B
, a white reference level vsw and a black reference level vsB, which will be described later, are inserted at a predetermined period. Next, in the gain control amplifiers 24R, 24G, and 24B, the gain is controlled by control signals SWRs SWG and SWB, which will be described later, and white level adjustment is performed, and further, in the level shift circuits 25R, 25c, and 25n, the control signals SWRs SWG and SWB, which will be described later, are controlled. A level shift is performed by the control signal SBR%SBGsSBB to perform black level adjustment. By performing the white level adjustment and the black level adjustment described above, the white balance adjustment is performed. It is added to the cathode 27R127G127B of tube 22.

The current flowing through the cathode 27R is the cathode current detection circuit 2.
8□, and this detection signal is applied to sample and hold circuits 29R and 30R. The current flowing through the cathode 27G is detected by a cathode current detection circuit 28G, and this detection signal is sent to sample and hold circuits 29G, 30. added to. The current flowing through the cathode 27B is detected by the cathode current detection circuit 28n, and this detection signal is applied to the sample and hold circuits 29B and 30B.

29B is added as a sampling pulse the black timing pulse PB obtained from the timing pulse generation circuit 21, and the sample hold circuits 30R, 30, .
The white timing pulse pw obtained from the timing pulse generator 21 is added as a sampling pulse 50B.

It is obtained at the timing shown in FIG. In other words, Eitetsu Hakugo S
If the length of the vertical planking gel 4 (indicated by VI3LK) of V is, for example, a 21H period, the pulse PW is applied during the first H period (indicated by IH) from the end of this vertical blanking period. , pulse PB is obtained in the second H period (denoted by 2H). Similarly, the 1H and 2H periods are video periods, but the images are not displayed on the screen.

The pulse PWsPB obtained at the above timing is used as a sampling pulse as described above, and the pulse Pw drives the white reference level generation circuit 55w, and the pulse PB drives the black reference level generation circuit 35B.

As a result, the white reference level generating circuit 53W outputs a white reference level VsW expressed by, for example, a level of 50 to 601RE as shown in FIG.

This reference level V8W is the reference level insertion circuit 23R.
, 25a, and 23B are inserted into the 1H period of the R%G%B signal, respectively. At the same time, the black reference level generating circuit 66 outputs a black reference level VSB expressed, for example, at a level of 5⁻E as shown in FIG. This base J'lA level Vsn is the base level insertion circuit 23.
J 114 by R, 23G,, 23B. They are inserted into the 2H periods of the G and B signals, respectively.

Therefore, if any of the currents flowing through the cathode 27R127G127B changes and the white balance collapses, the reference level VSW inserted in the 1H period and 2H period
% VSB changes and the change in s vsw is detected by the sample and hold circuit OR, 30G130B, and vsn
The change in sample and hold circuit 29.129G 129
Detected by B. and sample hold circuit 30
The detected values of R, 30G, and 30B are detected by differential amplifier 62R13.
2G and 32B, respectively, and the above 50 to 60
11 (, B equivalent to the reference voltage VW is detected. By adding this difference signal to the gain control amplifier 24n s 24 G, 24n as the open side 1 signal 5wn58was Swn, the gain of R1G%B1 Control is performed to adjust the white level.The detected values of the sample and hold circuits 29, .29c, and 29B are output to the differential amplifier 31R.
, 31a, and 51B, respectively, and the 5IRB
A considerable difference from the reference voltage VB can be seen. By applying this difference signal as a control signal 5BRsSBGsSBB to the level shift circuits 25R, 25G, and 25B, the 1(, G, and B signals are shifted to 0) and the black level is adjusted.

According to the above, control loops are configured for the B channel, G channel, and B channel, respectively, and the black level adjustment is performed by these control loops, thereby controlling the cathodes 27R, 27, and so on.

By making the cutoff points of the respective cathode voltage-current characteristics of 27n the same and performing the white level adjustment, the slopes of the respective cathode voltage-current characteristics can be made equal. As a result, the cathode electrodes 27R, 27c,
By maintaining the ratio of the cathode currents flowing through the respective terminals 27a at a predetermined level, the white balance of the screen can be stabilized.

A total of six gain control amplifiers are provided, which makes the circuit configuration complicated. Also, set the picture control to Y.
(Since the No. 8 and C signals are performed separately, the tracking of the gain control may deviate between the Y signal and the C signal.Furthermore, since the input of the color demodulation circuit 150 is gain controlled, the dynamic range is This could result in a lack of color, which could result in saturated colors.

OBJECTS OF THE INVENTION The present invention provides a white level stabilization circuit that solves the above problems.

SUMMARY OF THE INVENTION The present invention uses the gain control circuit for adjusting the white level described above also for picture control. This eliminates the need for a gain control circuit for conventional picture control.
The circuit configuration can be simplified.

Embodiment FIG. 3 shows a circuit in which the present invention is added to a part of the control loop for each channel of 几, G, and B constituting the automatic white balance adjustment circuit of FIG. 1, and the part corresponding to FIG. are given the same reference numerals. Oka: As mentioned above, automatic white balance adjustment is performed by white level adjustment and black level adjustment, and the white level stabilization circuit referred to in the present invention refers to a control loop that performs white level adjustment.

In FIG. 6, a control voltage for picture control obtained from a variable resistor 10 is converted into a control current Ic by a voltage-current conversion circuit 60, and this control current Ic is
1 to the multiplication circuit 62 Rs 62 c s 62, and a gain control signal Sw for adjusting the white level.
Each is multiplied by n%8WRs SWB.

Based on this multiplication output, gain control amplifiers 24R, 24c, 2
4n is controlled. The switch 61 is turned off only when the pulses PW and PB are applied, thereby interrupting picture control during the period in which the reference level V SW %V8B of the G, G, and B signals is inserted.

According to the above, during the period when the switch 610 is on,
Since the control signal 8WR1swc%8WB is multiplied by the picture control current Ic, SwR: Swn: SW
The B ratio is maintained, white level adjustment is performed, and picture control can also be performed. Along with this, the above VSW
Since the control current Ic is cut off during the insertion period of s vsn, only the change in the white level is detected and the control signal SWR is
% S WG s SWB can be obtained.

Therefore, according to this embodiment, the gain control amplifier 7. of FIG.
8 can be omitted to reduce the number of circuit elements and simplify the construction of circuit 4i#. Also, since picture control is performed for the R and 01B signals, no tracking deviation occurs.

Furthermore, since the gain control amplifier 7.8 is omitted, the color demodulator 15 of FIG. 1 has a wide dynamic range.
A signal is input, so color saturation and the like do not occur.゛FIG. 4 shows an example of the specific circuit configuration of FIG. 3, and parts corresponding to those in FIG. 6 are given the same reference numerals.

In the figure, transistors Q11 to Q16, bias
Voltage 'VRj, VB2, resistance R11, R3 and current Io
A gain control amplifier 24R is constructed as is known in the art (11) by using a current source 66 or the like that supplies the current. The Ti quasi-L/g line in FIG.・karaR
A signal is applied to the collector of transistor Q16 to obtain a gain-controlled output voltage VROUT. This output voltage vROUT Fi is applied to the level shift circuit 25R of FIGS. 1 and 3. Other gain control amplifier 24G,
24B is configured in the same way, and the C signal and B signal are applied to each, and the output voltage vcou'r s VRO
UT is obtained. The multiplication circuit 62R162c, 62
B are transistors Q17IQ1BlQ24 and Q, respectively.
191 Q20. Q25, Q211Q22+ Q26
It is constructed as shown in the figure. Then, bias voltage ■1 is applied to one transistor Q17, Q19, Q21, and the other transistor Q1B, Q20'% Q
The control signals 5WRs, 5WGs, and SWB are added to 22 and compared with the above signals.

On the other hand, the voltage-current conversion circuit 60 has positive and negative control currents I
This current Ic is applied to the collector of transistor Q23 through switch 61. A current 2 is further applied to this collector from a current source 64. This transistor Q23 constitutes a current mirror circuit together with the transistors Q24 to Q26.

According to the above configuration, the gain GR of the gain control amplifier 24R is input to the input signal R signal /I/1-vRlNl output'
Suppressing the VnouTs) transistors Q+7, Q16
If the emitter current of is 1, the gain is controlled by 1 or In. The above current (1) passes through a shunt circuit consisting of transistors Q17 and Q+a and becomes a current (3), and this current (15) flows through the transistor Q24 which serves as the current sowing of the current mirror circuit. The current 15 of this current mirror circuit is generated during the period when the switch 61 is off, that is, during the insertion period of the reference level VSW5VSB.
It is fixed at 2 and becomes I2+Ic during other periods. If the potential difference between the bases of the transistors Q17 and Qle of the above-mentioned shunt circuit is Vc, then the following equation is obtained. Therefore, ■3 is (Vc
-Vv), that is, it will be divided according to the SWR.
, ■The ratio between 1 and I5 is constant and does not change even if I5 changes.

By performing the above operations in the same manner for each of the R, G, and H channels, automatic white level adjustment is performed to stabilize the white level and picture control is performed. In this case, the control signal SWR% of different levels 8WG
By providing s AWB, picture control can be performed without changing the gain ratio even if the gains differ for each channel.

Effects of the Invention According to the present invention, the circuit configuration of the receiver can be simplified. Also, since picture control is performed on the RlG and f3 signals, no tracking deviation occurs. Furthermore, since a C signal with a wide dynamic range is input to the color demodulator, color saturation λD4(f does not occur).

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a television receiver including a conventional automatic white balance adjustment circuit to which the present invention can be applied, FIG. 2 is a timing chart of FIG. 1, and FIG. 3 is a circuit diagram showing an embodiment of the present invention. , H44 is a circuit diagram showing a specific example of the circuit shown in FIG. In addition, in the symbols used in the drawings, 10...... Picture adjustment variable resistors 24R, 24G, 24B... Gain control amplifier 6
1......Switch 62□, 62G1
62B...Multiplication circuit 8WRx 5WGS"'WB"
'Gain control signal. Agent Masaru Ueya Yoshio Tsune (voluntary) procedural amendment (1), received in May 1980! Dear Commissioner of the Japan Patent Office,
32 "3° 221゛0°) ¥, f+; White level stabilization circuit and 3, '1fli correction (relationship with '1 Patent applicant Tokyo, IT + Shinagawa Shinayo, Shinagawa Shinayo 6 guns) 1.1 '7rl'
i3': No. 5 (218) Sony (J Koshiki Company' 5, day of extraction order) (shipment date) Showa year, month, day 6
? The line 4 to 1 from the bottom of page 13 of the detailed specification of investigation, which is increased by 1llj, is corrected as follows: ``1--...No change.'' Note 3 11- Upper Vc &T i+e. Therefore, 11 is proportional to Ve, i.e., 5WR1, which is variable depending on f'C, I's. ” - the above

Claims (1)

[Scope of Claims] A white level stabilizing circuit in which a gain control circuit is provided for each channel of 1, R, and 10SB, and each gain control circuit is controlled in a closed loop according to the cathode current of each channel, A white level stabilizing circuit in which each of the gain control circuits is commonly controlled by the cathode current and the picture control signal. 2. inserting a white reference level into a predetermined period of each color signal of f(, G, B), detecting the cathode current of each channel during the predetermined period, and