JPS60186171A - Television receiver - Google Patents

Abstract

PURPOSE:To remove unnecessary pulses and to perform a double-speed non-interlaced scan accurately by outputting pulses from a horizontal synchronous separating circuit only in a horizontal blanking period after double-speed interlaced processing. CONSTITUTION:A video signal outputted from an amplifying circuit 2 have horizontal synchronizing pulses PH separated to generate double-speed horizontal synchronizing pulses P'2H, and gate pulses G1 are generated. Those gate pulses G1 are supplied to the synchronous separating circuit 15 to output pulses after synchronous separation processing only while gate pulses G1 are obtained. Consequently, unnecessary pulses PN mixed during a double-speed horizontal period are removed and only double-speed horizontal synchronizing pulses P2H are supplied to a horizontal deflecting circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a Chi Vision receiver suitable for use in double-speed non-interlaced scanning.

A color television receiver has been developed that obtains high-resolution images through double-speed non-interlaced scanning.

FIG. 1 is a system diagram showing an example of such a receiver, and this example shows a case in which luminance signals and color signals are digitally processed.

In the figure, a television signal is supplied to an A/D converter (3) via a tuner (1) and a video intermediate frequency amplification circuit (2), where it is digitally converted. This digital television signal is supplied to a Y/C separation circuit (4) and separated into a digital luminance signal YD and a carrier color signal CD. The signals (RY)D and (B-Y)D are demodulated.

The digital luminance signal YD that has passed through these and the delay element (6) is supplied to the digital signal processing circuit (7), and a digital luminance signal YD that has been subjected to double-speed non-interlace processing as described later and a pair of digital color difference signals (R-Y). D, (B-Y
) D is formed.

After these are converted into analog signals by a D/A converter (8), they are supplied to a matrix circuit (9) where primary color signals) l,
G and B are formed, and these are supplied to the color picture tube α through the output circuit (ill. The D/A converted luminance signal Y is further supplied to the synchronization separation circuit 05) to double the horizontal frequency. The horizontal synchronizing pulse P2H having (fH) is separated and supplied to the horizontal deflection circuit (I6) to form a horizontal deflection signal of 2fH, which drives the horizontal deflection circuit 1° αn.

With this configuration, double-speed non-interlaced scanning is performed to reproduce a high-resolution color image.

FIG. 2 shows an example of the digital signal processing circuit (7), and in this example, three IH (H is horizontal period) memories (20A
) to (20C) are provided, and each digital luminance signal Y
D is supplied, and v'! of 4fSC (fsc is the subcarrier frequency) is obtained from the address counter (19) in this example. : The 11th order is stored for each horizontal line using the write clock Cw, and sequentially read out using the read clock cR selected to have twice the write clock frequency.

The readout outputs of the memories (20A) to (20C) are supplied to the switching circuit (2 outputs) and the memory (20A)
, (20B) are supplied to the first adder 1) and combined, and then supplied to the - first attenuator (221) to form a non-interlaced interpolated signal. Similarly, between memory (20B) and (20C) and (20C)
Second and third adders t23 are installed between 0C) and 20A, respectively.
) (25+ and attenuator (24126+) are provided to form interpolation signals for non-interlacing to be inserted between the respective horizontal lines, and these are switched in a predetermined order in the switching circuit (2 swords). A digital luminance signal (using YD) for double speed non-interlaced eclipse is generated.

A pair of digital color difference signals (R-Y)D, (B-Y
) D is also subjected to similar signal processing.

By the way, some receivers (IO+) configured in this way are equipped with a means to change the sharpness in the vertical direction (V-sharpness).■Sharpness is, for example, the sharpness of horizontal stripes as shown in Figure 3A. When there is an image S, it is said to sharpen the image by emphasizing each boundary part (contour), and since the image S in Figure A is expressed by the luminance signal Y as in Figure B, the contour By emphasizing the signal level of the part in the direction of the arrow shown in Figure C, therefore, the black part becomes blacker and the white part becomes whiter, so the ring 'flI is emphasized. An image S is obtained.

Such sharpness processing is performed for each row in the Y/C separation circuit (4). In other words, this Y/C separation circuit (
In 4), a comb filter using two IH delay elements is generally used to eliminate dot interference. On the other hand, ■Sharpness processing is performed using two IHs connected in series.
A delay element is used, and the IH and 2H delayed signals and the current signal can be appropriately weighted and then combined, so in general, the delay element of the Y/C separation filter is used. The circuit is configured at ℃・ru.

However, in this way, in the Y/C separation circuit (4), ■
When sharpness processing is performed, the following disadvantages occur.

For convenience of explanation, FIG. 5 shows the signal waveform of the device shown in FIG. 1 in the form of an analog luminance signal, and IA in FIG. 5 shows a normal luminance signal Y that has been subjected to double-speed non-interlace processing. If this luminance signal Y is subjected to sharpness processing, the luminance signal Y shown in FIG. 2B is obtained.

is also a black signal whose level is emphasized in the negative direction, and this black signal YB is further emphasized toward the black level side than the pedicle level.

From the D/A converter (8), the outline part is strong 17 like this
Since the luminance signal Y converted to 1 is output, by passing it through a no-pass filter (not shown) provided in the horizontal synchronization separation circuit (15), a pulse as shown in FIG. 6C is obtained. . Therefore, as shown in the figure, in addition to the horizontal synchronizing pulse P2H, the waveform-shaped pulses include the black signal Y.
An unnecessary pulse PN based on the falling edge of B is also separated, and as a result, there is a possibility that the horizontal deflection circuit μD malfunctions due to this unnecessary pulse PN.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to reliably remove such unnecessary signals included in the horizontal period, thereby making it possible to accurately perform double-speed non-interlaced scanning.

Summary of the Invention Therefore, in the present invention, pulses are output from the horizontal sync separation circuit (15) only during the horizontal blanking period after double-speed non-interlace processing (therefore, the period is 4 times the normal horizontal period). It was designed so that

Due to this, unnecessary pulses P included in the horizontal scanning period
Since N is removed, there is no possibility that the horizontal deflection circuit will malfunction due to this unnecessary pulse PN, and double-speed non-interlaced scanning can be performed accurately.

Embodiment Next, a case in which the television receiver according to the present invention is applied to the above-mentioned television receiver subjected to digital signal processing will be described in detail with reference to FIG. 6 and subsequent figures.

However, the same reference numerals are given to the parts corresponding to those in FIG. 1, and the explanation thereof will be omitted.

In FIG. 6, the television signal (video intermediate frequency signal) output from the amplifier circuit (2) is supplied to the horizontal synchronization separation circuit (31) to separate the horizontal synchronization pulse pH of rH, which is sent to the AFC circuit C321. is supplied to 2fH
A double-speed horizontal synchronizing pulse P2H is formed, which is supplied to the first monomulti E to form the gate pulse G1 shown in FIG. 5E. The generation timing and pulse width of the gate pulse G1 are selected so as to include the double-speed horizontal synchronizing pulse P2H included in the luminance signal Y output from the D/A converter (8).

This gate pulse Gl is supplied to the synchronization separation circuit (15+), and the pulse subjected to the synchronization separation process is output only while the gate pulse G1 is obtained.As a result, unnecessary pulses PN mixed within the double speed horizontal period are removed. Therefore, only the double-speed horizontal synchronizing pulse P2H (FIG. 5F) is supplied to the horizontal deflection circuit (161).

Therefore, even if sharpness processing is performed before D/A conversion, there is no disturbance in the horizontal deflection system, and it is possible to correctly reproduce a high-resolution image by correct double-speed non-interlaced scanning.

The pulse width W1 of the gate pulse G may include at least the horizontal synchronizing pulse p2H, but this pulse p2
Since the period H is a normal horizontal period, in this example, it is selected to be approximately one half of the normal horizontal blanking period (horizontal blanking period after double speed processing).

In FIG. 6, (4) indicates a clock forming circuit, and the double-speed horizontal synchronizing pulse P'2H output from the AFC circuit (321) is supplied to the VCO (4 rsc clock synchronized with this). is formed and this is the counter 0
2) and synchronized to the input television signal.
A write clock ql of rsc is formed. In addition, the above-mentioned double-speed horizontal synchronization pulse P'2H and the synchronization separation circuit (15)
The double-speed horizontal synchronizing pulse P2H output from supplied with 8 rsc
A read clock CR is generated.

By the way, the above-mentioned gate pulse G1 is obtained with a period of zfH, and its pulse width is equal to that of the double-speed horizontal synchronizing pulse P2.
Since it is necessary to gate H correctly, a pulse width several times that of this P2H pulse width must be selected, for example, the horizontal blanking width after double speed processing as described above. If such a pulse width is selected, there will be jitter in the input television signal, and if the timing at which gate pulse G is obtained varies according to this jitter, even the unnecessary pulse PN adjacent to pulse P2)1 will be gated. There is a risk of

In order to eliminate this drawback, a solution to the problem is also provided in FIG.

Therefore, the horizontal synchronization Hals PH of rH output from the horizontal synchronization separation circuit Gυ is supplied to the second monomulti (5o) to generate the gate pulse (inhibition pulse) G2 shown in FIG. 7B.
is formed, and the V sharpness processing operation is prohibited only in the first video signal section.

It should be noted that, for convenience of explanation, FIG. 7 shows the cycle after double-speed non-interlace processing.

The gate pulse G2 is selected to have a pulse width W2 (WB is the horizontal blanking period) that is slightly wider than the horizontal blanking pulse, and the timing is such that the rising portion of the luminance signal Y is included in the latter half of the gate pulse G2. It is set to be output as . As a result, the rise of the luminance signal Y is temporally delayed by the period during which the gate pulse G2 exists, so even if the above-mentioned sharpness processing and double-speed non-interlaced scanning processing are performed, An unnecessary pulse PN is generated (C-E in the same figure). Therefore, even if the timing of generation of the gate pulse G1 varies due to jitter, the unnecessary pulse PN will not be gated by the gate pulse G1 (FIG. 12F and G).

As described in detail, according to the configuration of the present invention, in a device that performs double-speed, a, and tarlace processing, even if sharpness processing is performed at a stage before D/A conversion, this processing It has the feature that non-interlaced scanning is not disturbed by 1+, and high-resolution images can be reproduced at all times.

[Brief explanation of drawings]

FIG. 1 is a system diagram of a television receiver used to explain the present invention, FIG. 2 is a system diagram of a digital processing signal circuit, and FIG.
5 are waveform diagrams for explaining the operation, FIG. 6 is a system diagram showing an example of the television receiver according to the present invention, and FIG. 7 is a waveform diagram for explaining the operation. (7) is a digital signal processing circuit, (4) is ■Y/C separation circuit with sharpness processing function, (151C3υ is a synchronous separation circuit, G31 t50) is a gate pulse Gl
+ This is a mono-mulch for forming 02. Same as Hidemori Matsukuma! I.J.

Claims (1)

[Claims] In a television receiver that performs double-speed non-interlace processing after contour correction, the luminance signal that has been subjected to double-speed non-interlace processing is supplied to a horizontal synchronization pulse separation circuit, and the 2fH (fH is horizontal frequency) horizontal synchronization signal is synchronized and separated. A pulse is supplied to the horizontal deflection circuit to form a 2fH horizontal deflection signal, and a gate pulse is supplied to the separation circuit to gate the horizontal blanking period of /water period to be included in the horizontal scanning period. A television receiver in which unnecessary signals supplied to the separation circuit are removed.