JPS60185431A - Digital signal converter - Google Patents

Abstract

PURPOSE:To simplify the device constitution by detecting a special input train so as to change a code train thereby eliminating the need for handling a state vector and an uncertain code train. CONSTITUTION:When the i-th and the (i+1)-th input trains are inputted, a 4-bit data is impressed to a coder 2C. The coder 2C outputs a control signal S of a 3-bit code train corresponding to a 4-bit data based on the coding rule. The control signal S is delayed and becomes a reset signal for registers 3C, 4C. Thus, when the control signal S is logical ''0'', the code train Ci is unchanged and outputted via the register 3C. When the control signal S is logical ''1'', the code train is reset and changed into ''000''.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital signal +j conversion device used for magnetically recording digital data.

Conventional Structure and Problems Conventionally, the one shown in FIG. 1 has been known as a 273 code conversion device for converting a 2-bit digital data string into a 3-bit code string.

This device has a register 1A that temporarily holds a 2-bit input string A, an encoder 2A that includes an output logic circuit for code conversion, and a state vector that monitors the current encoding state. Register 3A and output 3-pin code string B
-i, and a temporary holding register 4A.

A 2-bit human input string A is held in register 1A and input to encoder 2A together with the value of the state vector held in register 3A. In the encoder 2A, predetermined encoding is performed according to the conversion diagram shown in FIG. 2, and corresponding to the values of the input string A and the state vector is output. The output code string B is held in the register 4A, and the new state vector X' is held in the register 3A. The following operations are sequentially and repeatedly performed in synchronization with the 2-bit input string A.

However, in this signal conversion device, as mentioned above, it is necessary to feed the state vector in addition to the input string, and the encoding of a particular input string is performed using the state vector as shown in the conversion diagram in This is done by selecting one of five types of code strings. This complicates the encoding process and causes the problem that the input string and the code string do not uniquely correspond.

This problem will be explained in detail. In the device mentioned above, there are only five types of patterns shown in FIG. 3 as the 3-bit output code string B, and a certain code string is, for example, "001".
When the last bit ends with ``1'' as in the case of ``1'', the code is converted so that the beginning of the next code string always starts with ``O''''. For this purpose, a 2-bit input string “00”,
"01", "10".

There are only three types of code strings that can be assigned to the four types of “11′”: “000”, “001”, and “010”. Also, if '000' is assigned to a code string of a certain 2-bit input string and shuffled, an endless series of '○' will be output.For these reasons, it is necessary to feedback two consecutive state vectors. This has caused the above-mentioned problems. Conventionally, there are also known devices that perform code conversion without using a series of state vectors. FIG. 4 is a code conversion diagram showing the operation of the device. As shown in this figure, this is a device that performs a combination of conversion of a 2-bit input string to a 3-bit code string and conversion of a 4-bit input string to a 6-bit I code string.

In Fig. 4, there is a code string whose first bit is marked 'X''. This It
++ −′+ Ol″, and if it is ’0′″, it is X
Convert it so that it becomes +lu-u 1 IT, If I I
Efforts are being made to prevent T-bic from occurring consecutively.

However, even when such conversion is performed, the apparatus is complicated because the encoding of a particular input string is output as a code string with an indeterminate (Pino) It X 11.

When the last input string ends with the first data "oo" in the 4-bit encoding shown in Figure 4, since the encoding is done with a variable length of 2 bits or 4 bits, , a new problem arises in that the code string generation is inefficient.

Purpose of the Invention The present invention was made in view of the conventional problems described above, and its purpose is to enable encoding operations even within a finite number of input data strings, without depending on the encoding state. The object of the present invention is to provide a digital signal conversion device that can easily perform encoding processing.

Structure of the Invention The digital signal converter of the present invention performs the i-th encoding based on a 4-bit totator consisting of the i-th 2-bit input string and the (1→-1)-th 2-bit input string.

At the same time, special data of the 4-bit data is detected, and the (1+1)th code string is changed to a predetermined code based on the detection signal.

As a result, the code rate 2/3 obtained by dividing the encoded digital signal string by adjacent '1' i1 to seven degrees o' is subjected to code conversion.

DESCRIPTION OF THE EMBODIMENT FIG. 5 shows a code rate of 2/3 according to an embodiment of the present invention.
1 shows a schematic configuration of a digital signal conversion device. This device has a register 1C that temporarily holds a 2-bit input string I, and an i-th (i
=1.2,3. ) input string ■1 and the latest (i+1)
an encoder 2C that generates the i-th 3-bit code string C1 based on the ith input string 11+1; a register 3C that temporarily holds the 3-bit code string output from the encoder 2C; It is equipped with cascade-connected registers 4C and 5C of 1 bit each to which a control signal S output simultaneously with the code string C1 is applied, and the circuit is connected so that the output of register 6C becomes a reset signal for registers 3C and 40. has been done.

Without further ado, the principle of the conversion operation of the above device will be explained.

In this invention, considering the encoding of continuous input strings, the sixth
The input string is encoded according to the basic encoding diagram in the figure, but as shown in the encoding diagram in Figure 7, it begins with ``■''.
In order to avoid successive It I II bits, only the 5th column of codes uses "P○00", which is not used in the basic encoding diagram of Figure 6, and is shown in the encoding table of Figure 8. XXX0
Perform an operation to change the code string to a code string of the form O○'''.Thus, the last bit 'I□ necessarily becomes °'○'', and the next input string is the basic encoding diagram shown in Figure 6. 1 or according to the encoding shown in FIG.

The above-mentioned special encoding "xxxooo" is the encoding that is performed when there is a special input string next to the input string in the encoding of consecutive input strings. After this encoding of "x x x o o o" is performed, the encoding operation always returns to the basic encoding diagram of FIG. 6 and the encoding diagram of FIG. 8.

Basically, the code conversion shown in Figure 6 is performed.
In order to detect the continuous input string of 4 bits shown in Figure 8, the total of 4 bits of the 1st input string and
The configuration is such that the bits are input to the encoder 2C.

FIG. 10 shows the state transition of this signal conversion device.

In this figure, the dotted line indicates the case where the above-mentioned special encoding is performed, and X'' indicates the beginning of the code string.

The same applies to decoding, and basically continuous code strings are decoded according to Fig. 6, but Fig. 8
By detecting "XXX0OO" shown in the figure, the above-mentioned special encoding process can be decoded without any problem.

The operation of the configuration shown in FIG. 5 will be explained in detail. When the first input string 11 is held in the register 1C and the next (i+1)th input string I, □, 1 is input, the encoder 2 CI
A total of 4-bit takes of iCId I i and 11+1 are applied.

The encoder 2C performs Ii and □ based on the encoding diagram of FIG. A control signal S of a 3-bit code string C1 and a code string C1, corresponding to 4-bit data of 1 is output. This control signal S is delayed by registers 4c and tsC and becomes a reset signal for registers 3c and 4C. Therefore, when the control signal S of '0'' is continuously output from the encoder 2C, the code string C1 output from the encoder 2C is not changed at all and is output via the register 3Ci.

The control signal S becomes "1" when a special input string shown in FIG. 8 is detected. This 5-tl 1
When It reaches register 5C, at this time register 3C
The code string C1+ held in is changed to oo
o". At the same time, register 4C is also reset, so the code string CI+2 following "000" is changed from the basic encoding diagram 1 in Figure 6 or the encoding diagram in Figure 8. is output without being

In other words, the input columns i+1 and i+2 are both special input columns in FIG. 8, and the encoder 2C uses the control signal S='M
Even if `` is output twice in a row, the output from register 5C resets register 4C and outputs 2, so the code string C
1+1 is changed to ' o o o ', but the code string C1+2 is outputted up to its '-1'.

As is clear from the explanation of ``Effects of the Invention'', this invention has 10 advantages.
, pay attention to the consecutive takes of the 1st input string and the (1+1)th input string, detect only the special input strings using a predetermined encoding table, and change the corresponding code string with l ~. Since this circuit processing is carried out, it is possible to easily recognize the code created by special encoding.
There is no need to handle state vectors or uncertain code strings during encoding, and the device configuration can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the entire configuration of a conventional 2/3 digital signal conversion device, FIGS. 2 and 3 are coding diagrams and code string diagrams for explaining the operation of the device in FIG. 1, and FIG. 5 is a block diagram showing the configuration of a 2/3 digital signal conversion device according to an embodiment of the present invention, and FIGS. 6 to 9 are coding diagrams of another conventional device. FIG. 10 is a state transition diagram of the apparatus shown in FIG. 6. 1C register, 2C-・ladder, 3C・register, 4C
and 5C...1 bit register. Figure 1 Figure 9A Figure 2 Figure 3 Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] Adjacent '1's in the encoded digital signal string are 1 to 1.
This is a device that performs code conversion with a code rate of 2/3 divided by 7 degrees 0'', which accepts a 2-bit input string and 1
means for sequentially obtaining a 4-bit input string consisting of the 2-bit input string of the first bit and the (]+1)th input string; and encoding means for generating the first code string based on the 4-bit data;
A storage means for temporarily storing the string of symbols outputted from the encoding means, a means for detecting special data from the 4-bit data, and a detection signal (F) of the detection means is temporarily activated. i+1)-th code string to a predetermined code string V
'C changing means.