JPS60184322U - variable impedance circuit - Google Patents

variable impedance circuit

Info

Publication number
JPS60184322U
JPS60184322U JP7138284U JP7138284U JPS60184322U JP S60184322 U JPS60184322 U JP S60184322U JP 7138284 U JP7138284 U JP 7138284U JP 7138284 U JP7138284 U JP 7138284U JP S60184322 U JPS60184322 U JP S60184322U
Authority
JP
Japan
Prior art keywords
variable impedance
impedance circuit
transistor
resistor
resistor connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7138284U
Other languages
Japanese (ja)
Inventor
山中 勉彦
市塚 悟
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP7138284U priority Critical patent/JPS60184322U/en
Publication of JPS60184322U publication Critical patent/JPS60184322U/en
Pending legal-status Critical Current

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  • Networks Using Active Elements (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図、第2図および
第3図は第1図の特性例図、第4図は第1図の使用例を
示す回路図、第5図〜第7図は第4図の動作説明図、第
8図および第9図は従来の回路側図、第10図は第9図
の特性例図である。 Q工・・・トランジスタ、R□v R2・・・抵抗、R
3・・・定電圧源。 「□」− [−− ↑゛ニ ー        V
Fig. 1 is a circuit diagram showing an embodiment of the present invention, Figs. 2 and 3 are characteristic examples of Fig. 1, Fig. 4 is a circuit diagram showing an example of use of Fig. 1, and Figs. 7 is an explanatory diagram of the operation of FIG. 4, FIGS. 8 and 9 are side views of conventional circuits, and FIG. 10 is a characteristic example diagram of FIG. 9. Q engineering...Transistor, R□v R2...Resistor, R
3... Constant voltage source. “□”− [−− ↑゛nee V

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] トランジスタと、トランジスタのエミッタに直列接続さ
れた第1の抵抗と、トランジスタのコレクタとエミッタ
との間に並列接続された第2の抵抗と、トランジスタの
ベースと第1の抵抗との間゛  に並列接続された定電
圧源とで構成されたことを特徴とする可変インピーダン
ス回路。
a transistor, a first resistor connected in series to the emitter of the transistor, a second resistor connected in parallel between the collector and emitter of the transistor, and a resistor connected in parallel between the base of the transistor and the first resistor. A variable impedance circuit comprising a constant voltage source connected to the variable impedance circuit.
JP7138284U 1984-05-16 1984-05-16 variable impedance circuit Pending JPS60184322U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7138284U JPS60184322U (en) 1984-05-16 1984-05-16 variable impedance circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7138284U JPS60184322U (en) 1984-05-16 1984-05-16 variable impedance circuit

Publications (1)

Publication Number Publication Date
JPS60184322U true JPS60184322U (en) 1985-12-06

Family

ID=30608828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7138284U Pending JPS60184322U (en) 1984-05-16 1984-05-16 variable impedance circuit

Country Status (1)

Country Link
JP (1) JPS60184322U (en)

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