JPS60182816A - M series code generator - Google Patents

Abstract

PURPOSE:To prevent a thin and high pulse from being generated by changing the position of a code extracting part so as to eliminate the use for a code length designating section and an output selection section. CONSTITUTION:A code generating section 1 is constituted by combining a multi- stage shift register 2 formed by coupling sequentially plural FFs 21-27 and a feedback logical circuit 3 feeding back the logical coupling of each stage output of them to the 1st stage FF21. The code extracting section is set to an intermediate output stage (1st output stage) of the multi-stage shift register 2 so as to extract an M series code having a code length (2<n>-1) in response to the number of stages (n) of the shift register 2. Even if a feedback input to the FF21 includes a thin and high level pulse, since the FF21 is latched in the timing just before the thin and high level pulse is applied, the thin and high level pulse is eliminated at a Q output of the FF21. The switching of the code length is realized easily by changing data content to be latched at a feedback value setting section 8.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a code generator applied to a communication system such as spread spectrum communication. The present invention relates to an M-sequence code generator used to generate the longest sequence code (hereinafter referred to as "M-sequence code").

<Background of the Invention> As shown in FIG. 4, a conventional code generator of this type includes a code generation section 1 consisting of a combination of a multi-stage shift register and a feedback logic circuit, a clock supply section 6, an initial value setting section 7, and a feedback value. It is configured by adding a setting section 8, etc., and extracts an M-sequence code with a code length corresponding to the number of stages of the shift register from the final output terminal of the multi-stage shift register (known technical document: [Spread Spectrum Communication System JR, Written by C, D 1xon,
Jacik Publishing). Incidentally, in recent years, in order to promote encryption in communication systems, there has been a demand for a system that can dynamically change the code length of the code. In order to meet such demands, conventionally, a code length designation section 10 for designating the code length of the code to be extracted, and an output selection section 11 for selecting the code output stage of the multi-stage shift register based on the designation of the code length. is provided, and the M-sequence code of a desired code length is extracted from the selected output stage. Therefore, according to the conventional method, a code length specifying section 10 and an output selecting section 11 are required, which increases the number of circuits and circuit wiring of the code generator, leading to a complicated circuit configuration and an increase in the cost of the device. There were disadvantages such as

Therefore, the inventor developed an M-sequence code generator having the circuit configuration shown in FIG. 5, which eliminates the need for the code length designation section and output selection section. The code generator shown in the figure consists of a code generation section 1 consisting of a multistage shift register 2 and a feedback logic circuit 3, a clock supply section 6, an initial value setting section 7, and a feedback value setting section 8. A code extraction section 5 is set at the feedback input section to the register 2. In the case of the circuit shown in FIG. 5, the number of circuits and wires can be reduced compared to the conventional example, and the circuit configuration can be simplified and the cost of the device can be reduced. However, when the M-sequence code extracted from the code extraction unit 5 is analyzed, as shown in FIG. 6, whisker-like pulses P+ r P2 are generated at various locations in the signal waveform, and these pulses may cause system malfunction. Some problems arose.

<Object of the Invention> The present invention provides an M-sequence code generator that eliminates the need for the code length designation section and output selection section and prevents the generation of whisker-like pulses by changing the position of the code extraction section. The purpose is to

<Structure and Effects of the Invention> In order to achieve the above object, the present invention eliminates the need for the conventional code length designation section and output selection section and eliminates the need for the conventional code length designation section and output selection section by setting a code extraction section in the intermediate output stage of the multistage shift register. The generation of pulses was prevented.

According to the present invention, the number of circuits and wires can be reduced compared to the conventional example, simplifying the circuit configuration and reducing the cost of the device, and completely preventing system malfunctions due to whisker-like pulses. It achieves the excellent effect of achieving the purpose of the invention.

<Description of Embodiments> FIG. 1 is a circuit block diagram of an M-sequence code generator according to the present invention, and FIG. 2 shows a specific example of the circuit.

In the illustrated example, the code generator 1 includes a plurality of 7-lip codes.
It is constructed by combining a multi-stage shift register 2 formed by sequentially connecting 70-tubes 21 to 27, and a feedback logic circuit 3 that feeds back the logical combination of the outputs of each stage in the multi-stage shift register 2 to the first stage flip/70-tube 21. In the invention, the code extraction section 5 is set at the intermediate output stage (first output stage in the illustrated example) of the multi-stage shift register 2, and the shift register 2
An M-sequence code with a code length (2-1) corresponding to the number of stages n is extracted. The feedback logic circuit 3 is composed of gate circuits 31 to 37 that input the outputs of each stage of the shift register 2, and exclusive OR circuits 41 to 46 that input each gate output and the logical combination output from the subsequent stage. The open/close states of each of the gate circuits 31 to 37 are set by a feedback value setting section 8, which will be described later.

The clock supply unit 6 supplies a clock of a predetermined frequency (for example, 3.2 MHz) output from a crystal oscillator (not shown) to each of the flip-flops 21 to 27 of the shift register 2 via a gate circuit 61. The gate circuit 61
are controlled to open and close by the latch circuits 62 and 63, and the latch operation of each latch circuit 62 and 63 (in the illustrated example, the data bus D
latching the contents of o) is controlled by start signal (1) and stop signal (2).

The initial value setting unit 7 is a circuit for directly initializing each of the seven flip-flops 21 to 27 of the multistage shift register 2, and opens the buffers 71, 72 with the initial set signal I3, and connects the data bus D. -, the contents of D6 are output to each of the flip-flops 21-27.

The feedback value setting unit 8 is a circuit for setting the calculation mechanism of the feedback logic circuit 3, in other words, the logical combination state of each stage output in the shift register 2, and connects the data bus D with the feedback tap signal I4.

The contents of ~D6 are set in the latch circuit 81, and the open/close states of each of the gate circuits 31-37 are determined based on the contents of this latch data.

The operation of each part of the circuit is controlled by a main control section 9 including a computer, and this main control section 9 controls each of the above-mentioned signals 1 to I.
4 and executes M-sequence code generation processing.

When the data bus Do is at logic "1" and the other data buses D1 to D6 are at logic rOJ, the initial stage is set.

When the gates of the buffers 71 and 72 are opened by the input signal I3, the shift register 2 transfers each data field D. -D6
It is initialized based on the data content of , flip/70 knob 21 is logic "1", other flip/70 knobs 22 to 2
7 becomes the q output of logic "0".

Next, data buses Do and D5 are at logic "1", data buses D1 to D4 . Assuming that these data contents are set in the latch circuit 81 by the feedback tap signal 4 when D6 is logic "0", the feedback logic circuit 3 indicates that the gate circuits 31 and 36 are "gate open" and the other gate circuits are "gate open". 32-3
5.37 is set to the "gate open" circuit state.

In this manner, when the start signal 11 is sent out in the above state and the logic "1" data on the data bus DO is set in the latch circuit 81, the next start/unnch circuit 63 is set and the gate circuit 61 is opened. . As a result, the clock is simultaneously supplied to each flip-flop 21 to 27 of the shift register 2, and in this case, the code extraction unit 5 outputs an M-sequence code with a code length of 26-1 as rllllllol, 010.
1100110111...'' are sequentially output. In the conventional method in which the final output stage of a multi-stage shift register is used as a code extraction section, the code arrangement is roooooolllolololollo starting from the initial setting state.
olloll...'', resulting in a 6-bit phase shift with the method of the present invention, and furthermore, in the example shown in FIG.
ollooolloll...'', and a 1-bit phase shift occurs between the system and the method of the present invention, but such a phase shift can be easily corrected by a program if necessary.

FIG. 3 shows a timing chart of the above circuit. In the figure,
■ is the clock, 5tx S6 is the output of each stage of the multistage shift register 2, D, , D2. D3 indicates the output power and output of the final exclusive OR circuit 41 in the feedback logic circuit 3. In the embodiment, the gate circuits 32 to 35 are
Since the gate circuits 31 and 36 are set to "gate open", the output signals 52 to S11 are not fed back, and only the output signals s and I s6 are fed back. As a result, the output signal S passes through one gate circuit 31 and becomes the input signal Dl to the exclusive OR circuit 41, and the output signal S6 passes through one gate circuit 36 and five exclusive OR circuits. 46, 45, 44. ．． Input signal D2 via 43.42
becomes. Normally, each time a signal passes through this type of logic circuit, a certain time delay t occurs, so the input signal is
A time delay t (=5 t ) occurs between D2. Therefore, the output signal D3 of the exclusive OR circuit 41 has a part where the logic changes from "1" to "0" to "1" due to this time delay, and when this output signal D3 is taken out as a sign output. In this case, the above-mentioned changing portion appears as a whisker-like pulse. However, as in the present invention, the multi-stage shift register 3
When taking out the code output from the intermediate output stage (for example, the first output stage), even if the feedback input to the flip-flop 21 includes the whisker-shaped pulse P, the flip-flop 21 will Since the latch operation is performed at the immediately previous timing, the whisker-like pulse P disappears at the q output of the flip-flop 21.

In order to stop the code generation, the stop signal 2 closes the gate circuit 61 via the latch circuits 62 and 63, and stops supplying the clock to the shift register 2. Further, switching of the code length can be easily realized by changing the data content latched in the feedback value setting section 8.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an M-sequence code generator according to the present invention, FIG. 2 is an electric circuit diagram showing an example of a specific circuit configuration thereof, and FIG.
The figure is a timing chart of the circuit shown in Figure 2, Figure 4 is a block diagram of a conventional example, Figure 5 is an electrical circuit diagram of an M-series code generator according to an improvement plan of the conventional example, and Figure 6 is a whisker-shaped pulse. It is a waveform explanatory diagram showing. 1... Code generation unit 2... Multi-stage shift register 3... Feedback logic circuit 5... Code extraction unit 8... Feedback value setting unit Patent applicant: Tateishi Electric Co., Ltd.-y+/ Figure 3

Claims (1)

[Claims] A code generating section configured by a combination of a multi-stage shift register and a feedback logic circuit, and a feedback value setting section for setting a feedback value to the multi-stage shift register are provided. An M-sequence code generator with an M-series code extraction section.