JPS60180146U - radio receiver - Google Patents
radio receiverInfo
- Publication number
- JPS60180146U JPS60180146U JP6850884U JP6850884U JPS60180146U JP S60180146 U JPS60180146 U JP S60180146U JP 6850884 U JP6850884 U JP 6850884U JP 6850884 U JP6850884 U JP 6850884U JP S60180146 U JPS60180146 U JP S60180146U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- tuner section
- local oscillator
- output signal
- tuner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Noise Elimination (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のＦＭラジオ受信機のブロック図、第２図
は相互変調妨害の発生条件を説明する周波数パターン図
、第３図は本考案に係るＦＭラジオ受信機のブロック図
、第４図は各局の周波数受信レベルを検出するためのタ
イムチャート、第 −５図は本考案にかするＡＧＣ制御
の処理の流れ図である。 −
１１・・・・・・チューナ部（第１のチューナ部）、１
１ｆ・・・・・−ＡＧＣ回路、１２−・・・・・中間周
波増幅回路、１３・・・・・−ＦＭ検波器、１５・・・
・−ＡＧＣ回路、−２１・−−−−４４２のチューナ部
、２３−・・・・・レベル検出回路、２５・・・・・・
−コントローラ、２６・・・・−ＰＬＬ回路、２７・・
・・・−ＡＧＣ切換回路、３１・・・・・・切換回路、
３２・・・・・・分周回路、３３・・・・・・ローパス
フィルタ、３ −４・・・・・・サンプリングホ
ールド回路、ＰＬＬＰ ｌ 。
ＰＬＩ、Ｐ ２−・間第１、第２のフェーズロックドル
ー プ。
１■ 第２図
１′１ ↑ ゛
ＩＴＩＬ＝Ｌ２Fig. 1 is a block diagram of a conventional FM radio receiver, Fig. 2 is a frequency pattern diagram explaining the conditions under which intermodulation interference occurs, Fig. 3 is a block diagram of an FM radio receiver according to the present invention, and Fig. 4. is a time chart for detecting the frequency reception level of each station, and FIG. 5 is a flowchart of the AGC control processing according to the present invention. - 11...Tuner section (first tuner section), 1
1f...-AGC circuit, 12-...Intermediate frequency amplification circuit, 13...-FM detector, 15...
・-AGC circuit, -21・----442 tuner section, 23-... Level detection circuit, 25...
-Controller, 26...-PLL circuit, 27...
...-AGC switching circuit, 31... switching circuit,
32... Frequency dividing circuit, 33... Low pass filter, 3 -4... Sampling hold circuit, PLLP l. PLI, P2--first and second phase-locked loops. 1■ Figure 2 1'1 ↑ ゛ITIL=L2
Claims (1)
制御するＡＧＣ回路と、１つのＰＬＬ回路を共用すると
共に各チューナ部に対応して形成された第１、第２の７
エーズロツクドループと、レベル検出回路と、各チュー
ナ部の局部発振器出力信号を切換えてＰＬＬ回路に入力
する切換回路と、第１のフェーズロックドループ内に配
設され乞と共にＰＬＬ回路出力電圧をサンプリングホー
ルドす、るサンプリングホールド回路と、サンプリング
ホールド指令によりサンプリングホールド回路をしてＰ
比回路出力電圧をサンプリングホールドさせ該ホールド
電圧を第１チューナ部の局部発振器へ−人力させ、且つ
切換回路をしそ第２チューナ部の局部発振器出力信号を
Ｐ比回路に入力させ、第２のチューナ部をして相互変調
妨害に関係する他局がらの信号を所定周期で受信させ、
該第２チューナ部から出力される希望局及び各他局から
の信号の受信レベルをレベル検出回路より得、該各局の
受信レベルに基づいて、前記自動利得制御回路を第１図 Ｔ １ １１１ＩａｒＪ−ＩＩｌ １ １ １ｆｂ”−’Ｉ １ 制御するコントローラを゛含むことを特徴とするラジオ
受信機。[Claims for Utility Model Registration] First and second tuner sections, an AGC circuit that controls the gain of the first tuner section, and a PLL circuit that share one PLL circuit and are formed corresponding to each tuner section. 1st, 2nd 7
A phase-locked loop, a level detection circuit, a switching circuit that switches the local oscillator output signal of each tuner section and inputs it to the PLL circuit, and a first phase-locked loop that samples and holds the PLL circuit output voltage. P
The output voltage of the ratio circuit is sampled and held, and the hold voltage is inputted manually to the local oscillator of the first tuner section, and the switching circuit is turned on.The output signal of the local oscillator of the second tuner section is inputted to the P ratio circuit, and the output signal of the second tuner section is input to the P ratio circuit. to receive signals from other stations related to intermodulation interference at a predetermined period,
The reception levels of the signals from the desired station and each other station outputted from the second tuner section are obtained from the level detection circuit, and the automatic gain control circuit is activated based on the reception level of each station. A radio receiver characterized in that it includes a controller for controlling I1111fb''-'I1.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6850884U JPS60180146U (en) | 1984-05-10 | 1984-05-10 | radio receiver |
| US06/733,593 US4654884A (en) | 1984-05-10 | 1985-05-10 | Radio receiver with switching circuit for elimination of intermodulation interference |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6850884U JPS60180146U (en) | 1984-05-10 | 1984-05-10 | radio receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60180146U true JPS60180146U (en) | 1985-11-29 |
| JPH026691Y2 JPH026691Y2 (en) | 1990-02-19 |
Family
ID=30603321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6850884U Granted JPS60180146U (en) | 1984-05-10 | 1984-05-10 | radio receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60180146U (en) |
-
1984
- 1984-05-10 JP JP6850884U patent/JPS60180146U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH026691Y2 (en) | 1990-02-19 |
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