JPS6017928A - Manufacture of complementary dielectric isolation substrate - Google Patents

Abstract

PURPOSE:To improve the dielectric strength and high frequency characteristic of a complementary dielectric isolation substrate by forming a high density buried layer having the same conductive type as that of an island formed of one conductive type in a single crystal near a dielectric film, thereby readily forming a complementary semiconductor element and preventing the influence of a polycrystalline substrate potential. CONSTITUTION:A p type conductive type single cystal island 20 which includes a p type high density buried layer removed by etching at the p type conductive type single crystal to the surface of an island to be electrically insulated by an insulating oxidized film 9, an island 21 having an n type conductive type single crystal including an n type high density buried layer in a p type conductive type single crystal including a p type high density buried layer, and an isolated substrate 23 having a plurality of islands 22 including only n type conductive type single crystal are provided. Thus, the influence of the polycrystalline substrate potential of a dielectric isolation substrate can be prevented by connecting the isolation substrate to the lowest potential of a circuit in case that an insulating oxidized film boundary is p<+> type and to the highest potential of the circuit in case that the insulating oxidized film boundary is n<+> type, thereby readily forming a vertical complementary semiconductor element to provide excellent electric characteristics and high dielecric strength.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a method for manufacturing a dielectric isolation substrate which is excellent in high voltage resistance and high frequency resistance and is necessary for constructing an integrated circuit using complementary semiconductor elements.

Monolithic integrated circuits typically include transistors, resistors,
It is necessary to electrically isolate a large number of components, such as capacitors, from each other. 'Currently, representative separation methods include the PN separation method and the dielectric separation method. Since the latter method usually uses an oxide film as an insulating material, it has features such as less parasitic capacitance than the PN isolation method, excellent high-frequency characteristics, and ease of increasing the breakdown voltage.

The most typical conventional method for manufacturing a dielectric isolation substrate is shown in FIGS. 1(a) to 1(d), and will be explained next.

First, as shown in FIG. 1(b), a separation groove 2 is formed on one side of a conductive single crystal silicon substrate 1 (not shown in FIG. 1(a)) by selective etching, and then the separation trench 2 is formed as shown in FIG. ''Secondly, an insulating oxide film 3 is deposited. Next, Figure 1 (C
), a polycrystalline silicon layer 4 is formed on the oxide film 3 by a gas phase reaction of silicon chloride, etc., this is used as a support layer 5, and by polishing at the positions indicated by broken lines,
As shown in FIG. 1(d), islands 6 of single-conductivity 114-crystalline silicon are isolated from each other by an oxide film 3 for insulation.
A dielectric isolation substrate 7 having the following properties is obtained. The biggest drawback of the conventional dielectric isolation substrate mentioned above is shown in Figure 1 (d).
) Since all the single-crystal silicon islands shown in ) are single-conducting WE, complementary semiconductor elements cannot be easily obtained, and the circuit must be constructed with two types of semiconductor elements: vertical type and lateral type. There is a particular thing.

Among these, the electrical characteristics of the lateral type are particularly poor, and the advantages of the dielectric isolation method, which is low parasitic capacitance and excellent high frequency characteristics, are completely lost, and the frequency characteristics of semiconductor integrated circuits are inferior to high frequency custom-made circuits. This is determined by the characteristics of the lateral type semiconductor element, and has the disadvantage that the element size becomes large in order to achieve a high breakdown voltage. Here, as a method for forming vertical complementary semiconductor elements on a dielectric isolation substrate of single conductivity, there is a method 1 in which wells of different conductivity are formed using a known technique such as thermal diffusion method. In order to achieve high breakdown voltage, it is necessary to increase the depth of the well in proportion to the device breakdown voltage, which requires a long time for diffusion and oxidation, and the accompanying lateral diffusion causes damage to the semiconductor device surface. This has disadvantages in that the surface concentration of is reduced, a surface inversion layer is formed, and the device breakdown voltage is reduced. Furthermore, under the influence of the polycrystalline substrate potential of the dielectric isolation substrate, the single crystal at the interface of the insulating oxide film becomes depleted or reversed, resulting in a reduction in device pressure.

The present invention replaces an island of monocrystalline silicon with single conductivity in a dielectric isolation substrate with an island of one type of conductivity, i ff
An island consisting of two types of conductivity with different types of conductivity including a high-concentration buried layer among the T-type conductivity, and 1
The single crystal near the dielectric film is made of a high-density island with the same conductivity as the island of one type of conductivity. The present invention provides a complementary dielectric isolation substrate that eliminates the above-mentioned drawbacks by forming a concentration buried layer, allows complementary semiconductor devices to be easily formed, and prevents the influence of the polycrystalline substrate potential.

That is, the present invention provides a dielectric isolation substrate having a plurality of single-crystal islands in which the polycrystal near the dielectric film is a highly concentrated buried layer with the same conductivity as the single crystal of the island. using 2
The polycrystalline in the region to be made into an island with a certain type of conductivity is removed by selective etching from the surface of the dielectric isolation substrate to a depth that satisfies the bulk breakdown voltage of the semiconductor element, and a transistor is formed in this etched island. On the island, a highly concentrated buried layer with conductivity different from that of the removed single crystal is formed on the remaining single crystal using thermal diffusion, ion implantation, etc., and then a highly concentrated buried layer is formed. After growing a single crystal on the single crystal and high concentration buried layer of the etched island, including the etched island, using an epitaxial growth device, etc., and incorporating impurities with conductivity different from that of the removed single crystal. , by removing by polishing or etching down to the surface of the first single conductive dielectric isolation substrate, it has a plurality of semiconductor single crystal islands insulated from each other by a dielectric film, and the conductivity of the single crystal of the island is removed. The shape is an island made of one type of conductivity, an island made of two types of conductivity with one type of conductivity, including a high concentration buried layer with a different type of conductivity, and an island made of one type of conductivity. There are islands of 29 types of conductivity that have different types of conductivity, and the single crystal near the dielectric film is a highly conductive island with the same conductivity as the island of one type of conductivity. This is a method of manufacturing a complementary dielectric partial f substrate characterized by obtaining a dielectric partial 11 substrate consisting of a concentration buried layer.

Next, embodiments of the present invention will be described with reference to the drawings.

2(a) to (e) are cross-sectional views showing a method of manufacturing a complementary dielectric isolation substrate according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view showing a method of manufacturing a complementary dielectric isolation substrate according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing an example of a semiconductor integrated circuit element manufactured by the semiconductor integrated circuit device.

First, in a polycrystalline silicon layer 8 manufactured by a known technique, as shown in FIG. A dielectric isolation substrate 12 is shown having islands 11 of single crystal silicon. However, the difference from the dielectric isolation substrate manufactured using the known technology shown in FIG. 1(d) is that in order to prevent the effect of the polycrystalline substrate potential on the dielectric isolation substrate, The method is to form a high-concentration buried layer using a thermal diffusion method, an ion implantation method, or the like before depositing an insulating oxide film.

To simplify the explanation, a case will be described in which a plurality of monocrystalline silicon islands 11 having a single conductivity have p-type groove conductivity, and different types of conductivity have n-type groove conductivity.

Next, as shown in FIG. 2(b), the islands of p-type groove conductivity which are required to have n-type groove conductivity are masked with an oxide film 13, and grooves 14 are formed by selective etching or the like. The depth of the trench 14 is determined by the depth and the specific resistance of the epitaxial growth layer that will be formed later.The bulk breakdown voltage is required for a semiconductor device manufactured by a known planar technique using a complementary dielectric isolation substrate 23, which will be described later. The depth shall be sufficient to satisfy the bulk pressure resistance.

Furthermore, among the etched islands, an oxide film 15 is formed on the island where the transistor is to be formed, as shown in FIG. 2(c).
A buried layer 16 with the highest n concentration is formed by thermal diffusion of P, As, Sb, etc., ion implantation, etc. using as a mask. Here, there is no problem even if all the p regions are replaced with the n highest concentration buried layer. Subsequently, as shown in FIG. 2(d), epitaxial growth is performed using the oxide film 17 as a mask, and an n-type groove conductive single crystal 18 is grown until the groove 14 is filled. At this time, a polycrystalline silicon layer 19 is simultaneously grown on the oxide film 17. Next, as shown in FIG. 2(e), the surface of the first p-type groove electrically conductive single crystal island 1.1 is removed by polishing, polishing, or etching, and electrically isolated from each other by the insulating oxide film 9. an island 20 of a p-type groove-conducting single crystal that is insulated from the top and including a p-maximum concentration buried layer; A complementary dielectric isolation substrate 23 having a plurality of islands 21 having an n-type groove conductive single crystal and a plurality of islands 22 having only an n-type groove conductive single crystal is obtained. According to the present invention, the influence of the polycrystalline substrate potential of the dielectric isolation substrate can be suppressed by connecting the dielectric isolation substrate to the lowest potential of the circuit when the insulating oxide film interface is p as described above, or as described below. As shown in the figure, the insulating oxide film interface is n
In the case of +, it can be prevented by connecting it to the highest potential of the circuit, making it easy to construct a vertical complementary type semiconductor element, with excellent electrical characteristics, stable characteristics even when aiming for high voltage resistance, and high voltage resistance. It is possible to construct an excellent integrated circuit device having features such as being smaller in size than a lateral type.

In the above embodiments, silicon is used as the single crystal substrate, p-type groove conductivity is used as the single-conductivity single crystal island, ■ groove structure is used as the selective etching method, oxide film is used as the isolation film and mask material, and n-type groove structure is used as the selective etching method. P+ as an impurity to make groove conductivity
Although AS+Sb was explained, Ge as a single crystal substrate
+ N-type trench conductivity as a single crystal island of single conductivity such as GaAs, U-groove structure as a selective etching method, nitride film as an insulating isolation film and mask material, and impurity to make p-type trench conductivity. Of course, a complementary dielectric isolation substrate using B, In, etc. may also be used.

Next, FIG. 3 shows a complementary vertical type PNP l- among semiconductor integrated circuit devices manufactured by known planar technology using the complementary dielectric isolation substrate 23 according to the present invention.
Ransistor 24 and vertical NPN) Ransistor 2
5 and vertical type PNE)N thyristor 26 are shown.

In the figure, 27 indicates a surface insulating film such as an oxide film, and 28 to 3
3 are the collector electrode, base electrode, emitter electrode, anode electrode, gate electrode, and base electrode of the semiconductor integrated circuit element, respectively.
The cathode electrode is shown. Note that the same elements as those in FIG. 2 are indicated by the same numbers and symbols. As is clear from the figure, by using the complementary dielectric isolation substrate according to the present invention, a vertical complementary semiconductor integrated circuit can be easily constructed.

As explained above, the complementary dielectric separation substrate according to the present invention has a single crystal island in a non-dielectric IC substrate, an island having one type of conductivity, and an island having a different type of conductivity within one type of conductivity. An island consisting of two types of conductivity having different types of conductivity including a highly concentrated buried layer, and an island consisting of two types of conductivity having different types of conductivity within one type of conductivity, and a dielectric By making the single crystal near the membrane a highly concentrated buried layer with the same conductivity as the island, which is made of one type of conductivity, the influence of the polycrystalline substrate potential can be prevented, and a complementary type can be formed in the vertical type. This has the effect that a semiconductor element can be easily formed, has excellent electrical characteristics, has a small element size even in the case of high surface area and one pressure, and can constitute a semiconductor integrated circuit with excellent reliability.

[Brief explanation of drawings]

Figures 1 (a) to (d) are cross-sectional views showing a conventional method for manufacturing a dielectric isolation substrate having single conductive single crystal islands, and Figure 2 (
a) to (e) are cross-sectional views showing a method for manufacturing a complementary T dielectric isolation substrate having complementary conductive single crystal islands according to the present invention;
The figure is a cross-sectional view of a semiconductor integrated circuit device manufactured using a complementary dielectric isolation substrate according to the present invention. ■...Single crystal silicon, 2...Isolation groove, 3,9.2
7... Oxide film for insulation, 4. ．． 8.19... Polycrystalline silicon layer, 5... Support layer, 6, 11... Single conductive single crystal island, 7, 12... Dielectric separation substrate, 10
... Single conductive high concentration buried layer, 13゜15, 17.
...Mask oxide film, 14°/° groove, 16-n highest tension buried layer, 18...n-type conductive single crystal, 20...p
Island of p-type conductive single crystal containing highest concentration buried layer, 21...
・In the p-type conductive single crystal including the buried layer with the highest concentration of p,
Island with n-type conductive single crystal containing highest concentration buried layer, 22
...An island having only an n-type conductive single crystal in a p-type conductive single crystal including a buried layer with the highest p concentration, 23...Complementary dielectric isolation substrate, 24...Vertical type PNP l - Ransistor, 25...Vertical type NPN) Ransistor, 26... Vertical type PNPN thyristor, 28
...Collector electrode, 29...Base electrode, 30...
・Emitter electrode, 31... Anode electrode, 32...
Gate electrode, 33...Cathode electrode Patent applicant NEC Corporation゛・-Fnor゛: (Q) (b) (C) Fig. 2 (d,) (e)

Claims (1)

[Claims] (1) A common semiconductor substrate, which has several islands of semiconductor Qi crystals insulated from each other by dielectric films, and the conductivity type of the single crystal of the island is one type; If
There are islands of two types of conductivity that have different types of conductivity, including a high-concentration indented layer, and two islands that have different types of conductivity within one type of conductivity. Complementary dielectric separation in which there are islands with different types of conductivity, and the single crystal near the dielectric film is a highly concentrated buried layer with the same conductivity as the island with one type of conductivity. In the method of forming the substrate, a dielectric isolation substrate is used in which islands of single conductivity are formed as a highly concentrated buried layer of single crystal near the dielectric film, and a single conductive island is formed in a region that is to be an island with two types of conductivity. The crystal is removed from the surface of the dielectric isolation substrate by selective etching at a depth that satisfies the bulk pressure distribution of the semiconductor element, and among the etched islands, the islands where transistors will be formed are etched on top of the remaining single crystal. Next, a highly concentrated indented layer with a conductivity different from that of the removed single crystal is formed by thermal diffusion, ion implantation, etc., and the etched islands, including the islands on which the highly concentrated buried layer is formed, are then etched. After growing a single crystal using an epitaxial growth device or the like on the crystal and high-concentration buried layer while adding impurities with conductivity different from the removed single crystal, the first single-conductivity dielectric separation is performed. It has several semiconductor single crystal islands that are insulated from each other by a dielectric film by polishing or etching to the surface of the substrate, and the conductivity type of the single crystal of the island is an island that has one type of conductivity. , an island consisting of two types of conductivity with different types of conductivity including a high-concentration buried layer with different types of conductivity within one type of conductivity, and an island with different types of conductivity within one type of conductivity. Dielectric separation in which there are islands with two types of conductivity, and the single crystal near the dielectric film is a highly concentrated buried layer with the same conductivity as the island with one type of conductivity. 1. A method of manufacturing a complementary dielectric isolation substrate, comprising: obtaining a substrate.