JPS60177786A - Video signal processing device - Google Patents

Abstract

PURPOSE:To make reduction of noise and Y, C separation simultaneously without deteriorating degree of resolution by performing cyclic addition of NTSC signals on the one hand, and making code inversion cyclic addition (cyclic addition) on the other hand at every frame period using two frame delay circuits. CONSTITUTION:After multiplying an input signal by (1-K) by a gain converter 20, divided into two, and one is added to an adder 21. After delaying the output 22 by one frame by a delay circuit 23, multiplied by K by a gain converter 24 and added to the adder 21 to constitute a recurrent type filter. By this way, C signal having negative frame interrelation and noise that has no interrelation are removed from the output 22 and remaining Y signal component is outputted. On the other hand, output 29 of an adder 25 is delayed by one frame by a frame delay circuit 26. Then code is inverted, and multiplied by K by a gain converter 28, and added again to the adder 25. Then, Y signal having positive interrelation between frames and noise having no interrelation are removed from output of the adder 25, and G signal 29 is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an NTSC video signal processing device.

(Prior art and its problems) In the NTSC standard system, the luminance signal (hereinafter referred to as Y signal)
A color signal (hereinafter referred to as C signal) amplitude-modulated with a subcarrier having a frequency 455 x 525 /2 times the frame frequency is superimposed on the frame frequency and transmitted. Therefore, for still images, the Y signal has a positive correlation of 100 degrees between frames, and the C signal has a negative correlation.

Therefore, as shown in FIG. 1, if the two human input signals are delayed by one frame in the frame delay circuit 1 and then added to the human input signal in the addition circuit 2, a Y signal 3 is obtained, and the sign is inverted in the inverter circuit 4. Then, by adding them in an adder circuit 5, the C signals 6 can be separated.

By the way, when the above-described YC separation method is used in combination with a general noise reducer, the following secondary problem occurs. Figure 2 is a block diagram of a general noise reducer, and its operating principle is to convert 9 human input signals into a gain converter 10 (1
-1<) (K: constant...0<K<1) After multiplying, the frame delay circuit 12 delays one frame, and the gain converter 14 multiplies the signal 15 and the adder 11 performs cyclic addition. do.

In this way, signal components that have correlation between frames are added in amplitude, and uncorrelated noise is added in power, so S
/N is improved by a factor of 1. ,. As mentioned above in 1-2, since the C component has a negative correlation between frames, it cannot be added as is.

For this reason, the 9 normal C components are separated using a bandpass filter,
A chroma inverter circuit 13 that inverts the sign of this component every frame is inserted in the recursion loop. However, in this chroma inverter circuit 13, the Y component included in the C signal band is also regarded as a C signal, and its sign is inverted.

This component is removed at output 16. When performing YC separation using a normal bandpass filter, etc.

Originally, the Y component included in the C signal band is unnecessary and therefore does not pose a problem, but when using the YC separation method using the frame correlation described above, the resolution deteriorates and becomes a big problem.

(Objective) The present invention provides a video signal processing circuit that simultaneously performs noise reduction and YC separation without deteriorating resolution.

The feature of the present invention is that by using two frame delay circuits, N
The purpose of this method is to simultaneously perform noise reduction and Y and C separation by performing cyclic addition on the one hand and sign-inverted cyclic addition (cyclic subtraction) on the other hand for each frame period of the TSC signal.

(Example) The present invention will be described in detail below using Examples.

FIG. 3 shows a block diagram of the first embodiment of the present invention.

After multiplying the human signal by (1-K) using the gain converter 20,
Divide it into two parts and add one to the adder 21. This adder 2
After the output 22 of 1 is delayed by one frame in the frame delay circuit 23, the gain converter 24 generates a KIl sound.

In addition to the adder 21, a recursive fill is configured. In this way, the output 22 of the adder 2 is the C signal having a negative frame period relationship and the Y signal component with the correlation noise removed and the Y signal component remaining λ.

On the other hand, the other output of the gain converter 20 is
Add to 5. After this output is delayed by one frame in a frame delay circuit 26, its sign is inverted in an instant 27, further multiplied by a gain converter 28, and then applied to a power calculator 25 again. In this way, the output power of the adder 25 is removed. This time, the Y signal having a positive correlation between frames and the uncorrelated noise are removed, and a C signal 29 is obtained.

By the way, when the image is still, the NTSC signal of the nth frame is Xn, the Y signal is Yn, and the C signal is Cn.
Then, the quadratic relationship holds, Xn=Yn+C, --
---(1) Yn=Yn, ---・-(2) Cn=-Cn-1... (3) If the output of the 11th frame is 22 and Z22n Z 22 n2Σ(i-K)K-Xn+□ ・・・・・・
・・・・・・・・・・・・(4) m=0 and again.

Yn-Yn-1-Yn-2......-Y...
・・・・・・・・・(5)Cn”=Cn+2
−Cn + 4・・・・・・・・・−C・・・・・・・・・
...(G)CTl+1""CTl+3=CTl+5
・・・・・・－−C・・・・・・・・・・・・If it is (7), then equation (5) is.

・・・・・・・・・・・・(8) 2CY-K" Y)+ to 2CQ- to -1- to 2- to 3+
・・・・・・・・・+(-1)"K""-1)] -[Y-K Y)+[2C(---))1+K2-Y+C2C(〒1-7)': ] (However, O<K<
1)=Y + (2C(-)) 2 (1[) -Y+-C・・・・・・・・・・・・・・・・・・ +9
)1[, and in addition to the Y signal from which the noise component has been removed, some C signal components remain at the output 22. Similarly, if the output 29 is Z29n, this is calculated in the same way.

Z29+1=C+ShiY・・・・・・・・・・・・・・・
. . , negative 0), and some Y signal components remain in the output 29 in addition to the C signal from which the noise components have been removed.

FIG. 4 is a block diagram of a second embodiment of the invention which eliminates the above drawbacks. Let me explain this behavior.

After the output 22 is delayed by the frame delay circuit 23, the human input signal 3 is multiplied by 77 by the adder 31 and the gain converter 30.
Add 3. In this case, as the output 22 in FIG. 3, Z22n determined by the above formula 00) will be added with ¥.Xn+1, so this output Z34n will be.

Z34n=(Y+”-C)+[(-→(Yn+t+Cn
+z)] 1 +K 1 +K ・・・・・・・・・・・・・・・・・・(Ll)Cn+]
= C, Yn-1-]-Y, so the αυ formula is.

Z34n= (1+)Y...Song...It becomes uz1+, and the C signal is completely removed from the output 34.

A Y signal with reduced noise components can be obtained.

Similarly, after inverting the sign of the human input signal 33 with an inverter 36, an adder 38 outputs the output 3 of the frame delay circuit 26.
5 and this output Z 39 n is calculated in the same way.

Z: +9n= (1+) C-・----Q311
10, the Y signal component is completely removed from the output 39,
A C signal with reduced noise components can be obtained.

(Effects) As described above, according to the present invention, a video signal processing circuit that simultaneously performs noise reduction and YC separation without deterioration of resolution can be realized with a simple circuit configuration, and a video signal processing circuit that handles still images can be realized. It is highly effective when applied to processing equipment.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a YC separation circuit using frame correlation.
FIG. 2 is a block diagram of a general noise reducer, FIG. 3 is a block diagram of a first embodiment of the present invention, and FIG. 4 is a block diagram of a second embodiment of the present invention. 1, 12.23.26: Frame delay circuit, 10.
14.20.24.28°30 gain converter, 2.5
．． IL 2L 25.31.38: Adder. 4.27.36: Inverter. Agent Patent Attorney Akio Takahashi Figure 1 Figure 2

Claims (1)

[Claims] 1) a first recursive filter means for extracting a luminance signal component by cyclically adding the gain-converted human video signal for each frame period via a first frame delay means; The second recursive filter means extracts the color signal component by reversing the sign of the human video signal every frame period through the second frame delay means and cyclically adding it.
C standard television signal brightness. A video signal processing device characterized by performing color signal separation. 2) a first recursive filter means for extracting a luminance signal component by cyclically adding the gain-converted human video signal for each frame period via a first frame delay means; a second recursive filter means for extracting a color signal component by inverting the sign every frame period through the frame delay means and performing cyclic addition; a first adding means for adding a human video signal whose gain has been converted by the same amount as the gain conversion amount by the second recursive filter means with the output of the first recursive filter means; The second adding means adds the human video signal whose gain has been converted by the same amount as the gain conversion amount by the second recursive filter means with the output of the second recursive filter means after the title is returned, to reduce random noise. NTS while planning
C standard television signal brightness. A video signal processing device characterized by performing color signal separation.