JPS60177710A - High frequency amplifier - Google Patents

High frequency amplifier

Info

Publication number
JPS60177710A
JPS60177710A JP3341784A JP3341784A JPS60177710A JP S60177710 A JPS60177710 A JP S60177710A JP 3341784 A JP3341784 A JP 3341784A JP 3341784 A JP3341784 A JP 3341784A JP S60177710 A JPS60177710 A JP S60177710A
Authority
JP
Japan
Prior art keywords
emitter
circuit
resistor
terminal
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3341784A
Other languages
Japanese (ja)
Other versions
JPH0544841B2 (en
Inventor
Akira Usui
晶 臼井
Kazuhiko Kubo
一彦 久保
Tadashi Yamada
忠 山田
Hiroyuki Nagai
裕之 永井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3341784A priority Critical patent/JPS60177710A/en
Publication of JPS60177710A publication Critical patent/JPS60177710A/en
Publication of JPH0544841B2 publication Critical patent/JPH0544841B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)

Abstract

PURPOSE:To ensure the stable working of a circuit which is obtained through integration of the high frequency DC connected multi-stage coupling, by leading a terminal outside an IC through a bonding wire of said IC and forming a filter circuit containing the inductance of the bonding wire from said terminal between the counter earths. CONSTITUTION:A sum current of the base current of a transistor (TR) Q2 and the current flowing through a resistance R12 is supplied to the emitter of the TRQ2. This sum current is also supplied to an earth (GND) through a resistance R13. Thus a potential decided by the product of the emitter current of the TRQ2 and the value of a resistance R13 is produced at the R13. This potential is fed back to the base of a TRQ1 through a resistance R14 and therefore the base potential of the TRQ1 is stabilized at a certain fixed point. Under such conditions, the input signals are amplified by both TRQ1 and Q2. However it is impossible to increase the gain by the emitter resistance R13 of the TRQ2 in terms of a high frquency. In this respect, a filter circuit 11 is inserted between earths from the emitter of the TRQ2. This reduces the feedback amount of a specific frequency and then stabilizes the circuit working.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、集積回路化された高周波増幅装置に関するも
のであシ、テレビジョンチューナー回路、衛星放送用受
信機等の高周波信号増幅用として用いられるものである
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an integrated circuit high frequency amplification device, which is used for high frequency signal amplification in television tuner circuits, satellite broadcasting receivers, etc. It is.

従来例の構成とその問題点 従来、100MH2帯以上の高周波信号を処理する高周
波増幅回路において、高利得を得るためには、第1図人
に示すような多段接続回路がよく用いられる。第1図人
の回路を集積化するには、同図Bに示すようなICパッ
ケージ1に封入する必要があるが、ICパッケージ1の
各々の端子1a。
Conventional Structure and Problems Conventionally, in a high frequency amplifier circuit that processes high frequency signals of 100 MH2 band or higher, a multistage connection circuit as shown in FIG. 1 is often used to obtain high gain. In order to integrate a circuit in FIG. 1, it is necessary to encapsulate it in an IC package 1 as shown in FIG.

1b、10,1dとICチップ間はボンディングワイヤ
ーで接続されるために、同図Bに示ずL1n+LG 、
 Lout 、 t、Bのようなワイヤーインダイタン
スを持ってし1つ。このワイヤーインダクタンスは、通
常2.6 mH〜6 mHの値となり、低い周波数では
無視できる値であるが、800 MHz以上の高周波信
号になると、無視できないものとなる。第1図の回路に
おいては、LIN 、 LB 、 Loutは外部回路
あるいは、IC内部の抵抗R1! R31”4により、
その影響を除去できるが、対アース(GND)間に挿入
されるインダクタンスLGだけは除去できない。
1b, 10, 1d and the IC chip are connected by bonding wires, so they are not shown in Figure B, but L1n+LG,
One with wire inductance like Lout, t, B. This wire inductance usually has a value of 2.6 mH to 6 mH, and is a value that can be ignored at low frequencies, but becomes a value that cannot be ignored when it comes to high frequency signals of 800 MHz or more. In the circuit of FIG. 1, LIN, LB, and Lout are external circuits or resistors R1! inside the IC. By R31”4,
Although that influence can be removed, only the inductance LG inserted between the ground and ground (GND) cannot be removed.

図の例ではトランジスタQ+ 、 Q2 のエミッタに
共通のインタフタンス成分りが挿入されてしまうのが特
に問題で、このために帰還ループが構成されて回路の発
振を招くという重大な欠点があった。
In the example shown in the figure, a particular problem is that a common interface component is inserted into the emitters of transistors Q+ and Q2, which creates a feedback loop and causes oscillation in the circuit, which is a serious drawback.

第1図Cは同図BのトランジスタQ2のエミッタに抵抗
R5を挿入し、かつボンディングワイヤーインダクタン
スLG2をICの外部に接続されるバイパス容量Cを通
して接地し、上記発振現象を改善しようとするものであ
るがトランジスタQ、1石だけなら問題はなくても、ト
ランジスタQ1と92を多段接続することで、ワイヤー
インダクタンスLG2(!:ともに、トランジスタQ1
のエミッタをIC内のアースに接地することによるワイ
ヤーインダクタンスLG、が存在するために、回路のア
ース電位が不安定となり、k+、1つならば問題はなく
ても多段接続においては、発振状態を除去できないとい
う欠点を持っていた。
In Figure 1C, a resistor R5 is inserted into the emitter of the transistor Q2 in Figure 1B, and the bonding wire inductance LG2 is grounded through a bypass capacitor C connected to the outside of the IC in order to improve the above oscillation phenomenon. However, if there is only one transistor Q, there is no problem, but by connecting transistors Q1 and 92 in multiple stages, the wire inductance LG2 (!: both transistor Q1
Due to the presence of wire inductance LG, which is caused by grounding the emitter of k+ to the ground inside the IC, the ground potential of the circuit becomes unstable, and even if there is only one k+, there is no problem, but when connected in multiple stages, an oscillation state may occur. It had the disadvantage that it could not be removed.

発明の目的 本発明はこのような多段接続の高周波集積回路において
、発振現象の生じ々い安定した動作を得るための手段を
提供することを目的とする。
OBJECTS OF THE INVENTION It is an object of the present invention to provide a means for obtaining stable operation without the occurrence of oscillation phenomena in such multi-stage connected high frequency integrated circuits.

発明の構成 本発明による高周波増幅装置は、エミッタ接地型増幅器
を直流結合して多段接続した回路を集積回路にて構成し
、2段目以後の増幅回路のエミッタには、エミッタ抵抗
を対アース間に接続し、かつそれらのトランジスタの少
なくとも1つのエミッタから、集積回路のボンディング
ワイヤを通して、集積回路の外に端子を出し、この端子
からボンティングワイヤーのインダクタンスを含んだフ
ィルター回路を対アース間に構成し、フィルター回路に
より特定の周波数を集積回路外に接地して、上記エミッ
タ抵抗による帰還を防ぎ利得をかせぐようにしたもので
ある。
Composition of the Invention The high-frequency amplification device according to the present invention is constituted by an integrated circuit of a circuit in which emitter-grounded amplifiers are DC-coupled and connected in multiple stages. and from the emitter of at least one of those transistors, a terminal is brought out of the integrated circuit through a bonding wire of the integrated circuit, and from this terminal a filter circuit including the inductance of the bonding wire is constructed between the terminal and ground. However, a specific frequency is grounded outside the integrated circuit using a filter circuit, thereby preventing feedback due to the emitter resistance and increasing gain.

実施例の説明 本発明の一構成例を第2図に示す。図示する例は、トラ
ン7スタQ+ 、 Q2 のエミッタ接地トラン7スタ
を用いた2段増幅回路である。商周波入力信刊は、入力
端仔INより供給され、出力端子0LITより出力きれ
る。ここでトランジスタQ、のコレクタには、電源子B
よシ抵抗R1+ を通して電流が流れ、その電流は、ト
ランジスタQ2のベースに分流されて、トラン7スタQ
2のコレクタには、箪1Jrr 十Bより抵抗R+2を
通して電流が供給される。
DESCRIPTION OF THE EMBODIMENTS An example of the structure of the present invention is shown in FIG. The illustrated example is a two-stage amplifier circuit using seven transistors with common emitters, Q+ and Q2. The commercial frequency input signal is supplied from the input terminal IN and output from the output terminal 0LIT. Here, the collector of the transistor Q is connected to the power supply terminal B.
A current flows through the resistor R1+, and the current is shunted to the base of the transistor Q2, and the current flows through the transistor Q2.
A current is supplied to the collector of No. 2 from 1JRR 1B through resistor R+2.

トランジスタQ2のエミッタには、トランジスタQ2の
ベース電流と抵抗R12を通して流れる電流の和電流が
流れ、抵抗R13を通して、アース(GND)に流わる
ため、抵抗R13にはトランジスタQ2のエミッタ電流
と抵抗R13の値との積で決する電位が発生し、これを
抵抗R14を通してトランジスタQ1のベースに帰還す
れば、トランジスタQ+(7)ベース電位が上昇し、ト
ランジスタQ、のコレクタ電位が下カシ、トランジスタ
Q2のエミッタ電位が下がり、トランジスタQ1のベー
ス電位はある一定点で安定し、抵抗RIT + R13
+ ”+4 + R16の値を選ぶことによりトランジ
スタQ+ 、 、Qzにはそわ、ぞれ所望の電流を流す
ことができる。このような状態では、入力信 −号はト
ランジスタQ+ 、 Q2で増幅されるが、トランジス
タQ2のエミッタ抵抗R13により高周波的には利得を
かせぐことができないため、トランジスタQ2のエミッ
タよシ接地間にフィルター回路11を挿入し、特定の周
波数の帰還量を減少させ、回路動作を安定させるもので
ある。なお、図における咄Rssは、抵抗R14で帰還
させる直流量を調整するだめに挿入されるものである。
The sum of the base current of the transistor Q2 and the current flowing through the resistor R12 flows through the emitter of the transistor Q2, and flows through the resistor R13 to the ground (GND). When a potential determined by the product of the value is generated and is fed back to the base of the transistor Q1 through the resistor R14, the base potential of the transistor Q+(7) rises, the collector potential of the transistor Q falls, and the emitter of the transistor Q2 The potential decreases, the base potential of transistor Q1 becomes stable at a certain point, and resistor RIT + R13
+ "+4 + By selecting the value of R16, desired currents can be made to flow through transistors Q+, Qz, and Qz. In such a state, the input signal - is amplified by transistors Q+ and Q2. However, since it is not possible to obtain gain at high frequencies due to the emitter resistor R13 of the transistor Q2, a filter circuit 11 is inserted between the emitter of the transistor Q2 and the ground to reduce the amount of feedback at a specific frequency and improve the circuit operation. Note that the resistor Rss in the figure is inserted to adjust the amount of DC to be fed back using the resistor R14.

ところで第2図の回路を集積化し、ICパッケージに収
めた場合には、第3図のような構成になり、集積回路チ
ップとバ、ケーゾ間はボンディングワイヤーで接続ざノ
′するために図に示すLrN、 Lout、LB、LC
,I、LC2のワイヤーインダクタンスを有してし甘う
。この値は、Mi+述のように、2.5〜5mHの値に
なり、Lout、 LB、 Lrnについては影響を除
去できることは前述のとおりであるが、LGI 、 L
C2の2つについては交流的には影響が大きく、相互に
影響して動作不安定状態となり発振状態になるためボン
ディングインダクタンスは少なくとも一方しか許され−
ないことになる。このため、本発明の第3図の例では、
一方のインダクタンスLG2を除去する手段をとること
によシ回路の安定性を確保しようとするもので、すなわ
ち、ICパソケ−7外にフィルター回路11を設置し、
LC2のインターフタンスと共振尽せ、これを吸収する
機能を持たせている。フィルター回路11としては第6
図A、B。
By the way, if the circuit shown in Figure 2 is integrated and housed in an IC package, the configuration will be as shown in Figure 3. Indicates LrN, Lout, LB, LC
, I, LC2. As mentioned above, this value is 2.5 to 5 mH, and as mentioned above, the influence can be removed for Lout, LB, and Lrn, but for LGI, L
The two C2 have a large influence in terms of alternating current, and because they influence each other, the operation becomes unstable and oscillates, so at least one bonding inductance is allowed.
There will be no. Therefore, in the example of FIG. 3 of the present invention,
The purpose is to ensure the stability of the circuit by removing one inductance LG2, that is, by installing a filter circuit 11 outside the IC path socket 7,
It has a function to absorb the interftance and resonance of LC2. As the filter circuit 11, the sixth
Figures A and B.

Cに示すような形が考えられる。第5図Aの例ではボン
ディングインダクタンスLG2とコンデンサC,とて直
列共振回路を構成し、LC2の影響を除去するとともに
所望周波数の近辺においてトランジスタQ2のエミッタ
抵抗R13の影響を排し、第4図の破線Bのような特性
を得て低い周波数帯の利得を抑えることができるもので
ある。800 MHz〜1GHz帯においてはコンデン
サC7の値として、15pF以下が適値となる。ここで
、コンデンサC,として1000pFのものを用いれば
、第4図の実線Aのような特性になり、低い周波数の利
得が大きくなりすぎるのと、インダクタンスI、G2の
影響により、第3図の回路は極めて発振しやすい状態に
なってしまう。このようなことから、直流結合の多段増
幅回路においては、上記の対応が不町決になる。なお、
第6図AにおいてコンデンサC1にダンピング抵抗を挿
入すれば広帯域が確保できて所望の効果を得ることがで
きる。
A shape as shown in C is possible. In the example shown in FIG. 5A, the bonding inductance LG2 and the capacitor C constitute a series resonant circuit to eliminate the influence of LC2 and the influence of the emitter resistor R13 of the transistor Q2 in the vicinity of the desired frequency. It is possible to obtain the characteristics shown by the broken line B and suppress the gain in the low frequency band. In the 800 MHz to 1 GHz band, a suitable value for the capacitor C7 is 15 pF or less. Here, if a capacitor C of 1000 pF is used, the characteristics will be as shown by the solid line A in Figure 4, and the gain at low frequencies will become too large, and due to the influence of the inductances I and G2, the characteristics will be as shown in Figure 3. The circuit becomes extremely susceptible to oscillation. For this reason, the above-mentioned solution is not acceptable in a DC-coupled multi-stage amplifier circuit. In addition,
In FIG. 6A, if a damping resistor is inserted into the capacitor C1, a wide band can be secured and the desired effect can be obtained.

第6図B、Cはフィルタ回路11の他の構成例を示すも
ので、第5図BはLC2,LXとCI+02により共振
回路を、第6図CはLC2,RXIとCI + C2に
よシ共振回路を構成するもので、このようにフィルター
回路に種々の展開を図ることにより第4図の特性Bに変
化を持たせることができるものである。
6B and 6C show other configuration examples of the filter circuit 11. FIG. 5B shows a resonance circuit using LC2, LX and CI+02, and FIG. 6C shows a resonance circuit using LC2, RXI and CI+C2. It constitutes a resonant circuit, and by developing the filter circuit in various ways as described above, the characteristic B in FIG. 4 can be varied.

本発明の第2の実施例を第6図に示す。第6図の例は第
3図のトランジスタQ1よりなる増rl+器とトランジ
スタQ2よりなる増中器の間にトランジスタQ3と抵抗
Ft+6からなるエミッタホロア回路を挿入したもので
あり、Qlの増幅器とQ2の増幅器の間の逆方向伝達関
係を向上させているもので、回路の安定性をより向上さ
せることができるものである。
A second embodiment of the invention is shown in FIG. In the example of FIG. 6, an emitter follower circuit consisting of a transistor Q3 and a resistor Ft+6 is inserted between the amplifier rl+ consisting of the transistor Q1 and the amplifier consisting of the transistor Q2 in FIG. This improves the reverse transfer relationship between the amplifiers, which can further improve the stability of the circuit.

本発明の第3の実施例を第7図に示す。この例は、第3
図の例のトランジスタQ1のエミッタとIC内アース間
に抵抗R16を挿入し、トラジスタQ1のエミッタから
ボンティングワイヤーLG3を通してIC外に端子を出
し、その端子にも第6図に示す構成のフィルター回路1
1′を挿入するもので、フィルター回路11.11’を
トランジスタQl、Q2の各々のエミッタに2段接続す
ることによシ第4図Bの特性を急峻にするものである。
A third embodiment of the invention is shown in FIG. In this example, the third
A resistor R16 is inserted between the emitter of the transistor Q1 in the example in the figure and the ground inside the IC, and a terminal is brought out from the emitter of the transistor Q1 to the outside of the IC through the bonding wire LG3, and the filter circuit with the configuration shown in Figure 6 is also connected to that terminal. 1
1' is inserted, and the characteristic shown in FIG. 4B is made steeper by connecting filter circuits 11 and 11' in two stages to the emitters of each of transistors Ql and Q2.

本発明の第4の実施例を第8図に示す。この装置は第6
図のエミッタホロワ回路を挿入する例において、トラン
ジスタQ1のベースへの直流帰還をエミッタホロアトラ
ンジスタQ3のエミッタより抵抗R14r ” +5 
による構成にてかけたものであり、第6図の構成と同様
の効果を得ることができる。
A fourth embodiment of the invention is shown in FIG. This device is the 6th
In the example of inserting the emitter follower circuit shown in the figure, the DC feedback to the base of the transistor Q1 is connected from the emitter of the emitter follower transistor Q3 to the resistor R14r'' +5.
It is possible to obtain the same effect as the structure shown in FIG. 6.

本発明の第5の実施例を第9図に示す。この図の例では
直流結合の多段接続増幅器を構成し、2段目以後の増幅
器の少なくとも1つのエミッタにはIC内アース間に抵
抗を挿入し、各々のエミッタよりボンティングワイヤー
LGNを通してICIIJに端子を出し、この端子とア
ース間に前記第5図のフィルター回路11Nを伺加する
ことにより、回路の動作安定化を図るものである。図に
おいて13にて示すエミッタホロア回路は挿入してもし
なくともよい。
A fifth embodiment of the invention is shown in FIG. In the example shown in this figure, a DC-coupled multi-stage connected amplifier is configured, and a resistor is inserted between the ground in the IC in at least one emitter of the second and subsequent amplifiers, and a terminal is connected from each emitter to ICIIJ through the bonding wire LGN. By connecting the filter circuit 11N shown in FIG. 5 between this terminal and the ground, the operation of the circuit is stabilized. The emitter follower circuit indicated by 13 in the figure may or may not be inserted.

但し、トランジスタQ1のベースへの直流帰還は2段目
以後の増幅器の偶数番目のエミッタから抵抗E(yBを
通して抵抗RNGとの分割電位を負帰還するものである
However, the direct current feedback to the base of the transistor Q1 is to negatively feed back the divided potential with the resistor RNG from the even-numbered emitters of the second and subsequent stage amplifiers through the resistor E (yB).

以上第1から第5の実施例について述べたが、直流帰還
抵抗R+< 、RNBはICの外で構成してもよく、ま
た直流帰還抵抗の電位の分割は必らずしもしなくともよ
い。
Although the first to fifth embodiments have been described above, the DC feedback resistor R+<, RNB may be configured outside the IC, and the potential of the DC feedback resistor does not necessarily need to be divided.

また、各実施例における出力信号はエミッタ接地トラン
ジスタのコレクタから直接取りだしているが、その出力
にエミッタホロア回路を挿入してエミッタホロア回路よ
り出力を得るようにしでもよい。
Furthermore, although the output signal in each embodiment is taken out directly from the collector of the common emitter transistor, an emitter follower circuit may be inserted into the output of the emitter follower circuit to obtain the output from the emitter follower circuit.

発明の効果 本発明を用いることにより、高周波直流接続多段結合の
集積化における回路の動作安定化を図ることができる。
Effects of the Invention By using the present invention, it is possible to stabilize the operation of a circuit in the integration of high-frequency DC connection multi-stage coupling.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A、B、Cは従来例における高周波増幅装置の回
路図、第2図は本発明の〜実施例における高周波増幅装
置の回路図、第3図は本発明の装置をICパッケージに
封入したときの等価回路図、券4図は多段増幅器の周波
数−振幅特性図、第6図A、B、Cは本発明で用いるフ
ィルター回路の各禅具体例を示す回路図、第6図は本発
明の第2の実施例を示す回路図、第7図は本発明の第3
の実施例を示す回路図、第8図は本発明の第4の実施例
を示す回路図、第9図は本発明の第5の実施例を示す回
路図である。 Ql、Q2 ・増幅トランジスタ、”+3 + ”+4
・ 抵抗、11・−フィルター回路。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第2
図 第3図 化4図 第5図
Figures 1A, B, and C are circuit diagrams of a high-frequency amplification device in a conventional example, Figure 2 is a circuit diagram of a high-frequency amplification device in embodiments of the present invention, and Figure 3 is a circuit diagram of a high-frequency amplification device according to embodiments of the present invention, and Figure 3 shows a device of the present invention enclosed in an IC package. Figure 4 is a frequency-amplitude characteristic diagram of a multistage amplifier. Figures 6A, B, and C are circuit diagrams showing specific examples of filter circuits used in the present invention. Figure 6 is a diagram of the present invention. A circuit diagram showing the second embodiment of the invention, FIG. 7 is a circuit diagram showing the third embodiment of the invention.
FIG. 8 is a circuit diagram showing a fourth embodiment of the present invention, and FIG. 9 is a circuit diagram showing a fifth embodiment of the present invention. Ql, Q2 ・Amplification transistor, "+3 + "+4
・Resistor, 11・-filter circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 Figure 4 Figure 5

Claims (4)

【特許請求の範囲】[Claims] (1) エミッタ接地型増幅器を直流結合にて多段接続
して集積回路を構成し、2段目以後のトランジスタの各
エミッタには集積回路内のアース間に抵抗を接続し、そ
れらのトランジスタの少なくとも1つのエミッタ端子か
らボンディングワイヤーを通して集積回路の外部に端子
を設け、その端子から外部アース間に、特定の周波数の
近辺に対して低インピーダンスになるようなフィルター
回路を設けるこ占を特徴とする高周波増幅装置。
(1) An integrated circuit is constructed by connecting emitter-grounded amplifiers in multiple stages using DC coupling, and a resistor is connected between the emitters of the transistors in the second and subsequent stages to the ground in the integrated circuit. A high frequency device that is characterized by providing a terminal outside the integrated circuit through a bonding wire from one emitter terminal, and installing a filter circuit between that terminal and external ground to provide low impedance in the vicinity of a specific frequency. Amplifier.
(2)2段目以後のトランジスタのエミッタ電位を抵抗
を通して入力段トランジスタのベースKW流負帰還をか
けることを特徴とする特許請求の範囲第1項記載の高周
波増幅装置。
(2) The high frequency amplification device according to claim 1, wherein the emitter potential of the transistors in the second and subsequent stages is subjected to negative feedback through the base KW flow of the input stage transistor through a resistor.
(3)各エミッタ接地型増幅回路間にエミッタホロア回
路が挿入されていることを特徴とする特許請求の範囲第
1項記載の高周波増幅装置。
(3) The high-frequency amplification device according to claim 1, wherein an emitter follower circuit is inserted between each emitter-grounded amplification circuit.
(4)入力段のトランジスタのエミッタとアース間に抵
抗を挿入し、上記エミッタよりボンディングワイヤーを
介して外部端子を設け、その外部端子から外部アース間
に、所望の周波数の近辺に対して低インピーダンスとな
るようなフィルター回路を設けることを特徴とする特許
請求の範囲第1項記載の高周波増幅装置。 (句 エミッタホロア回路のエミッタ端子より、抵抗を
介して入力段のトランジスタのべ〜スに直流負帰還をか
けることを特徴とする特許請求の範囲第3項記載の高周
波増幅装置。
(4) Insert a resistor between the emitter of the transistor in the input stage and the ground, provide an external terminal from the emitter via a bonding wire, and provide a low impedance in the vicinity of the desired frequency between the external terminal and the external ground. 2. The high frequency amplification device according to claim 1, further comprising a filter circuit such that: 3. The high frequency amplification device according to claim 3, wherein negative DC feedback is applied from the emitter terminal of the emitter follower circuit to the base of the input stage transistor via a resistor.
JP3341784A 1984-02-23 1984-02-23 High frequency amplifier Granted JPS60177710A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3341784A JPS60177710A (en) 1984-02-23 1984-02-23 High frequency amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3341784A JPS60177710A (en) 1984-02-23 1984-02-23 High frequency amplifier

Publications (2)

Publication Number Publication Date
JPS60177710A true JPS60177710A (en) 1985-09-11
JPH0544841B2 JPH0544841B2 (en) 1993-07-07

Family

ID=12385994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3341784A Granted JPS60177710A (en) 1984-02-23 1984-02-23 High frequency amplifier

Country Status (1)

Country Link
JP (1) JPS60177710A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6005441A (en) * 1998-01-21 1999-12-21 Mitsubishi Denki Kabushiki Kaisha Amplifying circuit
GB2329086B (en) * 1997-09-02 2002-06-26 Ford Global Tech Inc Low power RF amplifier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50101865U (en) * 1974-01-25 1975-08-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50101865U (en) * 1974-01-25 1975-08-22

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2329086B (en) * 1997-09-02 2002-06-26 Ford Global Tech Inc Low power RF amplifier
US6005441A (en) * 1998-01-21 1999-12-21 Mitsubishi Denki Kabushiki Kaisha Amplifying circuit

Also Published As

Publication number Publication date
JPH0544841B2 (en) 1993-07-07

Similar Documents

Publication Publication Date Title
US5051706A (en) High frequency power amplifier circuit
EP0893878B1 (en) High frequency oscillating circuit
US4764736A (en) Amplifier for high frequency signal
US4205276A (en) Audio amplifier with low AM radiation
KR960003560B1 (en) Voltage controlling oscillator
US6265944B1 (en) Fully integrated broadband RF voltage amplifier with enhanced voltage gain and method
JPS6043907A (en) Amplifying circuit
US5245298A (en) Voltage controlled oscillator having cascoded output
US3851269A (en) Hum reduction in transistor amplifiers
JPH036107A (en) Voltage controlled oscillator
JPS60177710A (en) High frequency amplifier
US5551075A (en) Semiconductor device including a plurality of interconnected functional integrated circuit blocks operating at high and ultrahigh frequencies, each having a DC distribution line
JP2001060826A (en) Two-band oscillating device
JP2643180B2 (en) Monolithic integrated circuit
JPH0548641B2 (en)
US6388517B1 (en) Input change-over type amplifier and frequency change-over type oscillator using the same
US20090186592A1 (en) Radio receiver and receiving semiconductor integrated circuit
JPH0544842B2 (en)
US3356952A (en) Stabilized mixer oscillator for wide band television receiver
US5793255A (en) Tuned RF amplifier
JPS5922416A (en) High frequency amplifier circuit
JP2565979B2 (en) Local oscillator circuit
KR0154772B1 (en) Wireless frequency output terminal circuit with low output impedance and high band shield characteristics
JPS6229208A (en) Local oscillation circuit
JPS61245627A (en) Oscillating circuit