JPS60176164A - Input/output unit of sequence controller - Google Patents

Abstract

PURPOSE:To enable auto setting of an address and to enable using whichever connector is connected, by connecting connectors to a control unit and by giving data from the control unit side through a bus line. CONSTITUTION:Connectors 1A and 1B are provided at both sides of a device 2, and terminals a1-a16 and b1-b16 are provided on the connectors. An input/output write signal IOW' (express I/O, hereunder) from a control unit of a sequence controller and an I/O read signal IOR' are connected to the terminals a1 and b1 and the terminals a2 and b2, respectively. Address buses A0-A3 and I/O data buses D0-D7 are connected to the terminals a3-a6 and b3-b6 and the terminals a7-a14 and b7-b14, respectively. With this constitution an address can be automatically set by giving data on an address bus from the control unit side through a bus line, and connectors can be used, whichever is connected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field 1] The present invention relates to an input/output crab knit of a sequence controller.

[Background Art] Conventionally, in this type of crab knit, the user specifies an address specific to each kani knit using a dip switch or the like. However, in this conventional system, if the user sets the address incorrectly, the sequence controller will not operate correctly, and there is a risk that the 1i1i control equipment may be destroyed.

[Object of the Invention] The present invention has been made in view of the above-mentioned drawbacks, and its purpose is to provide a self-IJJ system by simply connecting an input/output connector to a control unit consisting of a CPU, etc., without setting a special fixed address. address is set to , and input/output connector 2
To provide an input/output crab knit of a sequence controller which can be connected to any connector among the parts.

1 Disclosure of the Invention 1 Figures 1 to 2 (a) and (b) are drawings showing one embodiment, and in the figures IA and IB are connectors provided at both ends of the container body 2. and each connector IA and IB has a
Each terminal of 1~a+gJ1~Iz16 is provided.Terminal a
Corresponding terminals except between 6 and b6 are directly connected to each other in the device body 2, and the input/output write signal IOW from sequence controller control ll-1 and chive) 10 is connected to all b+. , terminals a2fb2 have input/output signals
Connect IOR, connect address bus Δ.~A3 to terminals Jls-astbs-b(, and connect terminals a7~a+4*
The input/output data paths D0 to D7 are connected to bt to b14, the power supply vcc is connected to the terminal alstb15, and the terminal a
The ground line GND is connected to 16tb+6. In the figure, 38t a b is a decoder,
Decor ・□gu3. The input terminals of a and 3b, which are the first input terminals, are connected to the line of the terminal 83tb3, and one decoder 3a connects the B input terminal, which is the input terminal of m2, to the line of the terminal altbl, and the other decoder 3b
connects the B input terminal, which is the second input terminal, to the line of terminal 121b2. Also, each decoder 3 at 3 b
The enable terminal E of the circuit is connected to the ground via a resistor R1. 4 is a D-type 7-lip 7a-tub;
Connect the terminal to the power supply Vcc, connect the clock terminals C' and LK to one terminal of the decoder 3a, and connect the Q terminal to the diode D.
The enable terminal E1 is connected to the enable terminal E1 through the diode D1, and the Q terminal is connected to the cathode of the diode D1 and the diode D1. )50
It is connected to the connection point with the cathode. Diode D1 has its 7 nonide connected to terminal a6, and diode 1)5 has its anode connected to terminal bG. Diode DI,
D5 constitutes a diode bridge with diode D2, I)6, and diode D2,1)6
The connection point is connected to the enable terminal E through a diode D3, and to the power supply Vcc through a resistor R2. Further, the connection point between the diode D2 and the diode D1 is connected to the power supply Vcc via a resistor R1.

5 is a latch, which connects the terminals IN and ~IN to the terminals a7 to a141b?, respectively. - b14, and the W'1' terminal is connected to the 0 terminal of the decoder a.

This latch 5 has output terminal 0 [I To~O11,T,
is connected to the external control circuit 6 to generate an external output signal to the controlled equipment. '7 a, 71) is 3
This is a signal input circuit in which the number of state buffers equal to the number of input/output data D, to D8 is provided, and the R1]1 signal of the 3-state buffer of the signal input circuit 7a is obtained from the 0 terminal of the decoder 31], and the signal input circuit 7b 3-state buffer RD
The two signals are obtained from one terminal of the decoder 313. Each three-state buffer receives an external human input signal via an external signal conversion circuit 8. The external control circuit 6 uses a relay, SSR, ) transistor, etc., and the external signal conversion circuit 8 converts an external input signal to an internal signal level using a photocoupler or the like. The device body 2 is provided with an input/output terminal block 2a and an input/output display light emitting diode 21) on one side, and a wiring duct space on the other side.

Next, the operation of the present invention will be explained based on the time chart of FIG. As shown in Fig. 4(a), the control unit) 1
Connect the pass line from 0 to the connector IA of the 1st person output unit (U), and connect the connector 113 of the input/output unit (U2) to the fan 99 of the 2nd H person output unit U2.
Connect the connector IA of the human output unit) U2 to the connector IA of the third input/output unit) U3.
If the control unit 10 is connected to
As shown in (e), the data on address bus A2 is
Let the data of A3 be 'L'. Then, the first human output unit connected to the control unit 10)01
As shown in Figure 3 (11), point a is pulled up to L'' through the diode D2 of Therefore, as shown in FIG. 3(i), point b becomes "L" state by the pull-ground resistor R3, and the enable terminals E of decoders 3a, 31] become "L", and the decoder 3a.

31) becomes output enabled and outputs in response to the signals input to the A input terminal and the B input terminal. In this case, the %V point is the state in which the diodes 5 and D6 are reverse biased, and for the pull-up resistor R1 of the next person's crab unit U2, as shown in ft53 figure (o), 9"■ ("). In this state, the data on the address bus A is set to "°'L" as shown in FIG. 3 (,), and the input/output read signal 10 r< shown in FIG. When the 1<DJ signal from the decoder 3b becomes L'' as shown in FIG. Tabas D.

~D7j-, and the control unit 1() reads the external human input signal. Now address bus A,
When the data is 1-'' and the input/output write signal 19W shown in FIG. 3(k) is L, the wT signal of the coder 3a is
As shown in FIG. 1, the control unit 10 is connected to the input/output data bus. The data being output to -D7 is stored in the latch 5 at the rising edge of the WT multiplied signal, and is passed through the external control circuit 6 to turn on and off the external load.

Next is address bus A. If the data is "H" and the input/output write signal OW is l L II, then 7 reprop 4
As shown in Fig. 3(m), the clock terminal CLK of
t+, and at the rising edge, the "I" signal to the D terminal of 7rip 70tube 4 is memorized, and the Q output becomes 3rd and 1st.
As shown in (g), the output becomes "L", and the Q output shown in (f) of FIG. When the 6th output is "L" and the Q output becomes ``H'', a current flows from the Q output to the resistor 1 (3) via the diode D4, and the 1j point becomes ``H''.

1) When the point becomes 'l-1', the enable terminals E of the decoders 3a and 3b become in the state of inhibiting the output of H" and become input terminals.

All outputs are "l-" regardless of the signal input to the B input terminal.
1''. Now, 1) The period '1'1 to 'I'2 during which the point is L'' is the selection period in which the outgoing crab unit can input and output. Also, when the Q output becomes L, the diode 1)
Lower the y point to "[," through 5. Therefore, the 1) point of the next unit FL+ 2 of the crowded crab unit U1 is l
]-++ is selected, and the input/output read signal IOR and input/output write signal lOW shown in FIG.
is effective against the crowded crab unit U2. In this way, each person's output unit) U 1 , U 2 , tJ
3. After completing the reading, give the clock Q f-CL K of the 7 resource 70 and 4, and send the selected output unit one after another to read and write all the human output units F. 52 can be done.

Next, as shown in FIG. 4 (1)), connect the connector IB of the first person output unit U1 to the control unit 10 side, and then connect the connector 113 of the second person output unit U1) to the control unit 10 side.
In the case shown in Fig. 4(a), if you connect the connector IA of the first person output unit (LJ 1) to the connector IA of the next person output unit U3, and then connect the connector 1B of the next person output unit U3 to the connector IA of the person output unit U2. Similarly, address bus A2 is “1”
]ゝ1, A3 is 1. Control unit 1 () so that
When outputs the 7 dress data, it lowers the point a through the diode 1)6 of the human output unit IU1, and the 7 rip 7a
Since the Q output of the knob 4 is I,°, no current is supplied to the point I, and the point b is lowered to l L II by the resistance 1< for the plug-grain. 1] When the point becomes L'', each signal of lOl<, [OW from the control unit 10 becomes effective at 11 and becomes the starvation output unit) U 2 and U3 are the Q outputs of the flip 70 and the knob 4. is "I4", so the diode l) ] , ]')
2 is reverse biased and due to the pull-up resistor 1<, λ" and ξ are pulled to "11" as shown in FIG. 3 (+1), and the address bus A is output from the connector IA. , the data becomes 'H' and is not selected.

Therefore A. The input/output data of the input/output unit U1 can be read using the tlOR and IOW signals.

Address bus A after reading/writing is completed. When the data is "lI" and the input/output write signal 10W is set to "L", 7 rip 70 tsub 4 is set at the rising edge, and the Q output becomes "+4".
゛, Q output is 1. '', current flows through diode D4 at point B and becomes ``H++'', and point Output unit U1 is not selected, and the next human output unit) tJ2 is selected, and it is read from the control unit 10 that it will be disconnected outside.In this way, which terminal is connected to connectors IA and lB of human output unit Y? It may be connected to the control unit 10 side, and the connectors may be connected to 1A and 1A, and IB and 113, but the signal must be input from the input/output unit connector with one power, and the connector with one color power. Must be connected to go out.

Further, 11 in FIG. 4(a) (11) is a connection cable.

[Effect of the Invention 1] Since the present invention is configured as described above, by simply inputting the data on the address bus from the control unit side via the pass line, it can automatically read and write one out-of-the-box data sequentially. This eliminates the occurrence of malfunctions caused by the user's address settings, and prevents accidents such as damage to the controlled equipment@1.Furthermore, it is possible to use either of the two connectors provided. It is possible to freely lay out the layout according to the user's purpose by connecting it to the machine, and there is no limit to the number of connected kaninits, which has the effect of being highly expandable.

4. Fig. 1i1(7) ai 11t Description Fig. 1 is a circuit diagram of an embodiment of the present invention, and Fig. 2(a).

(b) is a two-side view and a side view of the same device, FIG. 3 is a time chart of the same device, FIGS. 3a and 3b are decoders, 4 is a 7-rip 70 amplifier, 5 is a latch, and 1a.

7b is a signal input circuit, a l -' a l G g
l) 1-b l 6 is a terminal, Dl-D'6 is a diode, D, -D are data buses, A, ~A are address buses, IOW is an input/output write signal, "σ ball is a human output Readout symbol, Vcc is power supply, (, LK is clock terminal, CLE<
is a clear terminal, T: is an enable terminal, R, , 11 is a pull-up resistor, and R3 is a pull-down resistor.

Agent Patent Attorney Shi [+1 Ai 711-4 Figure 4 procedural amendment (spontaneous) May 7, 1980 Dear Commissioner of the Japan Patent Office 1, Indication of the case 1980 Patent Application No. 32792 + J' 2, Name sequence of the invention ] Point 0-59 Ninde Kanit 3, Relationship with the case of the person making the amendment Patent applicant's office Address: 1048 Kadoma, Kadoma City, Osaka Prefecture Name (
583) Matsushita Electric Works Co., Ltd. Representative Iku Kobayashi 4, Agent 5, Date of amendment order Voluntary 7, Subject of amendment amended as per attached sheet Application number Jifj 0111S59-32792 No. 1, Claims of the claimed invention Correct as shown below.

[1] The first controller provided with terminals for connecting or wiring the power supply, input/output data path, address bus, input/output write signals, and input/output read signals from the control unit of the sequence controller 0-controller, respectively. A second connector is provided, and the corresponding terminals of both connectors are connected to each other except for the terminal that connects the first line of the address bus, and the unconnected terminals of both connectors are connected to the input terminal of the diode bridge separately. At the same time, both output terminals of the diode bridge are connected to a power supply via a pull-arranging resistor, and a first input terminal and an input/output terminal are connected to a terminal of the connector corresponding to the second line of the address bus. a first decoder of IO evolution, the first decoder having a second input terminal connected to a terminal of the connector [corresponding to the second line signal]; A second decoder of IO evolution, which connects the input terminal of D to the terminal of a connector corresponding to the input/output signal;
A D-type clear block whose terminal is connected to the power supply, whose zero terminal is connected to the second output terminal of the first decoder, whose clear terminal is connected to the at terminal, and whose output is connected to the positive end of the diode ridge. and a latch that multiplies the signal from the first output terminal of the first decoder by WT, latches the input/output data on the data bus, and generates a latch output as an external output signal; and a signal input circuit that controls a 3-state buffer and inputs an external input signal to the data bus, and connects the negative terminal of the diode bridge to the enable terminal of each decoder via a second diode.
The enable terminal is connected to a pull-down terminal and grounded via a pull-down resistor. A sequence controller 0-ra input/output crab knit characterized by the following. ” 2. “Do-Ds J” on page 6, line 1 of the specification of the present application is “
D.

~Corrected as D7J.

3. ``Figure 3 (k)'' on page 8, line 7 of the same page is corrected to ``Figure 3 (e)''.

11 patent attorneys: Ishi 1) Chief Seven

Claims (1)

[Claims] 1) Power supply from the sequence controller control unit,
The first terminal is provided with terminals for connecting or sending and wiring human output data paths, address buses, input/output write signals, and human output output signals, respectively. If you add one fjS2 connector
Next, connect the corresponding terminals of both connectors, excluding the terminal for connecting the first line of the address bus, and connect the unconnected terminals of both connectors to the input ends of the diode bridge separately. Both output terminals are connected to the power supply via pull-up resistors, and the first input terminal is connected to the terminal of the connector corresponding to the second line of the address bus, and the terminal of the connector corresponding to the output write signal is connected to the first input terminal, which is connected to the terminal of the connector corresponding to the second line of the address bus. a decimal decoder having a second input terminal connected to the terminal; the first input terminal is connected to the terminal corresponding to the second line; the second input terminal is connected to the input/output read signal; 1) Connect the terminal to the power supply and connect the clock terminal to ttSl.
Connect the clear terminal to the terminal corresponding to the third line of the address bus, connect the first diode to the enable terminal of each decoder, and connect the Q output to the enable terminal of each decoder. The signal from the D-type 7-lip 70-tube connected to the positive end of the bridge and the first output terminal of the first decoder is set as W'r(;
The output of the second encoder is used to generate a latch output as a signal, and the 3-state buffer 7 is controlled by the output of the second coder, and the external input signal is taken into the data bus. signal input circuit and 411
iii. A sequence controller characterized in that the negative terminal of the diode bridge is connected to the enable terminal of each decoder via a second diode, and the enable terminal is grounded via a pull-down resistor. Crab knit in and out.