JPS60175418A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60175418A JPS60175418A JP3064584A JP3064584A JPS60175418A JP S60175418 A JPS60175418 A JP S60175418A JP 3064584 A JP3064584 A JP 3064584A JP 3064584 A JP3064584 A JP 3064584A JP S60175418 A JPS60175418 A JP S60175418A
- Authority
- JP
- Japan
- Prior art keywords
- chromium
- type silicon
- ohmic contact
- layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052804 chromium Inorganic materials 0.000 claims abstract description 19
- 239000011651 chromium Substances 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229910021357 chromium silicide Inorganic materials 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 241000238557 Decapoda Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の電極形成に関し、詳しくは、一
層目にクロムを金属電極として用いたものの熱処理工程
を含む半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the formation of electrodes for semiconductor devices, and more specifically to a method for manufacturing a semiconductor device including a heat treatment step using chromium as a metal electrode in the first layer. .
従来例の構成とその問題点 従来からクロムは電極金属として広く用いられている。Conventional configuration and its problems Chromium has been widely used as an electrode metal.
これは、シリコンとの接着性に優れ、かつシリコンとの
間にオーム接触が容易に得られるためである。しかしな
がら、単に、室温でクロムをｎ型シリコンに蒸着しただ
けでは、クロムとシリコンの接触抵抗や非オーム接触が
原因となって低損失型トランジスタの場合などでは、そ
の特性を悪くしていた。This is because it has excellent adhesion to silicon and ohmic contact can be easily obtained between it and silicon. However, simply depositing chromium on n-type silicon at room temperature deteriorates the characteristics of low-loss transistors due to contact resistance and non-ohmic contact between chromium and silicon.
以下図面を参照しながら従来のｎｐｎパワートランジス
タを例にし説明する。A conventional npn power transistor will be explained below as an example with reference to the drawings.
第１図にはクロム電極を形成したｎｐｎパワートランジ
スタの構造断面図を示す。第１図において、１はｎ型不
純物のエミッタ拡散層、２はｐ型不純物のベース拡散層
、３はｎ型エピタキシャル成長層、４はｎ型エピサブス
トレート、５はクロムを一層目とする金属電極である。FIG. 1 shows a cross-sectional view of the structure of an npn power transistor in which a chromium electrode is formed. In FIG. 1, 1 is an emitter diffusion layer of n-type impurities, 2 is a base diffusion layer of p-type impurities, 3 is an n-type epitaxial growth layer, 4 is an n-type epitaxial substrate, and 5 is a metal electrode whose first layer is chromium. It is.
以上のように構成された半導体装置について、以下その
動作について説明する。The operation of the semiconductor device configured as described above will be described below.
このｎｐｎパワートランジスタにおいてコレクタ電流Ｉ
Ｃは金属電極６を通じてコレクタからエミッタへと流れ
る。しかしながらこの従来装置の場合、その出力特性は
、第２図に示すように、低電流領域においてオーム接触
が得られなかったり（実線。）、オーム接触が得られて
もその接触抵抗が大きく（点ｍ）、その分トランジスタ
のｖａｔ（ｓＩＬｔ）特性を悪くするという欠点を有し
ていた。In this npn power transistor, the collector current I
C flows from the collector to the emitter through the metal electrode 6. However, in the case of this conventional device, as shown in Figure 2, the output characteristics are such that ohmic contact cannot be obtained in the low current region (solid line), or even if ohmic contact is obtained, the contact resistance is large (point point). m), it had the disadvantage of worsening the vat (sILt) characteristics of the transistor.
発明の目的
本発明はｎ型シリコンとクロムとの間に良好なオーム接
触を得る半導体装置の製造方法を提供するものである。OBJECTS OF THE INVENTION The present invention provides a method of manufacturing a semiconductor device that provides good ohmic contact between n-type silicon and chromium.
発明の構成
本発明の半導体装置の製造方法は、ｎ型シリコンに、一
層目電極として、クロム電極を形成した後、４００°Ｃ
以上の熱処理を行うことであり、これにより、クロムシ
リサイドの形成による良好なオーム接触が得られる。Structure of the Invention The method for manufacturing a semiconductor device of the present invention includes forming a chromium electrode as a first layer electrode on n-type silicon, and then heating the semiconductor device at 400°C.
By performing the above heat treatment, good ohmic contact can be obtained due to the formation of chromium silicide.
実施例の説明
以下本発明の一実施例について、図面を参照しながら説
明する。第３図は本発明実施例によるｎ型シリコンとク
ロムとの接触抵抗の熱処理温度依存性である。接触抵抗
は、Ｖ、Ｌ６Ｍ法でめた。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows the dependence of the contact resistance between n-type silicon and chromium on the heat treatment temperature according to an example of the present invention. The contact resistance was determined by the V, L6M method.
これよりわかるように、４００°Ｃ以上の熱処理を行う
ことにより、ｎ型シリコンとクロムとの接触抵抗は、極
端に減少し、更に、非オーム接触を示していたものもオ
ーム接触となることがわかる。As can be seen, by heat treatment at 400°C or higher, the contact resistance between n-type silicon and chromium is extremely reduced, and even non-ohmic contact becomes ohmic contact. Recognize.
まだ、第４図には、４５０°Ｃにおける熱処理時間と上
述の接触抵抗の関係を示す。これから熱処理時間が長い
程接触抵抗が減少していることがわかる。Furthermore, FIG. 4 shows the relationship between the heat treatment time at 450° C. and the above-mentioned contact resistance. It can be seen from this that the contact resistance decreases as the heat treatment time increases.
第６図は本発明の一実施例におけるｎｐｎパワートラン
ジスタの出力特性を示したもので、第１図の構造のｎｐ
ｎパワートランジスタを４５０’０３０分で熱処理した
ものである。以上のように本実施例によれば、ｎ型シリ
コン基板上に少なくともクロムを一層目に用いた多層金
属膜を形成し、これを４００’Ｃ以上の温度で熱処理す
ることにより、第３図、第４図の実験結果からもわかる
ように良好なオーム接触（Ｒｏｎ ）が得られ、ｖａｘ
（ｓａｔ）特性の改善が得られる。FIG. 6 shows the output characteristics of the npn power transistor in one embodiment of the present invention.
This is an n-power transistor heat-treated for 450'030 minutes. As described above, according to this embodiment, a multilayer metal film using at least chromium as the first layer is formed on an n-type silicon substrate, and by heat-treating the film at a temperature of 400'C or more, as shown in FIG. As can be seen from the experimental results in Figure 4, good ohmic contact (Ron) was obtained, and the vax
(sat) characteristics can be improved.
発明の効果
以上のように本発明は、ｎ型シリコン基板上に少なくと
もクロムを一層目に用いた多層金属膜を形成した場合、
４００°Ｃ以上の熱処理を行うことにより、オーム接触
もしくは接触抵抗の改善が得られることを明らかにした
ものであり、第１表にこの発明をｎｐｎバイポーラトラ
ンジスタ、ｎチャンネルＭＯ５ＦＥＴ 、ダイオードに
応用した場合の効果を示す。これより、その実用的効果
は非常に大なるものがある。Effects of the Invention As described above, the present invention has the following advantages: When a multilayer metal film using at least chromium as the first layer is formed on an n-type silicon substrate,
It has been revealed that ohmic contact or contact resistance can be improved by heat treatment at 400°C or higher, and Table 1 shows the results when this invention is applied to npn bipolar transistors, n-channel MO5FETs, and diodes. shows the effect of Therefore, its practical effects are very large.
第１図はｎｐｎパワートランジスタの断面図、第２図は
従来例のトランジスタの出力特性図、第３図は本発明実
施例によるｎ型シリコンとクロムとの接触抵抗の熱処理
温度依存特性図、第４図はｎ型シリコンとクロムとの接
触抵抗の熱処理時間依存特性図、第６図は本発明の一実
施例によるｎｐｎパワートランジスタの出力特性図であ
る。
１・・・・・ｎ型不純物の工ばツタ拡散層、２・・・・
・・ｎ型不純物のベース拡散層、３・・・・・・ｎ型エ
ピタキシャル成長層、４・・・・・・ｎ型エビサブスト
レート、５・・・・・・クロムを一層目とする金属電極
。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
ＣＥ
第３図
熱処理？ＪＬＣ”Ｃ）
第４図
然長惺時閉 （ケ２FIG. 1 is a cross-sectional view of an npn power transistor, FIG. 2 is an output characteristic diagram of a conventional transistor, FIG. 3 is a characteristic diagram of heat treatment temperature dependence of contact resistance between n-type silicon and chromium according to an embodiment of the present invention, and FIG. FIG. 4 is a heat treatment time dependence characteristic diagram of contact resistance between n-type silicon and chromium, and FIG. 6 is an output characteristic diagram of an npn power transistor according to an embodiment of the present invention. 1...N-type impurity ivy diffusion layer, 2...
...N-type impurity base diffusion layer, 3...N-type epitaxial growth layer, 4...N-type shrimp substrate, 5...Metal electrode with chromium as the first layer. . Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 CE Figure 3 Heat treatment? JLC”C) 4th natural closing time (Ke2
Claims (2)
層金属電極を形成し、これを４００ ’Ｃ以上の温度で
熱処理することを特徴とする半導体装置の製造方法。(1) A method for manufacturing a semiconductor device, which comprises forming a multilayer metal electrode using chromium as the first layer on an n-type silicon substrate, and heat-treating this at a temperature of 400'C or higher.
であることを特徴とする特許請求の範囲第１項に記載の
半導体装置の製造方法。(2) The specific resistance of the n-type silicon substrate is 0. 2. The method of manufacturing a semiconductor device according to claim 1, wherein o2Ωα or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3064584A JPS60175418A (en) | 1984-02-20 | 1984-02-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3064584A JPS60175418A (en) | 1984-02-20 | 1984-02-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60175418A true JPS60175418A (en) | 1985-09-09 |
Family
ID=12309552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3064584A Pending JPS60175418A (en) | 1984-02-20 | 1984-02-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60175418A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5277547A (en) * | 1991-05-18 | 1994-01-11 | Usui Kokusai Sangyo Kaisha Ltd. | Motor fan unit |
-
1984
- 1984-02-20 JP JP3064584A patent/JPS60175418A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5277547A (en) * | 1991-05-18 | 1994-01-11 | Usui Kokusai Sangyo Kaisha Ltd. | Motor fan unit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH05347413A (en) | Manufacture of semiconductor device | |
| JP3727827B2 (en) | Semiconductor device | |
| JPH02110975A (en) | Manufacture of semiconductor device | |
| JPH0456472B2 (en) | ||
| JPH0546106B2 (en) | ||
| JPS60175418A (en) | Manufacture of semiconductor device | |
| JPH02130868A (en) | Semiconductor device | |
| JPS6116574A (en) | Field-effect transistor and manufacture thereof | |
| JPS6116515A (en) | Manufacture of semiconductor device | |
| JPH04291966A (en) | Schottky barrier semiconductor device | |
| JPH08288503A (en) | Semiconductor device having planar high withstand voltage element and manufacturing method thereof | |
| JPH0454395B2 (en) | ||
| JPS62210674A (en) | Semiconductor device | |
| JP3130219B2 (en) | Semiconductor device | |
| JPS5957476A (en) | Manufacture of semiconductor device | |
| JP2538600B2 (en) | Method for manufacturing semiconductor device | |
| JPS59145520A (en) | Manufacture of semiconductor device | |
| JPS60169168A (en) | Electrode structure of semiconductor element | |
| JP2000252466A (en) | Power semiconductor device and manufacture thereof | |
| JPH029137A (en) | Manufacture of magnetically arranged vertical double-diffusion type power mosfet having very small source/drain region | |
| JPS60132365A (en) | Manufacture of semiconductor device | |
| JPH0766218A (en) | Bi-polar transistor and its manufacture | |
| JPS61125079A (en) | Semiconductor device and manufacture thereof | |
| JPS59163864A (en) | Semiconductor device | |
| JPS6298772A (en) | Semiconductor device |