JPS6017535A - Decimal multiple generator - Google Patents

Decimal multiple generator

Info

Publication number
JPS6017535A
JPS6017535A JP58124941A JP12494183A JPS6017535A JP S6017535 A JPS6017535 A JP S6017535A JP 58124941 A JP58124941 A JP 58124941A JP 12494183 A JP12494183 A JP 12494183A JP S6017535 A JPS6017535 A JP S6017535A
Authority
JP
Japan
Prior art keywords
binary coded
multiplicand
coded decimal
decimal number
digit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58124941A
Other languages
Japanese (ja)
Inventor
Koji Saito
康治 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58124941A priority Critical patent/JPS6017535A/en
Publication of JPS6017535A publication Critical patent/JPS6017535A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4915—Multiplying; Dividing

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  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To shorten execution time of instruction and reduce a control memory capacity by forming a m-time multiplicand without depending on a microprogram by only giving a multiplicand with (n) digits and the multiplier with 1-digit which designates the m-times. CONSTITUTION:The m-times of the multiplicand is formed without depending on the microprogram by only giving the multiplicand with n-digits and the multiplier with 1-digit which designates the m-times. For example, retain the multiplicand of the binary coded decimal number with n-digits on a register 1 and the multiplier of the binary coded decimal number with 1-digit on a register 5, generate 1-, 2-, 4- and 8-times multiplicands by binary coded decimal number generation circuits 2, 3 and 4, and input them to selection circuits 8 and 9 through signal conductors 101 to 401. Next, generate selection information S0 and S1, by a value (m) of the register 5 by a decode circuit 6, and input it to the selection circuit 8 and 8. Generate the submode signal etc., by a decode circuit 7 and input them to a decimal arithmometer 10. Operate binary coded decimal number by the decimal arithmometer 10 and input the operation output to a register 11 through a signal conductor 1001.

Description

【発明の詳細な説明】 （１）　発明の属する技術分野の説明 本発明は、データ処理装置に於ける１０進演算装置に関
し、特に、２進化１０進数を扱える１０進倍数発発生器
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a decimal arithmetic device in a data processing device, and in particular to a decimal multiple generator that can handle binary coded decimal numbers. be.

（２）　従来技術の説明 従来、この種の１０進倍数発生器は、被乗数の１倍、２
倍、４倍、８倍の倍数しか発生する事ができず、被乗数
の３倍、５倍、６倍、７倍、９倍を必要とする時には、
マイクロプログラム【よって被乗数の１倍、２倍、４倍
、８倍の組み合わせによって作成していたために、シフ
ト命令の実行時間が増加し、システム性能が低下する欠
点がめった。(2) Description of the prior art Conventionally, this type of decimal multiple generator has a multiplicand of 1 and 2.
When you can only generate multiples of times, four times, eight times, and need three times, five times, six times, seven times, nine times the multiplicand,
Microprograms were created using combinations of 1, 2, 4, and 8 times the multiplicand, which often resulted in increased execution time for shift instructions and decreased system performance.

又、従来技術では、被乗数のｍ倍（ｍ＝ｏ、ｉ〜９）を
指定する１桁（４ビツト）の２進化１０進数をマイクロ
プログラムで解読（分岐、判断）をし、被乗数のｍ倍を
作成し゛（いたために、マイクロプログラムのステップ
数が増加し、制御メモリの容量を増大化する要因となっ
ていた。In addition, in the conventional technology, a 1-digit (4-bit) binary coded decimal number that specifies m times the multiplicand (m = o, i to 9) is decoded (branched, judged) by a microprogram, and m times the multiplicand. Because of this, the number of steps in the microprogram increases, which causes an increase in the capacity of the control memory.

（３）　発明の詳細な説明 本発明は従来の上記事情に鑑みてなされたものであり、
従って本発明の目的は、０桁の２進化１０進数（被乗数
）と、このｍ倍（ｍ−０，１〜９）を指定する１桁（４
ビツト）の２進化ｌＯ進数（乗数）を与えるだけで、マ
イクロプログラムの助けを借りる事なしに、被乗数のｍ
倍（ｍ＝ｏ、ｉ〜９）を作成することにより、上記欠点
である性能低下、マイクロプログラムを格納する制御メ
モリの容量増加という問題を解決し、ン７ト命令の実行
時間の短縮を計９、かつ、制御メモリ容量の削減を割っ
た新規なデータ処理装置を提供する事にある。(3) Detailed description of the invention The present invention has been made in view of the above-mentioned conventional circumstances.
Therefore, the purpose of the present invention is to obtain a 0-digit binary coded decimal number (multiplicand) and a 1-digit (4
By simply giving the binary coded lO base number (multiplier) of the multiplicand, m
By creating a double (m=o, i to 9), the above-mentioned disadvantages of performance degradation and increase in the capacity of control memory for storing microprograms can be solved, and the execution time of 7-point instructions can be shortened. 9, and to provide a new data processing device with reduced control memory capacity.

（４）　発明の構成 上記目的を達成する為に、本発明に係る１０進倍数発生
器は、０桁の２進化１０進数（被乗数）と、このｍ倍（
ｍ−０，１〜・９）を指定する１桁（４ピント）の２進
化１０進数（乗数）を入力とする１ｏ進倍数発生器に１
於いて、２進化１０進数の８・４・２＠ｌコードへの変
換機能と１ビツトシフト機能とを有する２進化１０進数
２倍発生回路を３段接続し、被乗数の１倍、２倍、４倍
、８倍のＪＯ進数を発生させるように構成した２進化１
０進数２倍（ｔ＝ｏ、ｉ、２．３）発生回路と、該２進
化１０進２倍発生回路の４倍、８倍の出力を廁びオール
ゼロ出力のできる第１の選択手段と、ＭＩ記２進化１０
進２１倍発生回路の１倍、２倍の出力を透びオールゼロ
出力のできる第２の選択手段と、前記第１の選択手段と
第２の選択手段との出力を入力とする２進化１０進数の
加減算ができる１０進演３＋器と、乗数である４ビツト
の２進化１０進数によって前記第１の踊択手段、第２の
選択手段の切換情報、演算器の加減力モード及びキャリ
を発生する変換器とを具備して構成され、ｒｌ（’）２
進化１０進数のｍ倍（ｍ＝０．１〜９）を発生ずること
を％欲とする。(4) Structure of the Invention In order to achieve the above object, the decimal multiple generator according to the present invention generates a 0-digit binary coded decimal number (multiplicand) and m times this number (
1 to a 1o-adic multiple generator that inputs a 1-digit (4 pinto) binary coded decimal number (multiplier) specifying m-0, 1 to 9).
In this case, three stages of binary coded decimal number doubling generation circuits having the function of converting the binary coded decimal number to 8, 4, 2@l code and the function of 1 bit shift are connected, and the multiplicand is multiplied by 1, 2, and 4. Binary evolution 1 configured to generate double and eight times JO base numbers
a decimal number doubling (t=o, i, 2.3) generation circuit, and a first selection means capable of outputting four times or eight times as much as the binary coded decimal number doubling generating circuit to provide an all-zero output; MI Chronicle 2 Evolution 10
a second selection means capable of outputting all zeros through the 1x and 2x outputs of the decimal 21x generation circuit; and a binary coded decimal number whose inputs are the outputs of the first selection means and the second selection means. A decimal 3+ unit that can add and subtract , and a 4-bit binary coded decimal number as a multiplier generate switching information for the first selection means and second selection means, an addition/subtraction force mode of the arithmetic unit, and a carry. rl(')2
% desire is to generate m times the evolved decimal number (m = 0.1 to 9).

即ち、従来、０桁の２進化１０進数（被乗数）のｍ　倍
（ｍ＝０．１〜９）を作るためにへは、マイクロプログ
ラムにより被乗数をｍ回加算したり、被乗数の１倍、２
倍、４倍、８倍を発生する１０進倍数発生器を利用して
、この１倍、２倍、４倍、８倍の組み合わせで被乗数の
ｍ倍（ｍ＝０．１〜９）を作っていたものを、本発明に
おいてはマイクロプログラムの助けなしで、０桁の被乗
数と１桁の乗数を与えるだけで被乗数のｍ倍（ｍ−０，
１〜９）を発生する事ができる。In other words, conventionally, in order to create m times (m = 0.1 to 9) a 0-digit binary coded decimal number (multiplicand), the microprogram must be used to add the multiplicand m times, or add 1 times the multiplicand, 2 times the multiplicand.
Using a decimal multiple generator that generates times, 4 times, and 8 times, create m times the multiplicand (m = 0.1 to 9) by combining 1 times, 2 times, 4 times, and 8 times. In the present invention, the multiplicand can be multiplied by m (m-0,
1 to 9) can be generated.

（５）　発明の詳細な説明 次に本発明をその好ましい一実施例について図面を参照
して詳細に説明する。(5) Detailed Description of the Invention Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

第１図は本発明の基本的構成要素となる２進化１０進数
２倍発生回路の一実施例を示す基本図でおり、２進化１
０進数の８−４＠２・ｌコードを５・４−２−１コード
に変換し、この５・４・２◆１コードを左に１ビツトシ
フトする機能を表わしている。FIG. 1 is a basic diagram showing an embodiment of a binary coded decimal number doubling circuit which is a basic component of the present invention.
It represents the function of converting a 0-base 8-4@2.l code into a 5.4-2-1 code and shifting this 5.4.2◆1 code one bit to the left.

第　１　表 第１表＃：ｔ２進化１０進数の８−４−２−１コードと
５−４・２や１コードの対応表であり、その論理式は次
の通りである。Table 1 Table 1 #: This is a correspondence table between the 8-4-2-1 code and the 5-4.2 and 1 code in t2 evolved decimal notation, and its logical formula is as follows.

第２図は第１図と第１表で示した２進化１０進数２倍発
生回路を３段積み上げて、０桁の２進化１０進数の１倍
、２倍、４倍、８倍を発生できるように構成した本発明
の基本構成となるｎ桁２進化１０進数２倍発生回路の一
実施例を示す基本図である。Figure 2 shows how the binary coded decimal number double generation circuit shown in Figure 1 and Table 1 is stacked in three stages to generate 1, 2, 4, and 8 times the 0-digit binary coded decimal number. FIG. 2 is a basic diagram showing an embodiment of an n-digit binary coded decimal number doubling generation circuit which is the basic configuration of the present invention and is configured as shown in FIG.

但し、０桁の１０進数のリーディングゼロが１以上でな
い時には、オーバーフローする事がおる。However, if the leading zero of the 0-digit decimal number is not 1 or more, overflow may occur.

第３図は本発明による一因施例のブロック構成図である
。FIG. 3 is a block diagram of one embodiment of the present invention.

第３図において、０桁の２進化１０進数（被乗数）をレ
ジスタ１に、１桁の２進化１０進数（乗数）をレジスタ
５に保持する。２進化１０進数を０桁扱える第２図に示
す如き２進化１０進数２倍発生回路２．３．４をシリア
ルに接続し、信号線１０１で被乗数の１倍を、イイ号線
２０１で被乗数の２倍を、信号線３０１で被条数の４倍
を、信号線４０１て被乗数の８倍をそれぞれ得るように
接続されでいる。In FIG. 3, a 0-digit binary coded decimal number (multiplicand) is held in register 1, and a 1-digit binary coded decimal number (multiplicand) is held in register 5. A binary coded decimal number double generation circuit 2.3.4 as shown in FIG. The signal line 301 is connected to obtain four times the multiplicand, and the signal line 401 is connected to obtain eight times the multiplicand.

選択回路８＆：は信号線３０１と信号線４０１が接続さ
ｆｌ、ており、選択回路９には信号線１０１と信号線２
０１が接続されている。The selection circuit 8&: has the signal line 301 and the signal line 401 connected, and the selection circuit 9 has the signal line 101 and the signal line 2 connected.
01 is connected.

デコード回路６、デコード回路７は信号線５０１により
レジスタ５に接続されている。デコード回路６はレジス
タ５（乗数）の値ｍＧｌ：、より第２表に示す８０Ｓ　
８１のコードを発生する。The decode circuit 6 and the decode circuit 7 are connected to the register 5 by a signal line 501. The decoding circuit 6 uses the value mGl of the register 5 (multiplier): 80S shown in Table 2.
81 code is generated.

第２表 ＳＯ：第１選択回路の選択情報 Ｓｌ：第２選択回路の選択情報 Ｓｕｂ　Ｍｏｄｅ　：　１０進加減算器の減算指定Ｃａ
ｒｒｙ：　１０進加減算器の入力となるキャリＣａｒｒ
ｙ　：　入力となるキャリそのもの第２表は被乗数のｍ
倍指定時の第１％第２の選択手段の選択情報と１０進加
減算器の演算子−ド／入カキヤリを示す。イ’Ｑ号線６
０１を介してコードｓＯにより選択回路８を制御し、信
号線６０２を介してコートＳｌにＸり選択回路９を制御
する。デコード回路７はレジスタ５（乗数）の値ｍによ
り第２表ｔｉ　示ｔ　Ｓｕｂ　Ｍｏｄｅ　トＣａｒｒｙ
を決定する。Table 2 SO: Selection information of the first selection circuit Sl: Selection information of the second selection circuit Sub Mode: Subtraction designation Ca of the decimal adder/subtractor
rry: Carry that is input to the decimal adder/subtractor
y: The input carry itself Table 2 is the multiplicand m
The selection information of the 1st % second selection means and the operator code/input value of the decimal adder/subtractor when specifying times are shown. I'Q line 6
The selection circuit 8 is controlled by the code sO through the signal line 602, and the selection circuit 9 is controlled by the code sO through the signal line 602. The decoding circuit 7 uses the value m of the register 5 (multiplier) to select the sub mode shown in the second table.
Determine.

１０進加減算器１０は信号線８０１を介し選択回路８を
Ａ入力、信号線９０１を介し選択回路９をＢ入力とし、
信号線７０１を介するデコード回路７のＳｕｂＭｏｄｅ
イｉＡ号と、信号線７０２を介するデコード回路７のＣ
ａｒｒｙ信号とによってＡ±Ｂの２進化１０進数演算を
する事ができるよう接続されている。The decimal adder/subtractor 10 has an A input to the selection circuit 8 via a signal line 801, an input B to the selection circuit 9 via a signal line 901,
SubMode of decoding circuit 7 via signal line 701
iA and C of the decoding circuit 7 via the signal line 702.
It is connected so that binary coded decimal operation of A±B can be performed by the arry signal.

演算出力（積）は信号線１００１を通してレジスタ１１
へ送られる。The calculation output (product) is sent to the register 11 through the signal line 1001.
sent to.

次にレジスタ５（乗数）の値ｍにより決まる選択回路ｓ
、４ｉ択回路９及び加減算器１０の動作を示す。Next, the selection circuit s determined by the value m of register 5 (multiplier)
, 4i selection circuit 9 and the adder/subtractor 10.

レジスタ５（乗数）の値ｍ　選択回路８　力１鍼算−モ
ード選択回路９０　ゼロ出力　士　ゼロ出力 １　ゼロ出力　＋　１倍出力 ２　ゼロ出力　−ト　２倍出力 ３　４倍出力　１倍出力 ４　４倍出力　士　ゼロ出力 ５　４倍出力　＋　１倍出力 ６　４倍出力　＋　２借出カ フ　８倍出力　１倍出力 ８　８倍出力　士　ゼロ出力 ９　８イ音出力　＋　ｌイΔ出力 以上の演算を行り事により （０桁の１０進数（被乗数））Ｘ（１桁の１０進数（乗
数用の演算を実行する。Value m of register 5 (multiplier) Selection circuit 8 Force 1 acupuncture mode selection circuit 90 Zero output shi Zero output 1 Zero output + 1x output 2 Zero output -T 2x output 3 4x output 1x output 4 4x Output: Zero output 5 4x output + 1x output 6 4x output + 2 borrowed cuff 8x output 1x output 8 8x output By doing so, (0-digit decimal number (multiplicand)) x (1-digit decimal number (multiplicand) is executed.

（６）　発明の詳細な説明 本発明には、以上説明したようら一１ｎ桁の１０進数（
被乗数）と１桁の１０進数（乗数）により即時に積を得
られるように構成することにより１命令実行時間を短縮
し、システム性能を向上させ、制御メモリの容量を減ら
す事ができるという効果がある。(6) Detailed description of the invention As explained above, the present invention includes a 11n-digit decimal number (
By configuring the system so that the product can be obtained immediately using a multiplicand) and a 1-digit decimal number (multiplier), the execution time for one instruction can be shortened, system performance can be improved, and the capacity of control memory can be reduced. be.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の基本的構成要素でβる２進化１０進数
２倍発生回路の一実施例を示す概略構成図、ｍ２図は第
１図で示した２進化１０進数２倍発生回路を３段積み上
げて、０桁の２進化１０進数の１倍、２倍、４倍、８倍
を発生できるように構成した本発明の基本的概略構成図
、第３図は本発明に係る１０進倍数発生器の一実施例を
示すブロック構成図でｂる。 １ψ−争ｎ桁２進化１０進数（被乗数）用レジスタ、２
．３．４＠豐・１０進数２倍発生回路、５ｓ・・１桁２
進化１０進数（乗数）用レジスタ、６．７・・・デコ・
−ダ、８．９１１・ｅ選択回路、１０−・・１０進加減
算器、１１・・・演初−出力（積）を受ける１／ジスタ 特許出願人　日本電気株式会社 代　理　人　弁理士　熊　谷　雄太部 箔１ｍ 、１川、演川−困一一一一〇−休埠典 ×１Fig. 1 is a schematic configuration diagram showing an embodiment of a binary coded decimal number doubling circuit which is a basic component of the present invention, and Fig. m2 shows the binary coded decimal number doubling circuit shown in Fig. 1. Figure 3 is a basic schematic configuration diagram of the present invention configured to generate 1, 2, 4, and 8 times a 0-digit binary coded decimal number by stacking them in three stages. FIG. 3 is a block diagram showing one embodiment of a multiple generator. 1ψ-contention n-digit binary coded decimal number (multiplicand) register, 2
．． 3.4 @ Toyo・Decimal number double generation circuit, 5s...1 digit 2
Register for evolved decimal number (multiplier), 6.7...Deco
- da, 8.911・e selection circuit, 10-... decimal adder/subtractor, 11... 1/gyster that receives the first-output (product) Patent applicant NEC Corporation Representative Patent attorney Kumagai Yutabehaku 1m, 1 river, Enkawa-Kuichi-1110-Kyuubori x 1

Claims (1)

【特許請求の範囲】[Claims] ９桁の２進化１０進数（被乗数）と、このｍ倍（ｍ＝０
．１〜９）を指定する１桁（４ピント）の２進化１０進
数（乗数）を入力とする１０進倍数発生器に於いて、２
進化１０進数の８−４−２・１コードから５・４・２１
１１コードへの変換機能と１ビツトシフト機能とを有す
る２進化１０進数２倍発生回路を３段接続し、被乗数の
１倍、２倍、４倍、８倍の１０進数を発生させるように
構成した２進化１０進数２′倍（ｌ＝０．１．２．３）
発生回路と、該２進化１０進２′倍発生回路の４倍、８
倍の出力を選びオールゼロ出力のできる第１の選択手段
と、前記２進化１０進２′倍発生回路の１倍、２倍の出
力を選びオールゼロ出力のできる第２の選択手段と、前
記第１の選択手段と第２の選択手段との出力を入力とす
る２進化１０進数の加減算ができる１０進演算器と、乗
数である４ピントの２進化１０進数によって前記第１の
選択手段、第２の選択手段の切換情報、演算器の加減算
モード及びキャリを発生する変換器とを具備し、９桁の
２進化１０進数のｍ倍（ｍ＝ｏ、　ｉ〜９）を発生でき
るように構成したことを４１！１′故とする１０進倍数
発生器。A 9-digit binary coded decimal number (multiplicand) and m times this (m=0
．． In a decimal multiple generator that inputs a 1-digit (4 pinto) binary coded decimal number (multiplier) specifying 1 to 9), 2
Evolutionary decimal 8-4-2.1 code to 5.4.21
Three stages of binary coded decimal number doubling generation circuits having a conversion function to 11 code and a 1-bit shift function are connected to generate decimal numbers that are 1, 2, 4, and 8 times the multiplicand. Binary coded decimal number 2' times (l=0.1.2.3)
generation circuit, and 4 times the binary coded decimal 2' generation circuit, 8
a first selection means capable of selecting twice the output and outputting all zeros; a second selection means capable of selecting one and twice the output of the binary coded decimal 2' generator circuit and producing all zero output; a decimal arithmetic unit capable of adding and subtracting binary coded decimal numbers which input the outputs of the selection means and the second selection means; It is equipped with switching information for the selection means, an addition/subtraction mode of the arithmetic unit, and a converter that generates a carry, and is configured to be able to generate m times (m=o, i to 9) a 9-digit binary coded decimal number. A decimal multiple generator that assumes 41!1'.
JP58124941A 1983-07-08 1983-07-08 Decimal multiple generator Pending JPS6017535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58124941A JPS6017535A (en) 1983-07-08 1983-07-08 Decimal multiple generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58124941A JPS6017535A (en) 1983-07-08 1983-07-08 Decimal multiple generator

Publications (1)

Publication Number Publication Date
JPS6017535A true JPS6017535A (en) 1985-01-29

Family

ID=14897975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58124941A Pending JPS6017535A (en) 1983-07-08 1983-07-08 Decimal multiple generator

Country Status (1)

Country Link
JP (1) JPS6017535A (en)

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