JPS60173992A - Subordinate address switching system in subordinate synchronizing network - Google Patents

Abstract

PURPOSE:To obtain a subordinate address switching system in a subordinate synchronizing network which enables improvement in transmitting data quality by changing over the subordinate address according to received results of information on a transmitting channel condition and on a subordinate intra-station device. CONSTITUTION:When clock signals CL1-CLn transferred from a high-order station and an asynchronous clock signal are reproduced, the system detects them by an asynchronous detecting circuit 17 and outputs asynchronous alarm signals SALM1-SALMn to an alarm multiplex circuit 20. The circuit 20 multiplies and transfers them to a low-order subordinate station by using them as fault information of signals CL1-CLn due to abnormality of the intra-station system device. The low-order station takes OR of line alarm signals LALM1- LALMn by an OR circuit 16 and adds them to a subordinate address changeover controlling circuit 4. The circuit 4 decides that a clock distributing channel transferring the signals SALM1-SALMn is abnormal and designates a subordinate address changeover circuit 5 to change over to other clock distributing channels.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a slave synchronization network consisting of a plurality of slave stations that regenerates a clock signal synchronized with a clock signal from a master station and transfers it to lower slave stations, and particularly relates to This invention relates to a dependent optical switching system for maintaining the synchronization state of a clock distribution network.

(b) Technical Background The dependent synchronization method in a digital transmission system that transmits audio, images, data, etc. through a transmission path is such that one of the stations making up the network is the master station (mask station) and all other All stations are slave stations, and information regarding the frequency of the clock signal from the master station is transmitted to the slave stations, and each slave station uses various clocks synchronized with the clock signal from the master station as part of this information. This is a method of reproducing signals.

Therefore, in the slave synchronization method, it is necessary to transmit information regarding the frequency of the clock signal from the master station to all slave stations either directly or via other slave stations.

This is called a clock distribution path.

If the clock distribution path becomes abnormal due to a failure in the transmission path, information about the frequency of the clock signal cannot be transmitted, so multiple clock distribution paths are prepared, and if the current clock distribution path becomes abnormal, a backup clock can be used. A method is used to maintain a clock distribution path between the master station and all slave stations by switching to a distribution path.

However, the countermeasures against failures in the dependent synchronization method are mainly countermeasures against failures in the transmission line.

Currently, countermeasures do not necessarily include information abnormalities regarding the frequency of clock signals due to abnormalities in synchronous system terminal equipment, etc. It is desired to realize a dependent synchronization method that takes these countermeasures into consideration.

and (c) Problems with the Prior Art Next, a conventional slave synchronization system related to the above will be explained with reference to two drawings.

FIG. 1 shows a conventional slave synchronization scheme in a transmission system.

In the figure, 1 is a network synchronization device, 2 and 3 are synchronous system terminal devices, 4 is a dependent optical switching control circuit, 5 is a dependent optical switching circuit, 6 is a network synchronization circuit, 7, 8.9 are frequency conversion circuits, 10.24
11 is a PCl'l signal transmitting section, 11.15 is a Plo signal 7 receiving section, and 12 is a clock receiving circuit.

Figure 3 shows a timing generation circuit.

Note that a is the transmission line for the upper station, b is the transmission line for the lower station, and L
A! , MI ~ LALMn is the line alarm signal, C
LI~CLn are clock signals from the upper station, PI, l
'2. F3 indicates the clock signal reproduced and converted by the network synchronizer, and Flo indicates the output signal frequency of the timing generation circuit 13, respectively.

In the slave synchronization method shown in FIG. 1, the synchronization system terminal device 3 receives a plurality of clock signals CLI to CLn from an upper station (not shown) and generates necessary lock signals (PI, F2, F3).
network synchronization device that regenerates, converts, and outputs 1. Based on data from the upper station (not shown), the second station sends a corresponding line alarm signal (LA
Synchronous terminal device 2 that sends out LMI-LALMn)
．． Clock signal from network synchronizer 1 (Fl, F2.F3
Synchronous terminal equipment that multiplex-converts and outputs data based on 3. 4. Dependent optical switching control circuit that determines the clock signal (CLI to CLn) to be selected from the state of the line alarm signal (1,8 LMI to LALMn) from the synchronous system terminal device 2. A slave optical switching circuit 5, which is located in the network synchronizer 1 and switches and selects a plurality of clock signals (CLI to G[, n) from a higher-level station (not shown) under the control of the slave optical switching control circuit 4. A network synchronization circuit 6 for regenerating a clock signal with a new frequency synchronized with the clock signal (one of CLI to CLn) selected by the dependent switching circuit 5. Il
i! ! Frequency conversion circuits 7, 8, 9, . A PCM signal sending unit 10 that sends an I''CM signal (a signal obtained by pulse code modulating data) to an upper station (not shown). A PCM signal receiving unit that receives a PCM signal from an upper station (not shown). 1
13. A clock receiving circuit 12 that receives one predetermined clock signal (Fl in FIG. 1) among a plurality of clock signals (PI, F2, F3, etc.) of the frequency conversion circuits (7, 8, 9).
A timing generation circuit 13 that generates a timing signal frequency FIO necessary for data processing using the clock signal F1 received by the clock reception circuit 12. Timing generation circuit 1
I also like the timing signal (frequency F10) from 3.
CM signal transmitter 14 that multiplex converts the CM signal and outputs it to the lower station (not shown).Lower station (not shown)
PCM signal receiving unit 1 that receives the “1” CM signal from
5 to f+17.

In the conventional dependent synchronous network system shown in FIG.

A method for detecting a failure in the clock distribution path from the upper station (not shown) is to detect I"CM due to an abnormality in the transmission path a.
Signal abnormality (out of synchronization due to undetected synchronization signal at the beginning of the data frame or clock signal CI).

1 to CLn disconnection, etc.) was not monitored by the PCM signal receiving unit 11, and only φ was monitored.

Conventionally, in this method, the output frequency FO of the frequency converter 7,
The difference between the output frequency Fl of the frequency converter 8 and the output frequency F10 of the timing generation circuit 13 is r'cM signal transmitter 1.
4) are the same frequency,
That is, since there was no frequency conversion function other than the network synchronization circuit 6, there would be no problem if only abnormalities in the transmission line a were monitored.

However, with the development of synchronization systems, various frequencies (for example, 1
Next group, second order group frequency 1.544Mb/s, 6.312
(M+1/S, etc.), a plurality of frequency converters 7°8.9 (these typically using phase-locked loop circuits) became necessary. in this case,
Transmission path a is normal, but an asynchronous clock signal (C
Even if an asynchronous signal of
There is a drawback that even if there is an abnormality in the current clock distribution path, it is not possible to switch to the backup clock distribution path.

(d) Purpose of the Invention The object of the present invention is to provide a new dependent switching method in a dependent synchronous network that eliminates the above-mentioned drawbacks, and in particular, in a dependent synchronous network that enables further improvement of transmission data quality. The objective is to realize a dependent switching method.

(e) Structure of the invention Consists of a master station that distributes clock debt to all subordinate stations, and a plurality of slave stations that reproduce clock signals synchronized with the clock signal from the master station and transfer them to lower subordinate stations. In the dependent synchronous network, means for monitoring the state of a transmission path between an upper station of each of the dependent stations and the dependent station, and a clock signal sent from the main station and each of the dependent stations are transmitted to the main station. means for detecting that the oscillator is in an asynchronous state, and each of the dependent stations is in an asynchronous state with respect to the network synchronization phase synchronization oscillator of the dependent station, and transmitting the asynchronous state detection signal to the lower subordinate station. and means for selecting the asynchronous state signal from an upper station of the dependent station, and switching the dependent light depending on the reception result of the state information of the transmission path and the state information of the device in the dependent station, This can be achieved by a dependent switching method in a dependent synchronous network, which is characterized by the ability to further improve data quality.

(f) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 2 shows an embodiment of a dependent synchronous network according to the present invention.

In the figure, 16 is an OR circuit, 17 to 19 are asynchronous detection circuits, and 20 is an alarm multiplexing circuit. The same symbols as in Figure 1 indicate the same contents, and SAL old to SA
LMn indicates an asynchronous alarm signal from the alarm multiplexing circuit 20, respectively.

This embodiment consists of the components shown in FIG. 1, and a subordinate optical switching control circuit 4 which calculates the logical sum of the alarm signals ^LMI to ALMn sent from the upper station (not shown) and the asynchronous alarm signals SALM1 to SALMn. - Output OR circuit 16
．． Asynchronous detection circuit 172 that detects the asynchronous state of the network synchronization circuit 6; Asynchronous detection circuit 18° that detects the asynchronous state of the frequency conversion circuit (7, '8°9); Timing generation circuit 13
an asynchronous detection circuit 19 for detecting an asynchronous state of . Asynchronous alarm signal SAL from the asynchronous detection circuit (17-19)
It is comprised of an alarm multiplexing circuit 20 that multiplexes M1 to 5ALIIIn and sends it to lower dependent stations.

Next, the operation of this embodiment will be explained.

The PCM signal receiving unit 1 receives data and clock signals (CLI to CI, n) from upper stations (not shown), which are usually the highest priority routes for the corresponding station, among the multiple routes.
1. It is accepted at the output of the slave optical switching circuit 5 of the network synchronizer 1.

In the case of this embodiment, if there is no fault in the transmission path a and normal data is transferred,
' shall be determined.

The network synchronization circuit 6 composed of a PLL (phase 1 closed loop circuit) receives a plurality of clock signals (
CLI~CLn).

It reproduces a clock signal having an arbitrary frequency synchronized with the selected one clock signal (CLI to CLn) and outputs it to the two-frequency conversion circuit (7 to 9). At this time, if a clock signal asynchronous to the transferred clock signal (CLI to CLn) is reproduced, the asynchronous detection circuit 17 detects it and outputs asynchronous alarm signals SALMI to SALMn to the alarm multiplexing circuit 20.

Next, the clock signal regenerated by the network synchronization circuit 6 is converted to the frequency (Fl, F2, F3) required by the synchronization system terminal equipment 3 in the frequency conversion circuit (7 to 9), and is transmitted to each synchronization system terminal station. It is sent to device 3. Note that the case where the synchronous system terminal device 3 shown in FIG. 2 receives the frequency F1 is shown. If synchronization loss occurs in the frequency conversion circuits (7 to 9), the asynchronous detection circuit 18 detects it and issues an asynchronous alarm signal SAL to S.
ALMn is output to the alarm multiplexing circuit 20.

In the synchronization system end station device 3, the clock signal F1 reproduced from the network synchronization device 1 is received by the clock reception circuit 12, and the clock signal frequency FIO generated by the timing generation circuit 13 based on the clock signal F1 is sent to the PCM transmission section. It is transferred from I4 to the subordinate station via the transmission line. If an asynchronous state or the like occurs in the timing generation circuit 13, the asynchronous detection circuit 197 detects it and issues an asynchronous alarm signal SALMI~
SALMn is output to the alarm multiplexing circuit 20.

The alarm multiplexing circuit 20 includes asynchronous detection circuits (17 to 19)
), this asynchronous alarm signal SAL old ~ SALM is received.
Clock signals (CI, 1-CL
n ) failure information as a lower dependent station (not shown).
Transfer to.

Alarm multiplexing (indicated by the solid line in Figure 2), in which the output of the circuit 20 is directly transmitted to a lower dependent station (not shown) using a modem, etc. (shown by the solid line in Figure 2); As shown, there is a method of transmitting the data along with other data through the I'C 11 transmitter 14.

” Asynchronous alarm signals SALM1 to SALMn are sent from the second station (not shown) as described above.
is sent out, in the lower station (in this explanation, it refers to the device shown in FIG. 2), the logical sum circuit 16 takes the logical sum with the line alarm signals LALM 1 to LALMn, and the subordinate optical switching control circuit 4 Therefore, the dependent optical switching control circuit 4 outputs asynchronous alarm signals SALMI to S/II, 4
The clock distribution path that has sent out n is determined to be abnormal, and the dependent optical switching circuit 5 is instructed to switch to another clock distribution path.

(g) Effects of the Invention According to the present invention as described in section 2, it is possible to provide a dependent synchronization method in a dependent synchronization network that can accurately detect failures in clock distribution paths and further improve network synchronization quality. It has the effect of saying.

[Brief explanation of the drawing]

FIG. 1 shows a conventional slave synchronization system in a transmission system, and FIG. 2 shows an embodiment of a slave synchronization network according to the present invention. In the figure, 1 is a network synchronization device, 2 and 3 are synchronous system terminal devices, 4 is a dependent optical switching control circuit, 5 is a dependent optical switching circuit, 6 is a network synchronization circuit, 7, 8.9 are frequency conversion circuits, 10.14
is a PCM signal transmitter, 11°15 is a PCM signal receiver,
12 is a clock receiving circuit. 13 is a timing generation circuit, and 16 is an OR circuit. Reference numerals 17 to 19 indicate an asynchronous detection circuit, and numeral 20 indicates an alarm multiplexing circuit.

Claims (1)

[Claims] In a dependent synchronization network consisting of a master station that distributes a clock signal to all subordinate stations, and a plurality of slave stations that reproduce a clock signal synchronized with the clock signal from the master station and transfer it to lower subordinate stations, means for monitoring the state of a transmission path between an upper station of each dependent station and the dependent station, and a clock signal sent from the main station and each dependent station is in an asynchronous state with respect to a main oscillator in the main station; , in each of the dependent stations, means for detecting that the dependent station is in an asynchronous state with respect to a phase synchronized oscillator for network synchronization; means for transmitting the asynchronous state detection signal to the subordinate dependent station; means for selecting the asynchronous state signal from an upper station of the slave station, and switching the slave light according to the reception result of the state information of the transmission path and the state information of the device in the slave station. Optical switching method.