JPS60172824A - Analog digital converting circuit - Google Patents

Abstract

PURPOSE:To obtain an A/D converter at high speed, low power consumption and small size by constituting the circuit that the high speed converting performance being the highest feature of the parallel type is maintained and the cascade connection type is used together. CONSTITUTION:An A/D1 is a cascade connection type A/D converter having m- bit resolution, m-set of amplifiers A1, A2-Am are connected in cascade, and consists of comparators C1, C2-Cm of the same number connected in parallel with the input terminals of the amplifiers A1, A2-Am and a code converter EC1 converting a gray code output signal from the comparators C1, C2-Cm into a binary code. When the conversion of a parallel A/D converter A/D2 is attained by using a clock signal of duty ratio of 50%, if the convertion of the cascade connection type A/D converter A/D1 is finished in the pause period, the converting speed of the A/D converter using the cascade connection type and the parallel type in common is equal to the converting speed of the parallel A/D converter. Moreover, since the circuit scale is decreased because of the number of cascade connection types is increased and the low power consumption, small size and economy are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an analog-to-digital conversion circuit that performs high-speed conversion operations.

(Prior art) Conventionally, among analog-to-digital converters (hereinafter referred to as A/D converters) that convert analog signals to digital signals, parallel type and series series type circuits have mainly been used to meet the demand for high-speed performance. Transducers of different configurations are used.

In the parallel type, 2N-1 comparators (N is the number of bits) are used as main circuits. In other words, since there are 2N combinations of an N-bit digital signal expressed in binary code, when an N-bit digital signal is obtained by an A/D converter, 2N combinations of an analog input signal and a digital output signal are required. must be matched.

One way to do this is to use 2N-1 comparators each having an analog input signal as its first input and a reference voltage obtained by equally dividing the input level range of the analog signal into 2N as its second input. This is the basis of the parallel form, and it is the first characteristic. It is well known that with this configuration, signal conversion from analog to digital is completed instantaneously with a single conversion operation using a clock signal, and therefore the highest speed conversion is possible. However, since 2N-1 comparators are required,
Due to the necessity of a logic circuit for digitally encoding the comparator output into N bits, the circuit scale becomes extremely large.As a result, the number of elements and power consumption increase proportionately. When realizing LSI, there were drawbacks that hindered miniaturization, economy, and high reliability.

On the other hand, the series-parallel type A/D converter has an upper bit parallel type A/D converter that performs rough conversion, a lower bit parallel type A/D converter that performs fine conversion, and an upper bit parallel type A/D converter that performs fine conversion.
A digital converter that converts the output of the D converter back into an analog signal.
An analog converter (hereinafter abbreviated as D/A converter),
It consists of a subtraction circuit that subtracts the analog output signal of the D/A converter from the analog input signal. The analog input signal is first converted by a high-order bit parallel type A/D converter to obtain a final output high-order pit digital signal, and this output is simultaneously input to the D/A converter.

The D/A converter output signal is subtracted from the analog input signal by the operation of the subtraction circuit, and the obtained analog signal is input to the lower bit parallel type A/D converter to perform the second conversion. This output becomes the lower pit digital signal as the final output. The conversion operation of the series-parallel A/D converter is completed by the series of circuit operations described above, but
During this time, the analog input signal must be held at a constant signal level by the sample and hold circuit. The conversion speed is slower than the parallel type by the amount of the D/A converter. In addition, the circuit scale is close to that of the parallel type due to the need for two circuits of parallel type A/D converters and the need for a D/A converter with N-bit accuracy, increasing the speed of LSI.

There were problems in trying to make it smaller, more economical, and more reliable.

(Objective of the Invention) In order to solve these drawbacks, the present invention aims to reduce the circuit scale by creating a circuit configuration that uses the cascade type while maintaining high-speed conversion performance, which is the greatest feature of the parallel type. The present invention provides a high speed, low power consumption, and compact A/D converter.

(Structure and operation of the invention) This will be explained in detail below with reference to the drawings.

Figure 1 shows a combination type A/D of cascade type and parallel type according to the present invention.
1 is a basic circuit block diagram based on an embodiment of a converter; FIG.

A/DI is a cascaded A/D converter, A1. A, ~Am are amplifiers, EC1 is a code converter, SIN is an analog input signal, VRBF is a reference voltage, CI, C7 ~ Cm are comparators,
A/D2 is a parallel A/D converter, CLK is a clock input signal, 002 to 0rrl are amplifier output signals, Di-
Dm and Dm+i~I)m+. is the digital output signal.

Further, FIGS. 2 and 3 are diagrams for explaining the input/output characteristics of the amplifier, and VFs indicates the full-scale voltage.

A/D1 is a cascade type A/D converter with a resolution of m bits, and A1. m amplifiers A, ~Am are connected in cascade, and the same number of comparators C, , C, ~Cm1 are connected in parallel with the input terminals of amplifiers A, , A, ~Am, and these comparators C,,C, It consists of a code converter EC, which converts the Gray code output signal of ~Cm into a binary code. Amplifier A
, , A, ~Am, when o-vFs is input as the analog input signal SIN and 1/2VF8 is input as the reference voltage VREF, the output signal is VOUT = 21sIN-V
When the voltage difference between the two terminals is 0, VOUT; When an input signal voltage of o-vFs is applied to the first stage amplifier A when connected, each amplifier A1. The output characteristics of A, -Am are as shown in FIG.

By comparing these output signals with the reference voltage VREF in the comparators C1, C, ~Cm, 1/2 VFS + "/4 in correspondence with the input signal level
The level of VFS~'/2''VFS is determined, and the m-bit cascaded A/D converter A/D1 is established.The sign of the digital output signal of the cascaded A/D converter A/DI described here is The rule is Gray code, but each amplifier A, ,A2
It is easy to make a natural binary code by changing the input/output characteristics of ~Am, and in this case, the code converter E
It is clear that C1 can be omitted. In other words, the cascade-connected input/output characteristics are VouT:2 as shown in Figure 3.
SIN (when 0≦SIN<VREF) + Vot+
t=2 (5IN-VREF) (VREF≦SIN
<at vFs> If an amplifier is used, as in the previous case, by comparing each output signal with the reference voltage vREF, 1/2 VFS + 1/, i vFs −
The level of 1/2' VFS is determined, and an m-bit cascade type A/D converter A/D1 of natural binary code can be realized.

After obtaining an m-bit digital output signal by the conversion operation of the cascaded A/D converter A/D1 using such means, the final stage amplifier Am in the cascaded A/D converter A/Dl
The output signal is converted as an analog input signal of an n-pit parallel type A/D converter A/D2 to obtain an n-bit digital output signal.

As described above, a digital signal in which the output of the cascade A/D converter A/D1 is the upper bit and the output of the parallel A/D converter A/D 2 is the lower bit is a combination of the cascade type and the parallel type. can be obtained by the A/D converter of the present invention having a configuration of When the conversion operation of the parallel type A/D converter A/D2 is performed using the clock signal of the 50th duty register, if the conversion of the cascaded type A/D converter A/D1 is completed within the pause period, then the cascaded type The conversion speed of a parallel type A/D converter is equivalent to that of a parallel type A/D converter.

Furthermore, in terms of the ratio of the number of conversion bits between the cascade type and the parallel type, an increase in the number of cascade types means that the circuit scale can be reduced, leading to lower power consumption, smaller size, and economicalization. Therefore, the first stage is a cascade type A/D converter, and the second stage is a parallel type A/D converter.
By using a combination type configured with converters, it is possible to realize an A/D converter with low power consumption, small size, high reliability, and high speed.

FIG. 4 shows a combination type A/ of the cascade type and parallel type according to the present invention.
This is another embodiment of the D converter. D, ~Dn and Dn+
, ~Dn+□ is a digital output signal, 0° is an analog output signal of A/D2, Am-1 is an amplifier, Cm-1 is a comparator, and 0m-1 is an output signal of the amplifier.

The other constituent circuits are the same as the embodiment shown in FIG. The digital output signal of both A/D converters is a cascade-type and parallel-type A/D converter with a configuration in which the first stage is the upper bit and the second stage is the lower bit. The analog input signal is subjected to n-bit conversion by the parallel A/D converter A/D2 under the control of a clock signal, and the digital output signals become final digital output signals D1 to Dn. In parallel with this conversion operation, the remaining analog signal 0° after n-bit transformation is generated and used as an input signal to the cascaded A/D converter A/D1. The cascaded A/D converter A/D1 is the first
The conversion operation is exactly the same as in the embodiment shown in the figure, and the resulting digital output signal is the final output Dn+, ~Dn
It becomes +□.

Although the parallel A/D converter A/D2 is originally a circuit that outputs a digital signal, it can also generate an analog signal with an additional circuit. FIG. 5 is a circuit diagram explaining signal generation of O8, and FIG. 6 shows its characteristics. How to generate the analog signal to the cascaded A/D converter A/D 1 will be explained below. All + A13
HA45~A+rrl+11 AO is amplifier, al r
a2+ 63~am/2 are reference voltage terminals, IN,, I
N, ~INn, ru, -'ry are input terminals, Os
s*Osa+Ots~O1m+1 +0° is amplifier A18. AHsHA15~A+m++ output signal, C
l1ICIt * C13 to C1m are comparators, EC is a code converter, + VREF + -VREF is a reference voltage source, Rtt + Rst r Rss r R14+R
sa r R16~R, m is the reference resistance, D'L8B
-DM8B is a digital output signal. In this case, the analog signal generation circuit uses (2γ2)+1 circuits that are the same as the amplifiers used in the cascaded A/D converter A/D1.
+ Ass + The analog input signal SIN is used as a common input for the first input of A+s to A1m+1, and the voltage of terminal a1 is used as a reference voltage for each second input, and the voltage of terminal a1 is sent to amplifier All, terminal a2 is sent to amplifier A13, and terminal A3 is connected to amplifier A15, terminal am/2 is connected to amplifier A1m+1, and every other reference voltage terminal VREF of parallel type A/D converter A/D2 is connected as shown in FIG. At this time, the output signal of the amplifier obtained as shown in FIG. 6 is connected to an amplifier A having an OR input terminal. The output signal of amplifier A,1 is applied to input terminal IN, and the output signal of amplifier A8.1 is applied to input terminal IN. output signal to the input terminal IN2, . . . , amplifier A1. The analog signal O8 is generated by connecting the output signal of the amplifier A1m+1 to the input terminal IN, . . . and the output signal of the amplifier A1m+1 to the input terminal IN. Specifically, 1. Amplifier A. Since the input is in an OR configuration, the level of the analog human input signal SIN is the same as that of terminal a1.

If it is within the range of child a2, outputs 011 and 0,3 are used as input signals, and A of 011""013 is at the maximum level (Figure 6), and the level difference between 011 and 013 is maximum at points 81 and 82. A minimum level of O8 is obtained at the point. Next, when the analog input signal SIN is between terminals 82 and 85, the output is O1;
Since Ots is at a high level, it becomes 0 due to the function of the input section.
,3 and OSS are the input signals 0,3=01. The maximum level is obtained at point A2 (FIG. 6), and the minimum level O6 is obtained at points 82 and 83, where the difference between 013 and 0.50 levels is maximum.

Thereafter, by repeating the same operation, an analog signal having characteristics that can be connected as an input to the cascaded A/D converter A/DI in the subsequent stage can be generated.

As described above, in the configuration of a combined cascade type and parallel type A/D converter in which the output of the parallel type A/D converter A/D2 is the upper bit and the output of A/D1 is the lower bit, In general, this corresponds to a cascade type in which the dynamic range of the input signal does not change under the condition that the conversion accuracy becomes more severe as the lower bits become lower, so that it is an effective conversion operation in terms of accuracy.

Furthermore, it is clear from the circuit configuration that this embodiment has the same features as those described in the embodiment of FIG. Therefore, even in the combined form of this configuration, high speed, high precision, and low power consumption are achieved.

A small, highly reliable A/D converter can be realized.

The two-stage configuration using the cascade type and parallel type A/D converters has been described above based on the embodiment, but the features can also be achieved when the combination type configuration is divided into three stages: the front stage, the middle stage, and the rear stage and combined with each stage. It is possible to take advantage of
It is clear that an A/D converter with low power consumption, small size, and high reliability is desired.

(Effects of the Invention) As explained in detail in Plate 1 above, by making the A/D converter a combination of cascade type and parallel type, configuration 17i] takes advantage of the features of the simple cascade type and converts it into a fully parallel type. The circuit scale can be reduced in comparison. Reducing the circuit scale has the effect of reducing the number of elements and power consumption, leading to smaller size, higher reliability, and
It brings great advantages in economicization. Moreover, the conversion speed can be realized without impairing the conversion speed of the parallel type.

Because it has high-speed performance, element-level circuit configuration, and low power consumption, it is ideal for LSI integration, and is an A/D that is high speed, low power consumption, compact, highly reliable, and highly economical.
Converter can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of an A/D converter according to the present invention, FIG. 2 is a characteristic diagram showing an example of input/output characteristics of an amplifier used in the present invention, and FIG. 3 is a block diagram showing an example of the input/output characteristics of an amplifier used in the present invention. 4 is a block diagram showing another embodiment of the A/D converter according to the present invention, and FIG. 5 is a characteristic diagram showing another example of the input/output characteristics of the A/D converter of the present invention. FIG. 6 is a block diagram for explaining the generation, and is a diagram showing the input/output characteristics of the analog signal generating circuit used in the present invention. A,, A2-Am-1+ Am + All + A1
31 At5-A +m++ + Ao°°゛amplifier,
C1+ c2~crrl-1+ Cm + Co +
C121c13~C1m... Comparator, EC,, EC・
... Code converter, A/D 1... Cascade type A/D converter, A/D2... Parallel type A/D converter, SIN...
Analog input signal, VREF r + VREF + V
REF”・Reference voltage, CLK...Clock input signal, D1~Dm, Dm+1~Dman+DH~Dy1
+Dn++~Dn+mr DLSB-DMSB-digital output signal, Ol, O□~0m-1+0rr
x011+O+5rOHs~011T++1゜Oo・・
・Amplifier output, alz 82+ 83~am/2...
Base single voltage terminal, R11+Ru+ R131R141R
151R16-R+m...'Reference resistance, IN,, IN
, ~INn, IN, ~lNn-... Amplifier state Figure 5 Torture Figure 6 input signal

Claims (1)

[Claims] A plurality of stages of amplifiers and comparators each receiving a corresponding analog signal and a reference voltage are used. The output signal of each amplifier is input to the next stage amplifier and comparator. A cascade type A/D converter configured to be connected in cascade so as to produce a digital output signal, and an analog output of the amplifier at the final stage in the cascade type A/D converter or an analog input signal to be converted is input and converted. a parallel type A/D converter which uses a digital output signal to be reproduced later as a final digital output signal, and the input of the parallel type A/D converter is connected to the last stage of the cascaded type A/D converter. When the converted analog input signal is an analog output of an amplifier, the analog input signal to be converted becomes the input of the amplifier at the first stage of the front-packed cascade type A/D converter, and the input of the parallel type A/D converter is the converted analog input signal. In some cases, the parallel type A/
By arranging the analog output of the D converter to be the input of the amplifier at the first stage of the cascade type A/D converter, the analog input signal to be converted is converted into a digital signal in synchronization with a clock signal. an analog-to-digital conversion circuit configured to