JPS60171728A - Dry etching unit - Google Patents

Dry etching unit

Info

Publication number
JPS60171728A
JPS60171728A JP2707284A JP2707284A JPS60171728A JP S60171728 A JPS60171728 A JP S60171728A JP 2707284 A JP2707284 A JP 2707284A JP 2707284 A JP2707284 A JP 2707284A JP S60171728 A JPS60171728 A JP S60171728A
Authority
JP
Japan
Prior art keywords
temperature
pipes
temperature control
chamber
lower electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2707284A
Other languages
Japanese (ja)
Inventor
Haruo Sasaki
晴夫 佐々木
Kazuyuki Nishimura
西村 和行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2707284A priority Critical patent/JPS60171728A/en
Publication of JPS60171728A publication Critical patent/JPS60171728A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To enable a wafer to be etched at a uniform speed for improving the pattern precision, by arranging a parallel-plate electrode consisting of upper and lower electrodes within a chamber while burying a plurality of ring-shaped temperature control pipes in the lower electrode, any by circulating temperature controlled liquids independently in each of the pipes. CONSTITUTION:A chamber 1 is mounted on a stage 3 while it is hermatically sealed by means of an O ring 2. A parallel-plate electrode consisting of an upper electrode 4 and a lower electrode 5 is arranged within the chamber 1. The upper and lower electrodes 4 and 5 are grounded. A plurality of ring-shaped temperature control pipes 7 are buried in the lower electrode 5, and temperature controlled liquids 8a, 8b, 8c and 8d which are constantly temperature controlled by a temperature control unit (not shown) are independently circulated in each of the pipes. The temperature controlled liquids 8a-8d are independently controlled so as to have different temperatures from one another. Further, the temperature control pipes 7 are surrounded by a heat insulating material 9 so that the temperature precision of each pipe 7 is maintained by preventing the pipes from dissipating heat to or receiving it from the outside.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体製造工程において半導体ウェハをエツチ
ングするドライエツチング装置lこ関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a dry etching apparatus for etching semiconductor wafers in a semiconductor manufacturing process.

〔発明の背景〕[Background of the invention]

半導体のウェーハ製造技術lこおいてエツチング精度の
向上は、ウェーハ上に形成するパターン精度の向上、あ
るいはパターン形成歩留りに大きく影響する重要な事項
である。そして、エツチング精度を左右しエツチングの
均二性に影響を与える1つの重要なパラメータは、ウェ
ーハ温度である。
In semiconductor wafer manufacturing technology, improving etching accuracy is an important issue that greatly affects the improvement of pattern accuracy formed on wafers or the pattern formation yield. One important parameter that influences etching accuracy and affects etching uniformity is wafer temperature.

ウェーハ温度がエツチング速度に大きな影響を及ぼすこ
とは古くから知られており、従来からウェーハの温度制
御には種々の工夫がなされてきた。
It has been known for a long time that wafer temperature has a large effect on etching speed, and various techniques have been used to control wafer temperature.

その1つとし°C、ウェーハを吸着あるいは載置する側
の電極全体をヒータオたは温調液により一定温度に制御
する方式が採用されている。しかし、この方式ではウェ
ーハ全体を同一温度にしか制御できないので、ウェーハ
の中心部と周辺部とでエツチング速度に差異を生じ、エ
ツチング量のバラ゛ツキを皆無にできないという欠点が
あった。
One such method is to control the temperature of the entire electrode on the side where the wafer is adsorbed or placed at a constant temperature using a heater or a temperature control liquid. However, since this method can only control the entire wafer at the same temperature, there is a problem in that the etching rate differs between the center and the periphery of the wafer, making it impossible to completely eliminate variations in the amount of etching.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、エツチング速度がウェーハ温度に依存
することを利用し、ウェーハの中心部と周辺部とのエツ
チングのバラ゛ツキを無くしてエツチングの均一性を確
保し、パター7の高精度化と歩留り向上とを実現し得る
ドライエツチング装置を提供することにある。
The purpose of the present invention is to utilize the fact that the etching rate depends on the wafer temperature to eliminate variations in etching between the center and the periphery of the wafer to ensure etching uniformity and to improve the precision of the putter 7. It is an object of the present invention to provide a dry etching apparatus that can realize the improvement in yield and yield.

〔発明の概要〕[Summary of the invention]

本発明は、上記目的を達成するために、上部電極と下部
電極とよりなる平行平板zhをチャンバ内に配設し、か
つ下部電極に複数の温調パイプをリング状に埋設し、こ
の温調パイプにそれぞれ独立に温調液を循環するように
構成したことを特徴とする。
In order to achieve the above object, the present invention disposes a parallel plate zh consisting of an upper electrode and a lower electrode in a chamber, and embeds a plurality of temperature control pipes in a ring shape in the lower electrode. It is characterized by a configuration in which temperature control liquid is circulated through each pipe independently.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を図により説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

チャンバエが0リング2を介して気密シールされた状態
でステージ3上に装着されており、その内部に上部電極
4、下部電極5カ)らなる平行平板電極が配設されてい
る。上部電極4と下部電極5との間には高周波電源6が
接続され、下部電極5側は接地されている。また下部電
極5には複数のリング状の温調パイプ7が埋め込まれて
おり、それぞれには各々独立して図示しない温調装置l
こより常時温度制御された温調液8a、8b、8C18
dが循環するようにな°つている。温調液8a〜8dは
各々異なった温度になるよう独立制御されており、かつ
温調パイプ7の周りは断熱材9で覆われ、外部との熱の
受け渡しを防止して各パイプ7の温度精度を保つように
なっている。以上の構成により、fi4i5上のウェー
ハ10の温度を同心円分布になるようζこコントロール
することができる。
A chamber is mounted on a stage 3 in a state where it is hermetically sealed via an O-ring 2, and parallel plate electrodes consisting of an upper electrode 4 and a lower electrode 5 are disposed inside the chamber. A high frequency power source 6 is connected between the upper electrode 4 and the lower electrode 5, and the lower electrode 5 side is grounded. Further, a plurality of ring-shaped temperature control pipes 7 are embedded in the lower electrode 5, and each has an independent temperature control device l (not shown).
Temperature regulating liquids 8a, 8b, 8C18 whose temperature is constantly controlled by this
d is beginning to circulate. The temperature control liquids 8a to 8d are independently controlled to have different temperatures, and the temperature control pipes 7 are covered with a heat insulating material 9 to prevent heat transfer to the outside and maintain the temperature of each pipe 7. It is designed to maintain accuracy. With the above configuration, the temperature of the wafer 10 on the fi4i5 can be controlled to have a concentric distribution.

次に作用(とついて説明する。半導体ウェーハ10を工
゛ソチングする場合、図に示すようにエツチング処理室
内の下部電極5上にウェーハ10を搬送し、チャンバ1
をかぶせてから処理室内をステージ3の排気口3 、a
から真空ポンプにて一定圧力になるまで排気する。一定
圧力下でチャンバエのガス供給1コ1aよりエツチング
ガスを供給後、エツチング圧力が安定するのを待って高
周波電源6により高周波電圧を印加し、上部電極4と下
部電極5との間にプラズマ放電を起こさせ、化学反応お
よび物理反応によりウェーハ10上の膜をエツチングし
ていく。
Next, the operation will be explained. When etching the semiconductor wafer 10, as shown in the figure, the wafer 10 is transferred onto the lower electrode 5 in the etching processing chamber, and the etching process is carried out in the chamber 1.
After covering the processing chamber with stage 3 exhaust port 3,a
Then, use a vacuum pump to evacuate until a constant pressure is reached. After supplying etching gas from the gas supply 1a of the chamber under constant pressure, wait until the etching pressure becomes stable and apply a high frequency voltage from the high frequency power supply 6 to generate plasma discharge between the upper electrode 4 and the lower electrode 5. The film on the wafer 10 is etched by chemical and physical reactions.

この場合、エツチングはエツチングガスおよび膜の材質
fこ応じ、ウェーハ10中心部から周辺部へ輪を広げる
ように進行するか、またはその逆に進行しようとする。
In this case, depending on the etching gas and the material of the film, the etching tends to proceed in a circular manner from the center of the wafer 10 to the periphery, or vice versa.

しかし、温調パイプ71こよりエツチングの進行が速い
部分の温度を低くし、また進行が遅い部分の温度を高く
することにより。
However, by lowering the temperature of the portion where etching progresses faster than the temperature control pipe 71, and increasing the temperature of the portion where etching progresses slowly.

ウェーハ1o上の膜の工”ソチング速度を制御し、ウェ
ーハ1o上のエツチングを均一化でキル。
The etching speed of the film on the wafer 1o is controlled, and the etching on the wafer 1o is uniformized and killed.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように、本発明によれば、上部
電極と下部w、極とよりなる平行平板1を極をチャンバ
内に配設し、かつ下部電極に複数の温り4パイプをリン
グ状lこ埋設し、この温調パイプにそれぞれ独立に温調
液を循環するように構成してなるので、ウェーハ内のエ
ツチング速度が均一化し、パターン7ir度を向上させ
、パターン形成の歩留りを向上させることができる。
As is clear from the above description, according to the present invention, a parallel plate 1 consisting of an upper electrode, a lower part w, and a pole is disposed in a chamber, and a plurality of heating pipes are connected to the lower electrode as a ring. Since the temperature control liquid is configured to be embedded in the wafer and circulated independently through the temperature control pipes, the etching speed within the wafer is made uniform, improving the pattern irradiance and improving the yield of pattern formation. can be done.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明になるドライエツチング装置4の一実bm例
を示す断面図である。 I・・・チャンバ、 3゛・・・ステージ、4・・・上
部電極、 5・・・下部電極、 6・・・高周波電源、
7・・・温調パイプ、 8a〜8d・・・温調液、9・
・・断熱材、1o・・・ウェーハ X−+、ノ
The figure is a sectional view showing an example of the dry etching device 4 according to the present invention. I...Chamber, 3゛...Stage, 4...Upper electrode, 5...Lower electrode, 6...High frequency power supply,
7...Temperature control pipe, 8a-8d...Temperature control liquid, 9.
...Insulation material, 1o...Wafer X-+, No

Claims (1)

【特許請求の範囲】[Claims] 上部電極と下部電極とよりなる平行平板電極をチャンバ
内に配設してなるドライエツチング装置において、下部
電極に複数のリング状の温調パイプを埋設し、この温調
パイプにそれぞれ独立に温調液を循環するように構成し
たことを特徴とするドライエツチング装置。
In a dry etching device in which a parallel plate electrode consisting of an upper electrode and a lower electrode is arranged in a chamber, a plurality of ring-shaped temperature control pipes are embedded in the lower electrode, and each temperature control pipe can independently control the temperature. A dry etching device characterized by being configured to circulate a liquid.
JP2707284A 1984-02-17 1984-02-17 Dry etching unit Pending JPS60171728A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2707284A JPS60171728A (en) 1984-02-17 1984-02-17 Dry etching unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2707284A JPS60171728A (en) 1984-02-17 1984-02-17 Dry etching unit

Publications (1)

Publication Number Publication Date
JPS60171728A true JPS60171728A (en) 1985-09-05

Family

ID=12210860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2707284A Pending JPS60171728A (en) 1984-02-17 1984-02-17 Dry etching unit

Country Status (1)

Country Link
JP (1) JPS60171728A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01225121A (en) * 1988-03-04 1989-09-08 Hitachi Ltd Low-temperature dry etching system
US5445709A (en) * 1992-11-19 1995-08-29 Hitachi, Ltd. Anisotropic etching method and apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01225121A (en) * 1988-03-04 1989-09-08 Hitachi Ltd Low-temperature dry etching system
US5445709A (en) * 1992-11-19 1995-08-29 Hitachi, Ltd. Anisotropic etching method and apparatus
US5766498A (en) * 1992-11-19 1998-06-16 Hitachi, Ltd. Anisotropic etching method and apparatus

Similar Documents

Publication Publication Date Title
US10257887B2 (en) Substrate support assembly
US4971653A (en) Temperature controlled chuck for elevated temperature etch processing
JP2680338B2 (en) Electrostatic chuck device
TW200807560A (en) Substrate processing with rapid temperature gradient control
JP3242166B2 (en) Etching equipment
KR101164829B1 (en) Methods and apparatus for tuning a set of plasma processing steps
JPH08316215A (en) Gas heat transfer plasma treating device
JPS60208836A (en) Plasma etching device
TWI406348B (en) Dynamic temperature backside gas control for improved within-substrate process uniformity
KR19990088280A (en) Sputtering apparatus
JPH09320799A (en) Plasma processor and plasma processing method
JPH05243191A (en) Dry etching device
US5789324A (en) Uniform gas flow arrangements
JPH0487321A (en) Holding device of object to be treated in vacuum treatment apparatus
JPS60171728A (en) Dry etching unit
JP3583294B2 (en) Plasma emission device and plasma processing device
CN104282611A (en) Plasma processing cavity and static chuck thereof
JP6085106B2 (en) Plasma processing apparatus and plasma processing method
JP3372244B2 (en) Plasma processing equipment
KR100239405B1 (en) Semiconductor fabricating system
JPH08333681A (en) Apparatus for surface chemical treatment of flat sample by using active gas
JPS6230329A (en) Dry etching device
US6210594B1 (en) Near substrate reactant homogenization apparatus
JPH0237717A (en) Processor
JP2687012B2 (en) Plasma etching equipment