JPS6017137B2 - Duplicated memory data copying method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention enables an information processing system having duplicated memories to execute data copying for matching the contents of the duplicated memories without interfering with online operation. The present invention relates to a data copying method for a duplex memory that allows error detection to occur using an existing error detection circuit.

Figure 1 shows an overview of an information processing system with dual memory for high reliability.
-n is a central processing unit, 2-0 and 2-1 are memory controllers, 3-0 and 3-1 are memories, 4 is a common bus, and 5 is a copy bus.

Each of the central processing units 1-0 to 11n performs online processing using memories 3-0 and 3-1. When the central processing unit 1-n is absent and the central processing unit 1-n writes data to the memory, the same data is written to both memories 3-0 and 3-1, but the central processing unit 1-n or 1-
When each of n retrieves data from memory, the data read from either memory is sent to the requesting central processing unit. When an error is detected in the data read from the memory 3-0 or 3--, the faulty memory is disconnected from the system and the faulty memory is repaired.
If a failure occurs in the memory 3-1, the central processing units 1-0 to 11n will continue to perform online processing using the normal memory 3-1 even while the memory 3-1 is being repaired. Continue. When the repair of memory 3-1 is completed, the entire contents of memory 3-1 are exposed and the read data is transferred to memory controller 2-1, copy bus 5 and memory controller 2-1.
The data is sent to the memory 3-1 via the controller 2-1, and written in the memory 3-1. When copying data, control is simple if all areas of memory are copied at once by temporarily prohibiting access requests from central processing units 1-0 and 11-n, but this method Then online driving will be interrupted.

Furthermore, if data errors are detected and corrected during each process of reading, transferring, and writing data for copying, the detection/correction circuit becomes complicated and the copying time increases.
The present invention is based on the above consideration, and is capable of copying data without interrupting online operation in an information processing system equipped with a duplex memory, and of preventing data errors occurring in the process of copying data. It is an object of the present invention to provide a data copying method for a duplex memory, which has the characteristics of being able to perform high-speed detection without providing a complicated detection circuit.

Therefore, the duplex memory data copying method of the present invention includes a central processing unit and a duplex memory,
In an information processing system in which the same data is written to the duplicated memory under normal conditions, when a command instructing the copying of memory data is issued, both of the duplicated memories are not busy and the central After confirming that there is no access request from the processing device, read data from one memory, write the requested data to the other memory, and after writing the data is finished, read the same data from the other memory. It is characterized by the fact that it outputs the data and checks for errors. Before explaining the present invention in detail with reference to the drawings, the present invention will be summarized as follows.

'A' When the duplex memory is operating in data copy mode, it monitors the access requests from the central processing unit and only if there is no access request with the lowest priority is 1.
Online operation is made possible by providing a priority determination circuit that copies only the amount of memory blocks. [ol One memory block of data copying consists of a data word and an error correction code, and one cycle of data copying consists of reading data from the normal system, transferring data from the normal system to the repair system, and transferring data from the normal system to the repair system. It consists of writing data and sending data from the repair system, and detects data errors that occur during the process when the data is sent from the last repair system. 1. Data writes from the central processing unit that occur while the duplex memory is operating in data copy mode are written to both the normal system and the repair system.
Data is read only from the normal system, so that the data on both systems is always up-to-date.

0 When copying of all areas of memory is completed, this is notified to the central processing unit by an interrupt, and if an uncorrectable data error is detected, the copying operation is interrupted and an interrupt is sent to the central processing unit. Notify by.

Next, the present invention will be explained in detail with reference to the drawings.

Figure 2 shows one of the memory controllers used in the present invention.
FIG. 3 is a block diagram of an embodiment of the present invention. FIG. 3 is a diagram explaining the flow of copy data in the present invention. FIG. 4 is a block diagram of an embodiment of a copy control circuit used in the present invention. In FIGS. 2 and 3, 6-0 to 6-n are common bus control circuits, 7 is an error detection/correction circuit 8 is a mode control circuit, and 9 is a mode control circuit.
10 is a priority determination circuit, 10 is a copy control circuit, 11 is a memory control circuit, 12-n is a signal bus, 12-n is a signal bus, and 12-n is a signal bus.
3-0 None/13-n is an access request signal line, 14 is a bus, 15 is None/19 is a signal line, 20 is a bus, 21-
0 and 21 indicate memory buses, respectively.

Note that the same symbols as in Fig. 1 indicate the same items, and
Memory controllers 2-0 and 2-1 have exactly the same configuration. In FIG. 2, each of the common bus control circuits 6-1 to 6-n controls data transfer.

The error detection/correction circuit 7 not only performs error detection/correction but also generates an error correction code. The mode control circuit 15 determines the state of the memory controller, such as whether the memory controller is being accessed by the central processing unit, copying data while being accessed by the central processing unit, being a master, or being a slave. It is something to remember. The priority determination circuit 9 is
It performs a busy check and selects access requests according to priority. The priority determination circuit 9 determines that the memory is not busy and there is no signal line 13-0;
A copy request on signal line 16 or 18 can be selected only if there is no access request on signal line 13-n. The copy control circuit 10 controls data copying, and when the system becomes normal (copy data sending side), it extracts data from memory, sends out read data, etc., and performs restoration system (copy data receiving side). side), it receives data and writes the received data to memory. The copy control circuit 101 will be explained in detail later. In the case of memory write, the memory control circuit 11
It sends out a start signal, address information, and write data, and in the case of memory reading, sends out a read start signal and address information, and receives read data. Next, the data copying process of the present invention will be explained with reference to FIGS. 2 and 3.

Assume now that the memory controller 2-1 is a normal system and the memory controller 2-1 is a repair system.
Note that the normal system means the side that sends the copy data, and the repair system means the side that receives the copy data. When the memory controller 2-0 receives the copy operation request, it reads one memory block from the memory 3-0. This one memory block is composed of data and error correction code, as described above. One memory read from the memory block is transferred to the memory bus 21.
-0, which is sent onto the copy bus 5 via the memory control circuit 11, the bus 20 and the copy control circuit 10. Memo iJ・
In the controller 2-1, data on the copy bus 5 is written into the memory 3-- via the copy control circuit 5, the bus 20, the memory control circuit 11, and the memory bus 21-1. After one memory block has been written into the memory 3-1, the same memory block is read out and error detection and correction is performed by the error detection and correction circuit 7 in the memory controller 2-1. If an uncorrectable error is detected in this step, the data copy mode of the mode control circuit 8 is interrupted by a signal on the signal line 15, and the central processing unit is notified by an interrupt control circuit (not shown).
Furthermore, when copying of all areas of the memory is completed, the central processing unit is similarly notified by an interrupt. FIG. 4 shows details of the copy control circuit 10 and its related parts.

In FIG. 4, 22 is a command register, 23 is a copy address register, 24 is a copy/read instruction circuit, 25 is a copy/write instruction circuit, and 26 is a copy/read instruction circuit.
Data transfer completion notification circuit, 27 is a copy/check/read instruction circuit, 28 is a copy/bus direction determination circuit, 29
36 to 36 are gates, and 37 is a falling detection circuit, respectively. Also, the signals CPYRQ, CPEN, CPA
DD, CPYWTDATA, CPYRDDATA, *C
PYDT, RDST, WTST, MSV○, *CPYS
T, *CPYEND, CPYSTP and COMP are
Each has the following contents. '1' CPY
RQ Copy operation request signal ■ CPEN Signal that permits copy operation [31 CPADD Signal indicating the address to copy [4] CPYWTDATA Copy data written to memory on the spray side (repair system) {5
} CPYRDDATA Copy data t read from memory on the master side (normal system)
6} *CPYDT Data on the copy bus sent from the master side to the slave side '7' RDST Signal that instructs the memory control circuit to perform a read operation '8} Signal side that instructs the WTST memory control circuit to perform a write operation MSVO write operation Signal 00 indicating completion or read validity *CRYST A signal sent from the master side to the slave side, indicating the validity of the copy data (11) CPYEND A signal sent from the slave side to the master side, indicating the validity of the copy data. Signal (12) CPS indicating that writing is complete
TP A signal indicating that one cycle of copying is completed,
Address count up is sent to the copy address register 23, and C is sent to the priority determination circuit 9.
Instructs to reset the PEN signal.

(13) COMP Signal indicating that all addresses have been copied The copy control circuit 10 of FIG. 4 operates as follows.

Prior to data copying, initial values are set in the copy address registers 23 on the master and slave sides. After setting the initial value in the copy address register 23, a copy command is issued to the memory controller on the slave side. Memory on the slave side
The controller uses CPYR in its own priority determination circuit 9.
At the same time, it also sends CPYRQ to the memory controller on the master side. Master side (normal system)
In the copy control circuit 10, the MST signal is turned on. When a CPYRQ is sent from the slave side (restoration system), the master side priority determination circuit 9 confirms that no other access request exists and turns on the CPEN signal. When both the CPEN signal and the MST signal are turned on, the copy'read instruction circuit 24 turns on the RDST signal. When the RDST signal turns on, the memory control circuit 11 starts reading the memory. If the data read from the memory is valid, the MSVO signal is turned on. When both the RDST signal and the MSVO signal are turned on, the *CPYST signal is turned off. Further, the data CPYRDDATA read from the memory is inverted by the copy bus direction determining circuit 28 and sent out as *CPYDT.

As described later, *CPY sent from the slave side
When the END signal turns off, the copy/read instruction circuit 2
4 is reset, and then when the *CPYEND signal is turned on, the CPSTP signal output from the fall detection circuit 37 is turned on. The contents of the copy address register 23 are incremented by 11 by this ON CPSTP signal. In the copy control circuit 10 on the slave side (repair system), MST
The signal is said to be off.

When an OFF *CPYST signal is sent from the master side, the gate 30 outputs an ON signal, which causes the copy
The write instruction circuit 25 turns on the WTST signal. WT
When the ST signal turns on, the memory control circuit 11 writes CPYWTDATA sent from the master side and closed into the memory.

When the writing to the memory is completed, the gate 31 outputs an on signal, which causes the copy data transfer completion notification circuit 26 to output an on signal. This on signal turns off the *CPYEND signal, and at the same time, the copy/check/read instruction circuit 27 is set and the R
The DST signal is turned on. *When the CPYEND signal is turned off, the copy/write instruction circuit 25 is reset. When the RDST signal turns on, the memory control circuit 11
performs memory emptying. When the MSVO signal is sent from the memory, the gate 31 outputs an on signal and resets the copy data transfer completion notification circuit 26. This turns on the *CPYEND signal. *CPYEND
When the signal turns on, the falling detection circuit 37 outputs CPSTP.
Turn on the signal. With this ON CPSTP signal, this read data is checked by the FF detection/correction circuit, and the contents of the copy address register 23 are 113.
Also, the copy/check/read instruction circuit 27 is reset. When the contents of the copy address register 22 reach a predetermined value, the COMP signal is turned on to notify that the copying of all areas in the memory has been completed. As is clear from the above description, according to the present invention, data can be copied without interrupting online operation in an information processing system having a duplex memory, so maintenance after a failure in one system of the duplex memory is possible. The continuity of the entire information processing system is also ensured during recovery.

Additionally, there is no need for a dedicated and complex detection and correction circuit for data errors that occur during the data copying process.
Effects such as being able to reduce the cost of the memory controller and improving reliability can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an overview of an information system with dual memory, Fig. 2 is a block diagram of one embodiment of a memory controller used in the present invention, and Fig. 3 explains the flow of copy data in the present invention. FIG. 4 is a block diagram of one embodiment of a copy control circuit used in the present invention. 110 None, 1-n...Central processing unit, 2-0 and 2-1...Memory controller, 3-0 and 3-1...
...Memory, 4...Common bus, 5...
Copy bus, 6-n, no, 6-n... Common bus control circuit, 7... Error detection/correction circuit, 8.
...Mode control circuit, 9...Priority determination circuit, 10...Copy control circuit, 11...
...Memory control circuit. O diagram O 3 diagram next 2Gq next 4 diagram

Claims (1)

[Claims] 1. In an information processing system that includes a central processing unit and a duplicated memory, and in which the same data is written to the duplicated memory under normal conditions, when a command instructing the copying of data in the memory is issued, After confirming that both of the duplicated memories are not busy and that there is no access request from the central processing unit,
Read data from one memory, write the read data to the other memory, and after writing the data,
A data copying method for a dual memory, characterized in that the same data is read from the other memory and checked for errors.