JPS6017038U - GTO gate circuit - Google Patents

GTO gate circuit

Info

Publication number
JPS6017038U
JPS6017038U JP10751483U JP10751483U JPS6017038U JP S6017038 U JPS6017038 U JP S6017038U JP 10751483 U JP10751483 U JP 10751483U JP 10751483 U JP10751483 U JP 10751483U JP S6017038 U JPS6017038 U JP S6017038U
Authority
JP
Japan
Prior art keywords
gate circuit
gto gate
gto
current
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10751483U
Other languages
Japanese (ja)
Inventor
小林 忠夫
Original Assignee
株式会社明電舎
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社明電舎 filed Critical 株式会社明電舎
Priority to JP10751483U priority Critical patent/JPS6017038U/en
Publication of JPS6017038U publication Critical patent/JPS6017038U/en
Pending legal-status Critical Current

Links

Landscapes

  • Power Conversion In General (AREA)
  • Thyristor Switches And Gates (AREA)
  • Electronic Switches (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はGTO並列接続時のオフゲート電流の流れを説
明するための回路図、第2図はGTOのターンオフ特性
のバラツキによる遮断電流のアンバランス状態を説明す
るための波形図、第3図は従来のゲート回路の一例を示
す回路図、第4図は本考案に係るGTOのゲート回路の
一実施例を示す回路図である。 Ql及びQ2・・・・・・GTO1E□・・・・・・オ
ン電源、E2・・・・・・オフ電源、SWl及びSW2
・・・・・・スイッチ、Z1〜z3・・・・・・インピ
ーダンス、B・・・・・・電流バランサ。
Figure 1 is a circuit diagram to explain the flow of off-gate current when GTOs are connected in parallel, Figure 2 is a waveform diagram to explain the unbalanced state of cut-off current due to variations in GTO turn-off characteristics, and Figure 3 is FIG. 4 is a circuit diagram showing an example of a conventional gate circuit. FIG. 4 is a circuit diagram showing an example of a GTO gate circuit according to the present invention. Ql and Q2...GTO1E□...On power, E2...Off power, SWl and SW2
...Switch, Z1 to Z3... Impedance, B... Current balancer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 並列接続のGTOのオフゲート電流回路にのみ電流バラ
ンサを挿設したことを特徴とするGTOのゲート回路。
A GTO gate circuit characterized in that a current balancer is inserted only in the off-gate current circuit of GTOs connected in parallel.
JP10751483U 1983-07-11 1983-07-11 GTO gate circuit Pending JPS6017038U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10751483U JPS6017038U (en) 1983-07-11 1983-07-11 GTO gate circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10751483U JPS6017038U (en) 1983-07-11 1983-07-11 GTO gate circuit

Publications (1)

Publication Number Publication Date
JPS6017038U true JPS6017038U (en) 1985-02-05

Family

ID=30251189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10751483U Pending JPS6017038U (en) 1983-07-11 1983-07-11 GTO gate circuit

Country Status (1)

Country Link
JP (1) JPS6017038U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6327118A (en) * 1986-07-21 1988-02-04 Hitachi Ltd Semiconductor switch circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6327118A (en) * 1986-07-21 1988-02-04 Hitachi Ltd Semiconductor switch circuit

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