JPS601696A - Rom capable of access from x and y directions - Google Patents

Abstract

PURPOSE:To attain reading of data at the same speed from both X and Y directions by actuating X and Y sense means interlocking X and Y line driving means selected by the address signal and transmitting both high and low logic levels of a memory cell. CONSTITUTION:A memory cell array 1 of (mXn) bits has Q corresponding to each bit. The drain terminal of each Q is connected to a high potential VCC. Then the gate and source terminals are connected to the X and Y lines respectively via a wiring means 11 in response to level ''1'' and the data expected to each bit. While the gate and source terminals are connected to the y and X lines respectively via a wiring means 12 in response to level ''0''. The X and Y lines are reset to ''0'' for each input of the signal impressed to an address decoder and the X and Y selection signals respectively in a readout mode. Then an X line driver 2a and a Y line sense amplifier 3b or a Y line driver 2b and an X line sense amplifier 3a are actuated in response to both X and Y selection signals. Thus each Q output is transmitted through a selection part.

Description

[Detailed description of the invention] lal Technical field of invention The present invention relates to improved access functionality in ROM.

tbl Technical background Information processing systems (Jfd, as is well known, do not require rewriting of information such as code conversion or character pattern generators, etc., and simply respond to access ζ without generating a certain amount of information. This is a heavy machine that can be used repeatedly without damaging the contents of the 6c memory information even if the electric wire is disconnected.

tel Prior Art and Problems With the development of information processing systems, R has been used as a character pattern generator for character processing, especially dot pattern display.
(Demand for JM is increasing.In contrast to outputting data using the conventional dot configuration, display display data using a cathode ray tube (such as a single C) is used in Figure 1F.
In contrast to the final address scan method, which displays all erect characters in the X direction,
Data for dot printing by a serial printer or the like is based on a column address scan method in which one erect character shown in FIG. 1, tbl, is read out in the Y direction. In addition, for dot printing, in order to output character data for vertical writing, for example, in Chinese, Korean, or Japanese candy, when writing normally horizontally, M=]i column is used. It requires a row scan in the direction perpendicular to the scan.
Demata characters were processed using two types of methods: takutorou and column scan.

In order to save storage capacity, if we try to obtain the same data by row scan in one direction as by column scan in the iiq direction by 61toM, the access for each bit is less than 1. Address control is time-consuming, and the time required to control the digit is usually longer than the decimal point due to the bit configuration.

(dl OBJECT OF THE INVENTION The object of the present invention is to provide one IL
(JM has a function that allows access from both row scan and column scan directions, and can read stored data at the same operating speed for access from either direction. One set of 2 ROMs was required for
The purpose is to provide a means for implementing Km functions in one ROM.

tel Structure of the Invention The purpose of this invention is to connect the drain terminal to the high point of the power source by inserting a single bias resistor resistor into the memory cell, which corresponds to high or low surface J buried level for fixed storage. The memory cell array is configured by biasing the means for selectively wiring the gate and source terminals of the clusters to the word line/bit line in the input direction and the word line and bit line in the Y direction, and A means for applying a low level signal to a word line and a bit line, including an X and Y line driving means for driving X′f or Y line, and a corresponding Yi or X by operating the X and Y line driving means. Based on the Y and X-ray sense hand plate that senses the bladder extraction blade of the 4Ii Morisel in conjunction with the drive means, the address decoder section lowers the bell signal mark 11 means each time it is accessed. Both X
After initially setting the YmG world level, the N or X-ray sensing means that is linked to the selected X or Y-ray 1 driving means is activated in response to the address signal, and the crystal is activated by the self-tAt hand 14i that has been set in the memory cell array in advance. x, y characterized in that /low logic level is selected hb.
This can be accomplished by providing a ROM that is more accessible than P10,000.

(fl Embodiments of the Invention An example of the present invention will be explained below with reference to the drawings. Fig. 2 shows an embodiment of the present invention and another embodiment of the present invention.
Figure 3 is a block diagram of the ROM that can be accessed from both directions.
(See Figure 4 for the internal block diagram of JM's memory self-ray.) It (J
An internal block diagram of a memory cell array of M is shown. In the figure, 1 is a memory cell array corresponding to FIG. 3 according to one embodiment of the present invention, la is a memory cell array corresponding to FIG. 4 according to another embodiment, 2a is an x6 dryer, and 2b is a YI
M driver, 3a is a part of the present invention [X+1 sense amplifier corresponding to 11 parts, 3b is Y scarlet sense amplifier,
3c is an Xa sense amplifier corresponding to other embodiments; 4a;
4bIio reset driver, 5 is an address decoder section, 6 is a selection section, 11, 12, 13.14 is a wiring means, X
a.

b...m is the X-direction word line and focus line (X-ray U, Ya, b...11 is the Y-direction word line and bit line (Y line), Q + Q+, Q2 M for Ham memory cell
(JS) transistor QD is a NUS) transistor. In one embodiment of the present invention, an mXn memory cell array 1 is constructed with Qs corresponding to valleys, and all drain terminals of Qs are at a high potential of the supply voltage. .

According to the data expected to be connected to the high logic level 1 (corresponding to the high level), the wiring means 11
The gate terminal is connected to the X-ray, the source terminal is connected to the Y-line, the low logic level is 0 (corresponding to the color level), and the data f terminal is connected to the Y-line and the source terminal is connected to the On the other hand, when creating a new product, the address signal sent to the address coater section 5 and the X, YSS multiplied signal are input every time ζ
After turning on the zero reset drivers 4a and 4b and resetting the X and Y lines to zero, turn on the X-ray driver and f
Either the driver 2a and the Y-line sense amplifier 3b are turned on, or the Y-line driver 2b and the X-ray sense amplifier are enabled.

Note that the XY selection signal may be replaced by the most significant bit of the address signal. For example, when the Xa ray selected by the X-ray driver 2a is driven, the Ya-n line is connected to the wiring means 1.
1, Q outputs the city level, and since there is no output from Q by the wiring means 12, in the example of the X and a lines IIAAkJJ, lO...Ol are detected on Ya-ni, respectively. In the example of Xb edition drive, Ol...lO are detected. The Q outputs from these wiring means 11 and 12i are amplified and shaped via the Y-line sense amplifier 3h, and output from the selection section 6 from the 1^C external terminal. In the case of driving by the Y-ray line η Iha 2b, X a −m
Depending on ll, there is no output on Q, and the wiring means 12ζ detects the disturbance level, so the sign is opposite to that of the X-ray driver 28 & operation, and in the Ya-ray drive column, Ol... ...0 is detected, and the detection output of Q from these wiring means 11 and 124 is suppressed in this way. , the low level by wiring bow and wiping 12 can be read out by similar operating speed 5
It is J-Noh and UM is concerned.

Next, another embodiment will be described with reference to FIG.

In another embodiment, an embodiment of the present invention shown in 11J is such that the X memory cell array 1 shown in FIG. 3 is replaced with the memory cell array 1a shown in FIG. The 9 configurations are different in that the line sense amplifier 3C is used, but everything else is the same.In the memory cell array la, an mXn hit is constructed by using 1 bit as a set of 2 memory cells made up of Ql and Q2. Corresponding to the level, the drains of Q1+Q2 are connected to the high potential VCC of the supply voltage by the care means 13, and corresponding to the low level, the drains of Q1 and Q2 are connected to the ground potential by the wiring means 141. Q1 and Q2 have wiring means 13, and a high level is input to the gate terminal by driving the X-ray driver 2a or Y-line driver 21), so a high level is detected at the source terminal and the Y-n line or Xa- A high level detection signal is applied from the rr+ line to the Y-line sense amplifier 3b or the X-ray sense amplifier 3C, and data is sent out from the output terminal via the selection section 6. In the other embodiment shown in FIG. 4, signals corresponding directly to the selection of high and low levels by the wiring means 13 and 14 are detected on the X a-m, Ya, and n lines, and the X-ray sense amplifier 3C needs to be inverted. Good with no amplification shaping function. Also, depending on the circumstances, wiring method 1
The connection to the ground potential by 4 may be omitted and left floating if there is no problem with noise or the like.

It should be noted that Xa to m,
The setting of Ya-ni to the single-person level shall be carried out in the same manner as in the above-mentioned embodiment. Other embodiments of the present invention are constructed in this way, so that even access in both the X and Y directions allows access to a higher level than the wiring means 131 at the time of manufacturing, and access to 18 levels by the wiring means 14. A ROM with similar operational performance and m'f output is obtained.

tgl As described in detail about the invention, according to the present invention, conventional R (JM access methods could only be row scan or column scan), whereas bladder extraction at normal speed could be performed from both X and Y directions. With EiJ function, we can provide a ROM with the function of reading out the 8 self-memory data set by wiring means at the time of manufacturing at the same operating speed even when accessing from falling down, so the storage capacity is reduced. Measures useful for reduction will be taken.

[Brief explanation of drawings]

Figure 1 tal is a conceptual diagram of a conventional row address scan, Figure 1 tbl is a conceptual diagram of a conventional column address scan, and Figure 2 shows a history of the present invention and other examples. In the example, it is possible to access in both directions (Bronfre 1 and 3 by JMi).
The block diagram of the memorial array in one embodiment of the invention and FIG.
This is the Bronfre 1 of the memory cell array. In the figure, 1, 1.2 are memory cell arrays, 2II is an X1 sense driver, 2b is a Y-ray sensor, 3a, 3cit, X-ray center sense amplifier, 4
Fl, b is an O reset driver, 5 is an address decoke, 6 is a selection section, 11.12, 1:'i, 14 is a white lineman 1 and Q, Q1+Qz. Qn is a 1S transistor. L hood

Claims (1)

[Claims] υ A single 1IllU8) transistor element whose drain terminal is connected to the high potential of the power supply is used as a memory cell, and a sieve or a word line in the X direction corresponding to a low logic level is used as a memory cell. A memory cell array is constructed by selectively wiring the gate and source terminals of direct line f to the word green and bit lines in the X direction, and low level signals t# to the input and word lines/bit lines in the X direction. J)) Drive the middle row of g, inside direct entry or Xa=~
When υ is input, the Y line driving means and the X or Y s driving means operate to detect the output of the memory cell obtained in the corresponding Y or < line. X-ray sensing means 4 'III+ is changed, and the AT1/S decoder section applies a previous level signal every time it is accessed to set a low level to both XY lines, and then outputs the selected X in response to the address signal. or actuating the Y or X-ray sensing means that is linked to the X-ray driving means;
The wiring method applied to Lua 1/A on the memory in advance
)1,0M02) X, accessible from both X and Y directions, characterized by sending a low logic level through a selection section
A pair of +J (J8) transistor elements having a gate terminal connected to the word line/hit pair in the Y direction, a source terminal connected to the word line/hit line in the Y direction, a gate terminal connected to the X line, and a source terminal connected to the X line. is a memory cell, and comprises a step for selectively wiring the drain of the element to the surface potential of the power supply in accordance with a high or low logic level to be fixedly stored, and the word width in the X and Y directions. Means for printing a low level signal on the double bit line, X and Y line driving means for driving the inner direct X or X rays, -I
The IS is equipped with Y and XIpM sensing means for sensing the J nacelle bladder ejecting output in conjunction with the driving means.The address decoder section uses a low level signal marking means each time it is accessed, After setting the level for the i/1 period, the Y or X-ray sensing means that works with the selected X or Y-ray driving means is activated in response to the address signal, and the high/ik optical level is set by the wiring means installed in the memory cell array in advance. A box that can be accessed from both x and 1 directions (JM.