JPS60167318A - Photo applied-semiconductor manufacturing device - Google Patents

Photo applied-semiconductor manufacturing device

Info

Publication number
JPS60167318A
JPS60167318A JP2324984A JP2324984A JPS60167318A JP S60167318 A JPS60167318 A JP S60167318A JP 2324984 A JP2324984 A JP 2324984A JP 2324984 A JP2324984 A JP 2324984A JP S60167318 A JPS60167318 A JP S60167318A
Authority
JP
Japan
Prior art keywords
reaction
reaction chamber
processed
wafer
entrance window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2324984A
Other languages
Japanese (ja)
Inventor
Akira Shigetomi
重富 晃
Makoto Hirayama
誠 平山
Nobuyuki Yoshioka
信行 吉岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2324984A priority Critical patent/JPS60167318A/en
Publication of JPS60167318A publication Critical patent/JPS60167318A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To contrive to enhance work efficiency of a photo applied semiconductor manufacturing device by a method wherein at least two reaction chambers are provided in a reaction cell, the above-mentioned both reaction chambers are used alternately, and the light incident window of the reaction chamber not being used is purified. CONSTITUTION:The inside of a reaction cell main body 6 is separated into a first reaction chamber 11a and a second reaction chamber 11b according to a sluice valve 10. A wafer 3 to be processed is accommodated in the first reaction chamber 11a at first, and silicon is deposited on the wafer 3 to be processed according to a photo CVD reaction. Si is deposited also on a light incident window 7a for the degree of about 10min to reduce optical permeability, and when the reaction becomes hard to be generated, the sluice valve 10 is opened, and after the wafer 3 to be processed is transferred into the second reaction chamber 11b, deposition of Si onto the wafer 3 to be processed is continued similarly to the case at the first reaction chamber 11a. Then supply of SiH4 gas to the first reaction chamber 11a is stopped, carbon tetrafluoride gas is introduced, a high-frequency voltage is applied between electrodes 12a to generate plasma, and Si deposited to be adhered to the light incident window 7a is removed according to plasma etching.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、光応用半導体製造装置の改良に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in optical semiconductor manufacturing equipment.

〔従来技術〕[Prior art]

以下、レーザ光や紫外線などの光のエネルギーを用いる
光応用(3VD (Ohemica’l Vapour
 Deposition:化学的気相堆積)装置を例に
とって説明を行うつOVDは半導体集積回路装置を製造
する際、MOI3素子の多結晶シリコン層2層間絶縁膜
、ノ<シペ−ジョン膜の堆積などに用いられる重要な技
術である。そして、従来、 OVDは主として反応ガス
を加熱して化学反応を起こさせていたが、半導体素子の
微細化に伴う接合の浅薄化(shallow junc
tion化)、またはその動作の高速化のだめの不純物
プロファイルの急峻化、更には、多層配線の使用やプロ
セス誘起欠陥の防止に伴うプロセス順序の制約除去の要
請などのために、低温プロセス化が望まれている。この
流れに沿う技術として、現在、プラズマOVD技術が実
用化されている。そして、最近、低温OVDのエネルギ
ー源として、レーザ光や紫外線などの光のエネルギーを
用いる方法が注目され、この方式を用いて光応用OVD
装置の試作が行われている。
Below, we will discuss optical applications (3VD) that use light energy such as laser light and ultraviolet light.
The explanation will be given using chemical vapor deposition (CVD) equipment as an example. When manufacturing semiconductor integrated circuit devices, OVD is used for depositing an insulating film between two polycrystalline silicon layers of three MOI elements, and a non-sipation film. It is an important technique used. Conventionally, OVD mainly heated a reactive gas to cause a chemical reaction, but with the miniaturization of semiconductor devices, shallow junctions have become thinner.
low-temperature processing is desired due to the need for steeper impurity profiles to speed up operation, as well as the need to remove constraints on process order due to the use of multilayer interconnects and the prevention of process-induced defects. It is rare. Plasma OVD technology is currently being put into practical use as a technology that follows this trend. Recently, a method that uses light energy such as laser light or ultraviolet rays as an energy source for low-temperature OVD has attracted attention, and this method can be used to perform optical-applied OVD.
A prototype of the device is being manufactured.

第1図および第2図はそれぞれ従来の反応管形および反
応セル形の光応用CVD装置を示す模式的断面図である
。第1図および第2図において、(1)は紫外(UV)
線を放射する化学反応用ランプ、(2)は光を透過する
材料で作られた反応管、(3)は被加工ウエーハ、(4
)は被加工ウェーハ(3)が載置されるサセプタ、(5
)はウェー71補助加熱用赤外(工R)線ランプ、(6
)は反応セル本体、(7)は光透過材からなる光入射窓
、(8)は反応ガス導入口、(9)は反応ガス排出口で
ある。反応ガスは反応ガス導入口(8)から矢印工のよ
うに導入され、反応ガス排出口(9)から矢印0のよう
に排出される。
FIGS. 1 and 2 are schematic cross-sectional views showing conventional reaction tube type and reaction cell type optical CVD apparatuses, respectively. In Figures 1 and 2, (1) is ultraviolet (UV)
(2) is a reaction tube made of a material that transmits light; (3) is a wafer to be processed; (4) is a chemical reaction lamp that emits radiation;
) is a susceptor on which the wafer to be processed (3) is placed, (5
) is 71 auxiliary heating infrared lamp, (6
) is the reaction cell body, (7) is a light entrance window made of a light-transmitting material, (8) is a reactive gas inlet, and (9) is a reactive gas outlet. The reaction gas is introduced from the reaction gas inlet (8) as shown by the arrow, and is discharged from the reaction gas outlet (9) as shown by the arrow 0.

しかしながら、上述のような従来の装置では。However, in conventional devices such as those mentioned above.

反応によって生成した固形物が、反応管(2)の管壁。The solid matter produced by the reaction coats the wall of the reaction tube (2).

反応セルの光入射窓(7)に付着して、光の透過を妨げ
、反応が進行しにくくなってウェーッーへの堆積膜厚が
時間とともに飽和したり、運転毎の堆積条件や製品ウェ
ーハの再現性が損なわれることがある。
It adheres to the light entrance window (7) of the reaction cell, blocking the transmission of light, making it difficult for the reaction to proceed, and causing the thickness of the deposited film on the wafer to become saturated over time, as well as the deposition conditions for each operation and the reproduction of product wafers. Sexuality may be impaired.

〔発明の概要〕[Summary of the invention]

この発明は以上のような点に鑑みてなされたもので、反
応セル内に少なくとも2つの反応室を設け、各反応室の
光入射窓に付着した反応生成固形物を容易に除去できる
ようにするとともに上記両反応室を交互に使用し、使用
していない方の反応室の光入射窓を清浄化することによ
って作業効率のよい光応用半導体製造装置を提供するも
のである。
This invention has been made in view of the above points, and provides at least two reaction chambers in a reaction cell so that reaction product solids adhering to the light entrance window of each reaction chamber can be easily removed. In addition, by alternately using both of the reaction chambers and cleaning the light entrance window of the reaction chamber that is not in use, an optical semiconductor manufacturing apparatus is provided which is highly efficient in operation.

〔発明の実施例〕[Embodiments of the invention]

第3図はこの発明の一実施例の構成を示す模式的断面図
で、反応セル本体(6)の内部は仕切弁QOによって第
1の反応室(lla)と第2の反応室(xlb)とに分
離され、第1の反応室(lla)には光入射窓(7a)
1反応ガス導入口(8a)、反応ガス排出口(9a)が
設けられ、第2の反応室(1xb)には光入射窓(′7
b)。
FIG. 3 is a schematic sectional view showing the configuration of an embodiment of the present invention, in which the interior of the reaction cell body (6) is divided into a first reaction chamber (lla) and a second reaction chamber (xlb) by a gate valve QO. The first reaction chamber (lla) has a light entrance window (7a).
A reaction gas inlet (8a) and a reaction gas outlet (9a) are provided in the second reaction chamber (1xb).
b).

反応ガス導入口(sb)、反応ガス排出口(9a)が設
けられており、各反応室の動作は第2図の従来例と同一
である。、 (12a)および(12b)はそれぞれ第
1の反応室(lla)および第2の反応室(lxb )
内に設けられプラズマを発生させるだめの電極であるつ
まず、被加工ウェーハ(3)を第1の反応室(lla)
に収容し、反応ガス導入口(8a)からモノシラン(S
ta4)ガスを導入し、光入射窓(7a)を通して破線
矢印UVで示すように紫外光を照射し、被加工ウェーハ
(3)の上にシリコン(Sl)を堆積させる。約lO分
間徨度で光入射窓(7a)にもSlが堆積し光透過度が
低下し、反応が起9にくくなると、仕切弁ui開いて被
加工ウェーハ(3)を第2の反応室(11b)へ移し、
仕切弁Q0を閉じた後、第1の反応室(lla)におけ
ると同様にして、被加工ウェーッ・(3)上へのSiの
堆積をつづける。そして、この時、第1の反応室(ll
a)への81に14ガスの供給を止め、四フッ化炭素(
CF4)ガスを導入し、電極(12a)間に高周波電圧
を印加してプラズマを発生させ光入射窓C′7a)に堆
積付着したSiをプラズマエツチングによって除去する
。この除去は約10秒で完了する0次に、第2の反応室
(11b)内での反応速度が低下すれば、上述と同じ要
領で被加工ウェーッ・(3)を第1の反応室(lla 
)へ移して、Slの堆積を継続させ、第2の反応室(1
1b)の光入射窓(′7b)に堆積付着したSlを除去
する。以降これを繰返して所望の膜厚になるまで被加工
ウェーハ(3)にSiを堆積させる0このようにして、
常時7に浄な光入射窓を通して光を照射して、はぼ連続
的に効率的なSlの堆積が可能でおる。
A reaction gas inlet (sb) and a reaction gas outlet (9a) are provided, and the operation of each reaction chamber is the same as in the conventional example shown in FIG. , (12a) and (12b) are the first reaction chamber (lla) and the second reaction chamber (lxb), respectively.
The wafer (3) to be processed is moved into the first reaction chamber (lla) through a stump, which is an electrode for generating plasma.
monosilane (S) from the reaction gas inlet (8a).
ta4) Gas is introduced, and ultraviolet light is irradiated through the light incidence window (7a) as indicated by the dashed arrow UV to deposit silicon (Sl) on the wafer to be processed (3). Sl is also deposited on the light entrance window (7a) for about 10 minutes, reducing the light transmittance and making it difficult for a reaction to occur.Then, the gate valve ui is opened and the wafer to be processed (3) is transferred to the second reaction chamber ( 11b),
After closing the gate valve Q0, the deposition of Si on the workpiece wafer (3) is continued in the same manner as in the first reaction chamber (lla). At this time, the first reaction chamber (ll
Stop the supply of 14 gas at 81 to a), and add carbon tetrafluoride (
CF4) gas is introduced, a high frequency voltage is applied between the electrodes (12a) to generate plasma, and the Si deposited on the light incident window C'7a) is removed by plasma etching. This removal is completed in about 10 seconds.Next, if the reaction rate in the second reaction chamber (11b) decreases, the workpiece wafer (3) is transferred to the first reaction chamber (11b) in the same manner as described above. lla
) to continue the deposition of Sl, and then transferred to the second reaction chamber (1
The Sl deposited on the light entrance window ('7b) of 1b) is removed. Thereafter, this process is repeated to deposit Si on the wafer to be processed (3) until the desired film thickness is reached.In this way,
By constantly irradiating light through a clean light entrance window, it is possible to deposit Sl almost continuously and efficiently.

上側では81の気相堆積の場合を説明したが、他の物質
、例えば窒化シリコン(5L3N4 ) * 二酸化シ
リコン(S10□)などであってもよく、また、光応用
OVD装置のみならず、光を応用した気相エツチング装
置、気相ドーピング装置など、光応用半導体装置一般に
この発明は適用できる。更に反応室相互間のウェーハの
移動は自動化することができる。
In the upper part, the case of vapor phase deposition of 81 was explained, but other materials such as silicon nitride (5L3N4) * silicon dioxide (S10□) may also be used. The present invention can be applied to optical semiconductor devices in general, such as vapor phase etching devices and vapor phase doping devices. Furthermore, the movement of wafers between reaction chambers can be automated.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明になる光応用半導体製造
装置では反応セルをいずれも光入射窓とこの光入射窓の
内面の清浄化手段とを有する複数個の反応室に分割し、
第1の反応室で被加工半導体ウェーハに光応用気相化学
反応を施し、光入射窓の光透過度が低下すれば、被加工
半導体ウェーハを第2の反応室に移して光応用気相化学
反応を引続き施すとともに、上記第1の反応室では光入
射窓の内面を清浄化できるようにしたので、極めて効率
のよい操作が可能である。
As explained above, in the optical semiconductor manufacturing apparatus according to the present invention, the reaction cell is divided into a plurality of reaction chambers each having a light entrance window and a means for cleaning the inner surface of the light entrance window,
A semiconductor wafer to be processed is subjected to an optical vapor phase chemical reaction in the first reaction chamber, and when the light transmittance of the light entrance window decreases, the semiconductor wafer to be processed is transferred to a second reaction chamber and subjected to an optical vapor phase chemical reaction. Since the inner surface of the light entrance window in the first reaction chamber can be cleaned while the reaction continues, extremely efficient operation is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はそれぞれ従来の反応管形および反
応セル形の光応用OVD装置の構成を示す模式的断面図
、第3図はこの発明の一実施例の構成を示す模式的断面
図である。 図において、(3)は被加工半導体ウェーハ、(6)は
反応セル本体、(7a)、(7b)は光入射窓、00は
仕切弁、(lla)、(llb)は反応室、 (12a
)、(12b)はプラズマ発生用電極である。 なお、図中同一符号は同一または相当部分を示す。 代理人 大岩増雄 第1図 第2図 第3図 手続補正書(自発)、 1、事件の表示 特願昭59−023249号2、発明
の名称 光応用半導体製造装置3、補正をする者 事件との関係 特許出願人 代表者片山仁へ部 4、代理人 4、補正の対象 明細書の発明の詳細な説明の欄 5、補正の内箸 明細書をつぎのとおり訂正する。
1 and 2 are schematic sectional views showing the configuration of conventional reaction tube type and reaction cell type optical OVD devices, respectively, and FIG. 3 is a schematic sectional view showing the configuration of an embodiment of the present invention. It is. In the figure, (3) is the semiconductor wafer to be processed, (6) is the reaction cell body, (7a) and (7b) are the light entrance windows, 00 is the gate valve, (lla) and (llb) are the reaction chambers, (12a)
) and (12b) are electrodes for plasma generation. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 Procedural amendment (voluntary) 1. Indication of the case Japanese Patent Application No. 59-023249 2. Title of the invention Optical semiconductor manufacturing equipment 3. Case of the person making the amendment To Hitoshi Katayama, Representative of the Patent Applicant, Section 4, Agent 4, Column 5 of Detailed Description of the Invention of the Specification Subject to Amendment, and the amended Chopstick Specification are amended as follows.

Claims (4)

【特許請求の範囲】[Claims] (1)透明体によって覆われた光入射窓を有し、この光
入射窓を通して外部から入射される光のエネルギーを利
用して内部で被加工半導体ウェーッ・に気相化学反応を
施すようにした反応セルを備えたものにおいて、上記反
応セルをいずれも光入射窓と、この光入射窓の内面の清
浄化手段とを有する複数個の反応室に分割し、これらの
反応室の内の第1の反応室において上記被加工半導体ウ
ェーハに上記気相化学反応を施し、上記第1の反応室の
光入射窓に反応生成物が耐着して光透過度が低下すれば
、上記被加工半導体ウェー71を第2の反応室に移して
上記気相化学反応を引続いて施すとともに上記第1の反
応室では上記清浄化手段で当該反応室の光入射窓の内面
を清浄化できるようにしたことを特徴とする光応用半導
体製造装置。
(1) It has a light entrance window covered with a transparent material, and uses the energy of light incident from outside through this light entrance window to perform a gas phase chemical reaction on the semiconductor wafer to be processed inside. In a device equipped with a reaction cell, the reaction cell is divided into a plurality of reaction chambers each having a light entrance window and means for cleaning the inner surface of the light entrance window, and the first of these reaction chambers is When the semiconductor wafer to be processed is subjected to the vapor phase chemical reaction in the reaction chamber of 71 is transferred to a second reaction chamber to continue the gas phase chemical reaction, and in the first reaction chamber, the inner surface of the light entrance window of the reaction chamber can be cleaned by the cleaning means. Optical semiconductor manufacturing equipment characterized by:
(2) 光入射窓の内面の清浄化手段として当該反応室
内でガスプラズマを発生させる装置を備えたことを特徴
とする特許請求の範囲第1項記載の光応用半導体装置。
(2) The optical semiconductor device according to claim 1, further comprising a device for generating gas plasma within the reaction chamber as means for cleaning the inner surface of the light entrance window.
(3)反応室相互間の被加工半導体ウェーッ・の移動を
自動化したことを特徴とする特許請求の範囲第1項また
は第2項記載の光応用半導体製造装置。
(3) The optical semiconductor manufacturing apparatus according to claim 1 or 2, characterized in that the movement of the semiconductor wafer to be processed between reaction chambers is automated.
(4)光のエネルギーを利用した気相化学反応が光応用
化学的気相堆積反応であることを特徴とする特許請求の
範囲第1項ないし第3項のいずれかに記載の光応用半導
体製造装置。
(4) Optical semiconductor manufacturing according to any one of claims 1 to 3, characterized in that the vapor phase chemical reaction using light energy is a photo-applied chemical vapor deposition reaction. Device.
JP2324984A 1984-02-09 1984-02-09 Photo applied-semiconductor manufacturing device Pending JPS60167318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2324984A JPS60167318A (en) 1984-02-09 1984-02-09 Photo applied-semiconductor manufacturing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2324984A JPS60167318A (en) 1984-02-09 1984-02-09 Photo applied-semiconductor manufacturing device

Publications (1)

Publication Number Publication Date
JPS60167318A true JPS60167318A (en) 1985-08-30

Family

ID=12105321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2324984A Pending JPS60167318A (en) 1984-02-09 1984-02-09 Photo applied-semiconductor manufacturing device

Country Status (1)

Country Link
JP (1) JPS60167318A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6320429U (en) * 1986-07-24 1988-02-10
US5427824A (en) * 1986-09-09 1995-06-27 Semiconductor Energy Laboratory Co., Ltd. CVD apparatus
US5976259A (en) * 1985-02-14 1999-11-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method, and system
US6013338A (en) * 1986-09-09 2000-01-11 Semiconductor Energy Laboratory Co., Ltd. CVD apparatus

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976259A (en) * 1985-02-14 1999-11-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method, and system
US6113701A (en) * 1985-02-14 2000-09-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method, and system
JPS6320429U (en) * 1986-07-24 1988-02-10
US5427824A (en) * 1986-09-09 1995-06-27 Semiconductor Energy Laboratory Co., Ltd. CVD apparatus
US5629245A (en) * 1986-09-09 1997-05-13 Semiconductor Energy Laboratory Co., Ltd. Method for forming a multi-layer planarization structure
US5855970A (en) * 1986-09-09 1999-01-05 Semiconductor Energy Laboratory Co., Ltd. Method of forming a film on a substrate
US6013338A (en) * 1986-09-09 2000-01-11 Semiconductor Energy Laboratory Co., Ltd. CVD apparatus

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