JPS60167213A - Ac switch circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an AC switch circuit interposed between an AC power source and a load to prevent arcing between contacts that open and close.

BACKGROUND ART Conventionally, relay switches and the like have been used to turn on/off the connection between a load and a power source.

In order to minimize arcing between the contacts during on/off operation of the relay switch, the following steps were taken. Using a transformer that detects the voltage applied to the load from the power supply, a current transformer that detects the current, etc., each output of the transformer and current transformer and the input signal that generates the drive signal that drives the relay switch are used. The relay switch was controlled to operate without arcing by matching with the relay switch. Such transformers, current transformers, etc. are expensive and the overall size of the circuit increases. Furthermore, the number of components of the phase detection circuit including the transformer and the current transformer increases, and the cost of the entire circuit increases.

Purpose The purpose of the present invention is to solve the above-mentioned technical problems, and to provide an AC switch circuit that can operate a relay switch that opens and closes the connection between a load and an AC power source without arcing, and can realize low cost. That's true.

Embodiment FIG. 1 is an electrical circuit diagram for explaining the basic operation of an embodiment of the present invention. When supplying AC power to the load (from EO), connect relay switch a1 to diode D
When the diode D is cut off, the relay switch a2 is turned on, and then the relay switch a2 is turned on when the diode D is conductive. Conversely, when cutting off the power from the AC power supply EO that is being supplied to the load,
The relay switch a2 is turned off when the diode D is conductive, and then the relay switch al is turned off when the diode D is turned off.

FIG. 2 is a block diagram showing the overall electrical configuration 5 of one embodiment of the present invention. Relay control circuit Y is current transformer CT
It receives the output of the transformer PT and the output of the transformer PT, detects the phase of the power given to the load from the load power source EO, and turns on/off the relay switches al and a2. In other words, the relay switches al and a2 are turned on/off at the operating timing as explained in FIG. 1 above. In addition, the relay control circuit Y can control the relay switches al and a2 even if the input signals of the relays that drive the relay switches al and a2 disappear during operation or when an input signal higher than the maximum operating frequency is applied. , a2 are driven to a preset state.

FIG. 3 is an electrical circuit diagram of one embodiment of the present invention. Fourth
The operation when the power of the load p is turned off will be described with reference to the timing chart shown in the figure. The output of the coil L2 of the transformer T is in opposite phase to the voltage vO of the AC power source EO shown in FIG. Comparator 1 discriminates the level of the output of coil L2 of transformer T whose waveform has been shaped into a rectangular wave, and the output of comparator 1 is applied to AND gate 2 and NOTOR.
It is applied to a circuit that generates a pulse at the rising edge of a rectangular wave formed by gate 6. The output of AND gate 2 is shown in Figure 4 (3
) is the pulse p3 shown in FIG. This pulse is shown in Figure 4 (1
) is synchronized with point 07 where the phase of the voltage of AC power source EO changes from positive to negative.

Hereinafter, the pulse shown in FIG. 4(3) will be referred to as a second detection pulse. Here, for example, when the input signal p4 shown in FIG. 4 (4) applied to the terminal Sl goes from high level to low level, the input signal p4 undergoes noise cutting and bounce canceling processing, and then the second detection After the input signal p4 changes due to matching with the pulse, the first second detection pulse p5 shown in FIG. 4(5) is output. This second detection pulse p5 is sent out from the OR gate 14. In addition, the noise cut and bounce cancel are performed by AND game.
)5, an OR gate 6 and a time limit circuit TM3. The delay circuit DYI is operated by the second detection pulse p5 and sends out a pulse p6 delayed by a time t1 from the second detection pulse p5 as shown in FIG. 4(6). The delay circuit DY2 receives the pulse p6 from the delay circuit DYI via the AND gate 16, and outputs the pulse p6 shown in FIG. 4(7).
Sends 7. Pulse p7 is longer than pulse p6 at time t2.
However, it was delayed. That is, the second detection pulse p5 is delayed by the time t1+'t2. This delay time tl+t2 is a value set in consideration of the time of the relay-off drive signal that turns off the relay switch a2 when the diode D is in a conductive state.

The second detection pulse p7 delayed by time tl+t2 is
The time limit circuit TMI is operated, and the fourth
A signal p8 as shown in FIG. 8 is sent out. This signal p
The pulse width Wt of 8 is αη of relay switch a2 in FIG.
This is the time setting from when the off drive signal p17 shown in Figure 4 is generated until when the off drive signal p18 shown in Figure 4 tS is generated for the relay switch a1 so that the relay switch a1 is turned off when the diode D is in the cutoff state. . Time limit circuit T
The output of M1 is the NOTOR gate 14 and NOR gate 3.
The signal is applied to the time limit circuit TM2 via a circuit that generates a pulse at the falling edge of a rectangular wave consisting of 7.

The time limit circuit TM2 sends out a signal p9 having a pulse width W2 as shown in FIG. 4(9). This pulse width W2 is a time set to flow current through the relay coil only during the relay operating time. Normally, the relay operating time when on is longer than the relay operating time when off, so the pulse width W2 is the time when the relay is on. Set longer than the relay operating time. Each output of time limit circuits TMI and TM2 is applied to OR gate 38.

The OR gate 38 outputs a signal plO shown in the fourth position. The AND gate 41 performs 1 noise cut and bounce cancellation on the input signal p4, and inverts the input signal p4.
OTOR gate 14 signal and RS flip-flop 32
The OFF drive signal p17 shown in FIG. 4, a7), which turns off the relay switch a2, is output.

The RS flip-flop 32 sends out a signal p20 shown in FIG. This signal P20 is the input signal p4
goes from a high level to a low level, it goes from a low level to a high level. A signal p5 shown in FIG. 4(5) from the OR gate 14 is applied to the trigger terminal T of the D flip-flop 33a via the OR gate 20. D
The input terminal of the flip-flop 33a is connected to the output of the RSS flip-flop 3, a time limit circuit TMI, and a time limit circuit T.
Since the AND output with the OR output with M2 is given, the output signal p14 of the D flip-flop 33a is at a low level as shown in FIG. 4I.

Further, the trigger terminal T of the D flip-flop 33a has an R
The output from the output terminal Q of the S flip-flop 32 and the O of the OR gate 38 of the time limit circuit TMl and time limit circuit TM2.
AND gate 19 of the R output and the second detection pulse
An output is provided via an OR gate 20. After the level of the input signal p4 changes, the second detection pulse is successively applied to the trigger terminal T of the D flip frog 33a as shown in FIG. Since the signal applied to the input terminal Q is at a high level, the output terminal Q of the D flip-flop 33a
The signal p14 from the output terminal also becomes high level as shown in FIG. 4 (0).

The output from the output terminal Q of the D flip-flop 33a is
The signal is applied to the trigger terminal T of the D flip-flop 33b through a circuit that generates a pulse at the falling edge of a rectangular wave consisting of a NOTOR gate 14 and a NOR gate 23. NO
From the R gate 23, the pulse I shown in FIG. 4 (151)
15 is sent out. The D flip-flop 33a and the D flip-flop 33b have a counter configuration.
The output of the flip-flop 33b is the D flip-flop 3.
It becomes a 1/2 frequency divided waveform of the output of 3a. The output from the output terminal Q of the D flip-flop 33b is passed through a circuit that generates a pulse at the falling edge of a rectangular wave consisting of a NOTOR gate 14 and a NOR gate 35, and an OR gate 31.
It is applied to the reset terminal R of the R87 lip-flop 32. A signal p16 shown in the fourth position is sent out from the output terminal Q of the D free lag flop 33b.

FIG. 5 (pulse p1 from AND gate 19 shown in IQ)
3 is applied to the time limit circuit TM4, and the time limit circuit TM4 sends out a signal p24 having a pulse width W4 shown in FIG. This pulse width W4 is provided to detect whether the switching states of the relay switch a1 shown in FIG. 4 @ and the relay switch a2 shown in FIG. 174 of vO
less than the period. In other words, when the switching states of the relay switches al and a2 change to de-energize the load, the output of the coil L2 of the transformer T changes from the AC power supply K.
The phase of the voltage vO of O changes from anti-phase to in-phase. Therefore, only when the power is turned off, after the second detection pulse is generated,
During 1/2 period of AC power supply EO, the output of comparator 1 is at a low level. The output of the time limit circuit TM4 is the NOTOR gate 14 and N.

The inverted output of the comparator 1 output and 57)
ND is taken by AND gate 3o. A pulse p25 shown in FIG. 4(c) is sent from the NOR gate 25.

AND Goo) From 30, the pulse p2 shown in the 4th turn)
6 is sent. A pulse p26 is applied to the reset terminal R of the RS flip-flop 32 via the OR gate 31, and the RS flip-flop 32 is reset. FIG. 4 shows a state in which the RS flip-flop 32 is reset after the operations of the relay switches al and a'2 are completed. The OFF drive signal p18 of the relay switch a1 shown in FIG. 408 is obtained by ANDing the signal p2o from the output terminal Q of the RS flip-flop 32, the signal p9 from the time limit circuit TM2, and the inverted signal of the input signal p4. A
It is sent out from the ND gate 43. This off drive signal 1)
18, the relay switch a1 is turned off when the diode D is in the cutoff state.・ In the above manner, relay switch a2 is connected to diode D.
When the diode D is in the conductive state, the relay switch al is turned off, and then the relay switch al is turned off when the diode D is in the cutoff state, thereby dissipating the power in the load.

Hereinafter, with reference to the timing chart shown in FIG. 5, the operation when power is applied to a load will be described. relay switch a
When l and a2 are off, coil L2 of transformer T
As shown in FIG. 5(2), the output A of is in phase with the voltage vO of the AC type 4EO in FIG. 5(1). Coil L of transformer T? The output A of is passed through comparator 1 to AND gate 2
and NOT gate 3, which generates a pulse at the rising edge of a rectangular wave. The AND gate 2 sends out a signal synchronized with point 07 at which the phase of the voltage Vo of the AC power source EO changes from negative to positive, as shown in FIG. 5(3). Hereinafter, the signal shown in FIG. 5(3) will be referred to as the first detection pulse. When the input signal p4 shown in FIG. 5 (4) applied to the terminal Si changes from low level to no-y level, the OR output of the input signal p4, the first detection pulse of FIG. 5 (3), and time limit circuits TMI and TM2 The first detection pulse B5 shown in FIG. The first detection pulse B5 in FIG. 5 (5) is generated by the delay circuit DYI.
The delay circuit DYI outputs the signal B6 shown in FIG. 5(6). In the delay circuit DYI, in order to generate an on drive signal for the relay switch a1 so that the relay switch a1 is turned on when the diode D is cut off, the timing adjustment time t1, which takes into account the ON operation time of the relay, is used as shown in FIG. ) is delayed. The time limit circuits TMI and TM2 operate in the same manner as when the power is turned off, and generate pulses having pulse widths W1 and W2. The time limit circuit TM1 sends out the signal B8 shown in FIG. 5(8), and the time limit circuit TM2 sends out the signal B8 shown in FIG.
) is sent out. The OR gate 38 ORs the outputs of the time limit circuit TMI and the time limit circuit TM2, and sends out the signal BIO shown in FIG. 5 121. AND gate 42 connects this signal BIO and RS flip-flop 3.
The output of 2 and the input signal p4 are ANDed and the result shown in Fig. 5 (2
Sends out the on-drive signal B20 for the relay switch a1 shown in [].

An ON drive signal for relay switch a1 is obtained from AND gate 40 by ANDing the OR output of time limit circuits T1 and T2, the output of RS flip-flop 32, and the first detection pulse. ON drive signal B of this relay switch a1
21 is shown in FIG. 5 (121).

The D flip-flop 33a and the time limit circuit TM4 are operated by ANDing the OR output of the time limit circuits TMI and TM2, the output of the RS flip-flop 32, and the first detection pulse. The time limit circuit TM4 detects a change in the switching state of the relay switches al and a2, and sends out a signal B17 having a pulse width W4 as shown in FIG. 5 Uη. The output of the time limit circuit TM'4 is the NOTOR gate 31 and NOR
The signal is applied to a circuit that generates a pulse at the falling edge of a rectangular wave formed by a gate 25. From NOR gate 25, Figure 5 (
Pulse B18 shown above is sent out, and that pulse B18 is applied to AND gate 30. The AND gate 30 ANDs the pulse B18 and the inverted signal from the NOT gate 4 from the comparator 1, and sends the signal B19 shown in FIG. Give to R. As a result, the RS flip-flop 32 is reset and sends out the signal B16 shown in FIG. 5 (06). The RS flip-flop 32 is set when the input signal p4 changes from a low level to a high level, and is reset after the relay switches a1 and a2 are operated, as shown in FIG. 5(2) and FIG. In addition, the time limit circuits TMl and TM2 for generating relay drive signals are
It operates only by the first detection pulse generated when the output B16 of the RS flip-flop 32 is at a high level.

Therefore, time limit circuits TMI and TM2 do not operate after relay switches al and a2 are turned on.

The timing chart shown in FIG. 6 will be explained below. The waveform diagrams in FIG. 6 (11 to 6) are the signal waveforms from the output terminals of each circuit shown in FIG.
1) to 1.20+ in FIG. In the timing chart of FIG. 6, the timing chart of FIG.
Descriptions that overlap with the explanations in the figures will be omitted.

The circuit configuration of the present embodiment is as shown in FIG. 6 υD by matching the second detection pulse with the input signal p4 only while the output signal p20 shown in FIG. 6 (A) of the RS flip-flop 32 is at a high level. Drive signal pH of relay switch a1 and drive signal p1 of relay switch a2 shown in the sixth drawing
2. Therefore, when the RS flip-flop 32 is reset, the relay drive signals p11 and p12 are no longer generated. The timing at which the RS flip-flop 32 is reset is after the level of the input signal p4 changes, after the first second detection pulse shown in FIG. After 4 cycles of voltage vO. This four-cycle counting operation is performed by D flip-flops 33a and 33b. From the D flip-flop 33a, as shown in FIG.
A signal PI4 shown at 141 is sent out, and a signal p16 shown in FIG. 6 (161) is sent out from the D flip-flop 33b. It is reset when the operation is completed or when the cycle of the preset voltage VO is completed as shown in FIG. 6 u61, whichever comes first.Relay switches a1, a2
is set to on, relay switch al
, a2 is set on from terminal Si (4).
Even if the input signal p4 shown in FIG. On-drive signal p11 of relay switch a1 shown in Fig. 0, and AN
Relay switch a shown in Fig. 6 α from D gate 40
The second ON drive signal p12 is not generated.

Through such an operation, relay switch a1 and relay switch a2 are turned on, and AC power source EO is supplied to the load.

Figure 7 shows the output terminals SMN, SMF, S in Figure 3.
FIG. 2 is an electrical circuit diagram of a relay drive circuit connected to SN and S8F, respectively. Line l! 50 is supplied with a power supply voltage Vcc. Line l! 50 is connected to the base of the transistor Tr51 via a resistor R51 and a resistor R52, to the collector of the transistor Tr51 via a resistor R53, and to the transistor Tr5 via a resistor R53 and a resistor R54.
The base of the transistor Tr52 is connected to the base of the transistor Tr52, and the emitter of the transistor Tr52. Line I again! A resistor R59 is connected to the emitter of the transistor Tr54, to the base of the transistor Tr54 via a resistor R57 and a resistor R56, to the collector of the transistor Tr56 via a resistor R57.
and the base of the transistor Tr56 via the resistor R58, the cathode of the ener diode D51, one end of the relay coil A2, and the collector of the transistor Tr53. The collector of transistor Tr54 is connected to the cathode of Zener diode D52, the other end of relay coil A2, and the collector of transistor Tr55. The anode of Zener diode 051 is
Connected to the anode of Zener diode D52. Transistor Tr51°Tr53. Tr55. Each emitter of Tr56 is grounded. The terminal SMN is connected to the pace of the transistor Tr51 via a resistor R52, and to the pace of the transistor Tr55 via a resistor R57. The terminal SMF is connected to the pace of a transistor Tr53 via a resistor R55, and to the pace of a transistor Tr56 via a resistor R58.

A power supply voltage Vcc is applied to line J'60.

Line I! 60 is connected to the pace of the transistor Tr61 through the resistor 61 and the resistor R62, to the collector of the transistor Tr61 through the resistor R63, to the pace of the transistor Tr62 through the resistor R63 and the resistor R64,
Each is connected to the emitter of the transistor Tr62. Line I again! 60 is connected to the emitter of the transistor Tr64, to the pace of the transistor Tr64 via a resistor R67 and a resistor R66, to the collector of the transistor Tr66 via a resistor R67, to a resistor R69 and a resistor R6.
8 and connected to the pace of the transistor Tr66, respectively. The collector of the transistor Tr62 is connected to the cathode of the Zener diode D61, one end of the relay coil A1, and the collector of the transistor Tr63. The collector of transistor Tr64 is connected to the cathode of Zener diode D62, the other end of relay coil A1, and the collector of transistor Tr65. The anode of the Zener diode D61 is the Zener diode D6.
2 anodes. Transistor Tr61,
Tr63. Tr65. Each emitter of Tr66 is grounded. The terminal SSN is connected to a resistor R and connected to the pace of a transistor Tr65 via a resistor R67. terminal S
SF is connected to the pace of the transistor Tr63 via a resistor R65, and is connected to the pace of the transistor Tr63 via a resistor R68.
Connected to 66 paces.

The operation of this circuit will be explained below. The signals applied to the terminals S and MN are applied to the connection point between the resistors R51 and R52 and to one end of the resistor R57. As a result, the transistor Tr51 turns on, and then the transistor Tr5
2 turns on. Further, the signal applied to the terminal SMN turns on the transistor Tr55. Therefore, a coil current flows through the relay coil A2 in a direction that turns on the relay switch a2 shown in FIG.

Next, the signal applied to the terminal SMF is applied to the gate of the transistor Tr53 via the resistor R55, turning on the transistor Tr53. Further, the signal applied to the terminal SMF is applied to the base of the transistor Tr56 via the resistor R58, turning on the transistor Tr56. When the transistor Tr56 is turned on, the transistor T
r54 is also turned on. Transistor Tr53. When Tr54° Tr56 is turned on, a coil current flows through the relay coil A2 in a direction that turns off the relay switch a2.

Next, the signal applied to the terminal SSN is applied to the pace of the transistor Tr61 via the resistor R62, turning on the transistor Tr61, and then turning on the transistor Tr62.
Turn on. Further, the signal applied to the terminal SSN is applied to the transistor Tr65 via the resistor R67, turning on the transistor Tr65. As a result, a coil current flows through the relay coil A1 in a direction that turns on the relay switch a1.

Next, the signal applied to the terminal SSF is applied to the pace of the transistor Tr63 via the resistor R65, turning on the transistor Tr63. Further, the signal applied to the terminal SSF is applied to the pace of the transistor Tr66 via the resistor R6B, turning on the transistor Tr66,
Subsequently, the transistor Tr64 is turned on. As a result, a coil current flows through the relay coil A1 in a direction that turns off the relay switch a1.

As described above, the signal applied to the terminal SMN causes a current to flow through the relay coil A2 in the direction of turning on the relay switch a2, turning on the relay switch a2, and the signal applied to the terminal SMF causes the relay switch a2 to turn on. A current flows through the relay coil A2 in the direction of turning off the relay coil A2, and the relay switch a2 is turned on. Terminal SSN
The signal applied to terminal SSF causes a current to flow through relay coil A1 in the direction of driving relay switch a1 on, turning on relay switch a1, and the signal applied to terminal SSF causing current to flow in the direction of driving relay switch a1 off. Current flows through relay coil A1, and relay switch a1 is turned off.

Effects As described above, according to the present invention, power consumption can be saved by generating each drive signal for turning on/off the first relay switch and the second relay switch a preset number of times. This also improves the reliability of the circuit.

, 4. Brief description of the drawings Fig. 1 is an electric circuit diagram for explaining the basic operation of an embodiment of the present invention, and Fig. 2 is a block diagram showing the overall electrical configuration of an embodiment of the present invention. 3 is an electric circuit diagram of an embodiment of the present invention, FIG. 4 is a timing chart for explaining the operation of the electric circuit of FIG. 3 when power is turned off, and FIG. FIG. 6 is a timing chart for explaining the operation when power is applied to the load in the electric circuit of FIG. 3, and FIG. FIG. 7 is a timing chart for explaining the operation for preventing a hit, and is an electric circuit diagram of a relay drive circuit connected to terminals SMN, SMF, and 5SNfSSF shown in FIG. 3, respectively.

al, a2-relay switch, D, D1-D4...diode, KO...AC power supply, L...load, T...
・Transformer, CI, C2...Capacitor, R, R1~
R5, R51 to R59, R61 to R69...Resistance, T
MI~TM4...Time limit circuit, DYI, DY2...
Delay circuit, Tr51 to Tr56. Tr61NTr66・
...Transistor, D51, D52. D61, D6
2... Zener diode, AI, A2... Relay coil, 1... Comparator, 2, 5, 9, 12, 13, 15
e 16 * 18 * 19-2. , 1 e 27
．． 30.40 m41.42,43...AND gate, 3,4,5at7.8,11,22,24,26,3
4,36°39...NOT gate, 6,10. ．． 14
, 17, 20.29.31. 38-OR gate, 23
,25*28.35,37・NOR gate, 33a,
33b...D flip-flop, 32...RS flip-flop agent Patent attorney Kei Nishi Department Figure 1 Figure 2 p 2 S! ? ! : Ushio B o,,,saq 3
M++J+J++'WN--Meeeee~1. -to 1.
-9ν-11 Figure 7 Procedures Amendment 1, Indication of the case Patent application 1983-23583 2, Name of the device AC switch circuit 3, Person making the amendment Relationship to the case Applicant Address Name (583) Matsushita Denko Co., Ltd. Representative 4, Agent Address: Shinkosan Building Kokusai EX, 1-13-38 Nishiki-cho, Nishi-ku, Osaka 0525-5985 IMTAPT
J Voluntary Amendment 6, Detailed Explanation of the Invention in the Specification Subject to Amendment, Drawing 7, Contents of Amendment (1) Specification/Letter Page 5, Line 9, "Voltage VOJ" has been replaced with "Load Current ILJ" correct.

(2) In the 17th line of page 5 of the specification, the word "voltage" is corrected to "load current."

(3) “Figure 5 0” on page 10, line 11 of the specification
The text has been corrected to ``See Figure 4.''

(4) On page 10, line 13 of the specification, “Figure 5 (2)
4) Correct the text "J" to "Figure 4 (24) J.

(5) "Voltage VO" on page 10, line 18 of the specification
The statement "Correct to load current ILJ.

(6) The second line of page 11 of the specification is corrected as follows.

Voltage vO from the opposite phase of the load current IL of the AC power supply EO
(7) In the 5th line of page 13 of the specification, the phrase ``rOR output'' is corrected to ``inverted signal of rOR output''.

(8) Lines 8 to 9 of page 14 of the specification are corrected as follows.

A of the output of the timing circuit T2, the output of the RS flip-flop 32, and the input signal p4 (9) In the 10th line of page 14 of the specification, "relay switch all" is corrected to "relay switch a2."

(10) In the specification, page 14, lines 11 to 12, "relay switch all" is corrected to "relay switch a2J."

Figure 4 has been corrected as shown in the attached sheet.

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Claims (1)

[Scope of Claims] Two first .C. The first relay switch has diodes connected in series, and the ON operation of the relay switch is such that the voltage waveform of the AC power source is in the first half period in the opposite direction of the diode. turn on the relay switch, and after a delay turn on the second relay switch during the forward half period of the diode,
Furthermore, the OFF operation of the relay switch is an AC switch circuit in which the above voltage waveform turns off the second relay switch during the forward half cycle of the diode, and later turns off the first switch during the reverse half cycle of the diode. In the above, a first relay drive circuit that turns on/off the first relay switch and a second I++7- animal motion circuit that turns on/off the second relay switch are each driven by an input signal from the outside. When the input signal is either high level or low level, the first
A first relay drive signal that turns on the first relay switch is sent from the relay drive circuit a predetermined number of times, and a second relay turn-on drive signal that turns on the second relay switch is sent from the second relay drive circuit in advance. A first relay off drive signal is sent out a predetermined number of times, and when the input signal is at the other level, a first relay off drive signal that turns off the first relay switch is sent out a predetermined number of times, and a second relay off drive signal is sent out a predetermined number of times.
An AC switch circuit characterized in that a second relay off drive signal for turning off a second relay switch is sent from the relay drive circuit a predetermined number of times.