JPS60166990A - Liquid crystal driving circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a liquid crystal drive circuit.

[Prior art]

In recent years, high bias and high duty circuits are often adopted in dynamic drive type liquid crystal drive circuits as costs become lower and functionality becomes higher.

[Problems with conventional technology]

As mentioned above, when the liquid crystal drive circuit becomes high bias and high duty, there is a problem that the circuit configuration becomes complicated.
Particularly in power supply circuits, a large number of boosted voltages are required, and the number of capacitors that are external components increases accordingly. This has been an obstacle for electronic wristwatches, which require miniaturization.

[Purpose of the invention]

The purpose of the present invention is to provide a liquid crystal drive circuit that has a simple circuit configuration that reduces the number of capacitors and can contribute to the miniaturization of small electronic devices such as electronic wristwatches.

[Key points of the invention]

In a liquid crystal driving circuit that boosts a battery voltage to obtain a boosted signal and dynamically drives a liquid crystal based on this boosted signal, the boosted signal is a predetermined voltage consisting of the battery voltage and a boosted voltage higher than the battery voltage. The liquid crystal drive signal dynamically drives the liquid crystal in synchronization with the output timing of a high boosted voltage of the pulse signal.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit configuration diagram of an electronic timepiece, and as shown in the figure, a timekeeping circuit section 1 that generates clock information, a power supply circuit section 2, a timing signal generation section 3, a common electrode drive circuit 4, a segment electrode drive circuit 5, Composed of a liquid crystal common electrode substrate 6, segment) [@A substrate 7 using a dynamic drive method.

Thus, the clock circuit 1 includes an oscillator 8, a frequency dividing circuit 9, and a counter 1.
It consists of a 0° decoder 11, and the oscillator 8 is, for example, a 327
A 68 Hz reference signal is generated and applied to the frequency divider circuit 9. Further, the frequency dividing circuit 9 divides the reference signal into, for example, a signal of IHz and supplies it to the counter 10, and also generates a divided signal f of various frequencies and supplies it to the timing signal generator 3, and also divides the frequency of the reference signal into a signal of, for example, IHz, and supplies it to the timing signal generator 3. is given to the power supply circuit 2.

The counter 10 counts the signal II (Z) to obtain time measurement data such as hours, minutes, and seconds, and provides it to the decoder 11.

The decoder 11 decodes the above clock data to obtain display data aata1 to datan, and sends them to the corresponding segment electrode input terminals of the segment electrode substrate 7 via the corresponding buffers 751 to 5n in the segment electrode drive circuit 5, respectively. The signals 5IG1 to s'han are given.

The power supply circuit section 2 has a battery 1 that generates a source voltage i, 5vt-1.
2. N-channel MOSFET (MOB field effect transistor) 13.14. P-channel MOSFET
15, an inverter 16, and a capacitor 17. The positive electrode side of the battery 12 is grounded (its voltage level is VO), and the P channel MO
It is connected to the drain of 8FIiT15, and the negative electrode side is (
(The voltage level is Vl) The above MO of N channel
It is connected to the source of 8FET13 and the drain of MOSFET14. In addition, the drain of MO8FIiT13 is connected to one end side of the capacitor 17, and the drain of MO8FIiT13 is connected to one end side of the capacitor 17.
:The source of T14 and the source of MO8FFi'['15 are both connected to the other end side of the capacitor 17. Furthermore, M.O.
The above signal S is connected to the gate of SFET 13 by inverter 16.
A signal S is applied directly to each gate of the MOSFETs 14 and 15. The output voltage VLO at one end of the capacitor 17 is supplied to the timing signal generator 3, the common electrode drive circuit 4, and the segment electrode drive circuit 5. Note that the voltage at the other end of the capacitor 17 is VC.

In addition, the clock circuit section 1 outputs the output voltage (vOlVl) of the battery engineer 2.
Driven by

The timing signal generator 3 receives the frequency divided signal f1 or the voltage V.
A timing signal &, 10X% 1 ay having a waveform as shown in FIG. 2 is generated based on LOSVl and is applied to the common electrode drive circuit 4. This common electrode drive circuit 4 is made up of four x7's 8, 19, 20, and 21. The timing signal a is input to both the buffers 18 and 21, the timing signal lax is input to the buffer 19, and the timing signal 1cy is input to the buffer 20. And the buffer 18 has voltages VL0 and v
By applying l to the buffer 21, an output voltage vIt is obtained, and by applying voltages v1 and vO to the buffer 21, an output voltage v01 is obtained. Furthermore, buffer 19.
20 outputs a common signal LOX or LOY by applying a voltage V, , V, , respectively, and supplies it to the corresponding common electrode input terminal of the common electrode substrate 6 .

The electrode structures of the common electrodes or segment electrodes of the common llttm board 6 and the segment electrode board 7 have a one-to-one correspondence, and as shown in the figure, the 10th digit of the hour digit has two electrodes, and the first digit has a digit. 7 electrodes in the mold, 2 dot electrodes for seconds display that flash at 1 second intervals, 11 minutes digit, 10th digit, 1
It consists of seven electrodes each shaped like a white letter. And X
side common signal L Gl: K or Y side common signal LOY and segment signals 81iiG1 to 8E G
n is applied, each electrode is dynamically driven (in this embodiment, % bias, % duty) to display time information. Note that voltages VLO and VO are applied to both buffers 75 to 5n in the segment electrode drive circuit 5.

Next, the operation of the above embodiment will be explained with reference to the time charts of FIGS. 2 to 4. The oscillation circuit 8 in the clock circuit section 1 constantly generates a reference signal of 32768 Hz and supplies it to the frequency divider circuit 9. Therefore, the frequency divider circuit 9 divides the frequency of the reference signal and provides the IHvs signal to the counter 10, and also provides the divided signal f of various frequencies to the timing signal generator 3, and further divides the frequency of the reference signal and provides the signal of IHvs to the timing signal generator 3. A signal S with a frequency of 192 Hz varying between 70 and 171 is applied to the power supply circuit section 2. The counter 10 counts the IHss signal to obtain time data such as hours, minutes, and seconds, and provides the data to the decoder 11. The decoder 11 decodes this clock data to obtain display data datal-datan and supplies them to the corresponding buffers 51-5n in the segment electrode drive circuit 5.

On the other hand, in the power supply circuit section 2, the signal S with a frequency of 192H2 is inputted at the voltage v1 level during the first half period of one cycle and at the voltage v09 level during the second half period, so that in the first half period (voltage Vl) N channel Mo2. The FET 14 is turned ONt, and the N-channel and P-channel MO81FETs 13.15 are turned OFF. Therefore, the boost capacitor 17 is charged to the voltage v1 of the battery 12, and the voltage VLO becomes equal to 1. Next, the second half % period (voltage 'yO) "c'!; t, MO8FIE'l
'14 is 0FFL, MO8FI'l'13.15 are both turned ON. Therefore, the above voltage VLO is V2 (V2=2
v1).

The timing signal generating section 3 generates a second
The timing signal a11C (, IC
y, and buffers 18 to 18 in the common electrode drive circuit 4
Give to 21. Therefore, from the common electrode drive circuit 4,
A common signal LOXSLOY as shown in FIG. 2 is generated. As can be seen from the drawing, in this case, the two cycle period of the signal S mentioned above is one cycle period of the common signals LOX and LOY.
Cycle period, i.e. display one cycle period (384Hz
). When the level of the signal 8 is vl, the common signals LOX, LOY, and the segment signal 81
The levels of G1 to SFIGm are also all set to Vl, and each electrode of the liquid crystal is set to a non-driven state. On the other hand, while the level of the signal S is VO, the level of the common signals LOX and LOY becomes V2 once, and at that time the level becomes vo.
Any segment signal 8F, G, ~S FJG
The electrode supplied with n is set to a driving state and is turned on.

Signals X-81 and X-82 in the time chart of FIG. 4 indicate voltage waveforms applied to the electrodes of the liquid crystal that is turned off or turned on, respectively.

Although the above example uses % bias and % duty, the present invention can also be applied to other drive systems.

〔Effect of the invention〕

As explained above, the present invention provides a liquid crystal drive period using a signal at a second voltage level higher than a reference first voltage level, an intermediate level between the first and second voltage levels, and a second voltage level at the first voltage level.
This is a liquid crystal drive circuit that generates a common signal in the liquid crystal dynamic drive system, in which the liquid crystal non-drive period by a voltage level signal is used as a signal for one display cycle, and a segment signal for this common signal. This has the advantage of reducing the number of capacitors and simplifying the circuit configuration, contributing to the miniaturization and cost reduction of small electronic devices such as wristwatches.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIGS.
The figure is a diagram showing a time chart. 1... Timing circuit section, 2... Power supply circuit section, 3... Timing signal generation section, 4... Common electrode drive circuit, 5... Segment Electrode drive circuit, 6... Common electrode substrate, 7... Segment electrode substrate, 12...-'* pond, 13.14.1
5...MO8FE'l', 16...Inverter, 17...Capacitor, 18-21...
Mountain buffer. Patent applicant Casio Computer Co., Ltd. Figure 2 Figure 3

Claims (1)

[Claims] A liquid crystal drive circuit comprising a battery voltage, a boosting means for boosting the battery voltage to obtain a boosted signal, and a means for obtaining a liquid crystal drive signal for dynamically driving a liquid crystal based on the boosted signal obtained by the boosting means. wherein the boost signal obtained by the boost means is a pulse signal with a predetermined period consisting of the battery voltage and a boost voltage higher than the battery voltage;
A liquid crystal driving circuit, wherein the liquid crystal driving signal dynamically drives the liquid crystal in synchronization with the output timing of a high boosted voltage of the pulse signal.